JPH08185358A - Microprocessor - Google Patents

Abstract

PURPOSE: To shorten time to be required for an MPU stop request up to an MPU operation stop. CONSTITUTION: When a flag for permitting/inhibiting the generation of a cache flash signal is '1', a cache flash circuit generates a cash flash signal FLS when a clock is raised twice after inactivating a sleep signal supplied from the external and supplies the signal FLS to the clear input terminals CLR of respective valid flags V1 to Vn through respective transfer gates 61 to 6n. When the contents L1D to LnD of lock flags corresponding to the valid flags V1 to Vn are a value '0' indicating a rewrite permission, the gates 61 to 6n are opened. The cache flash circuit generates the signal FLS also at the time of executing an MPU stop instruction or a cache flash instruction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor including a cache.

[0002]

2. Description of the Related Art Microprocessors used in portable electronic devices and control devices are required to have low power consumption for battery driving and heat countermeasures, and the operation of the microprocessor is stopped during an unnecessary period. In this type of microprocessor, a cache built-in type microprocessor capable of high-speed operation is connected to a bus master and an external memory via a bus, and the bus master writes data to the external memory while the microprocessor is not operating. Will cause a difference with the data in the cache.

In order to prevent this, some microprocessors have a bus snoop function of monitoring a write to an external memory and reflecting the write in a cache. However, since the cache must be operated even while the microprocessor is not operating, the effect of reducing power consumption becomes small. In a microprocessor having no bus snoop function, a process shown in FIG. 6 is performed by software in order to prevent the above data difference. Hereinafter, the numerical value in the parenthesis represents the step identification number in the figure.

(1, 2) When a microprocessor stop instruction is executed or a stop interrupt request is issued to the microprocessor during normal operation, the following processing is performed. (3) To invalidate the data in the cache memory, first turn off the cache. Also, the index address IX is cleared to zero. (4) Write "0" in the valid flag V designated by the index address IX to obtain the index address IX.
Invalidates the data in the cache memory specified by.

(6) If the index address IX is not equal to the final value n, the index address IX is incremented and the process returns to step 4. (7) When IX = n, the clock inside the microprocessor is turned off to stop the operation of the microprocessor. (8) When the stop release request is issued to the microprocessor, the clock in the microprocessor is turned on.

(9) The cache is turned on, and the normal operation of step 1 is returned to.

[0007]

The above processing takes a long time from the microprocessor stop request to the microprocessor operation stop for the following reason. (1) Since it is necessary to turn off the cache and fetch the instruction in the external memory into the microprocessor, a memory wait occurs.

(2) It is necessary to repeat the operations of steps 4 to 6 for all index addresses IX. Further, it is necessary to create an extra program for performing the processing of FIG. 6 and secure the program area in the external memory. In view of the above problems, an object of the present invention is to provide a microprocessor that can shorten the time from the microprocessor stop request to the microprocessor operation stop and that does not require a program for operating the valid flag. To do.

[0009]

According to the first aspect of the present invention, a micro computer having a cache having a cache memory and a valid flag holding a binary value indicating valid / invalid of stored contents for each address of the cache memory. In the processor, the valid flag has an initialization input for forcing its held value to a value indicating the invalidity,
It has a cache flash circuit which generates a cache flash signal after the sleep signal supplied from the outside becomes active and supplies it to the initialization input terminal.

According to the first aspect of the invention, the cache flush signal causes the valid flag to have a value indicating invalidity.
The time from the microprocessor stop request to the stop of the microprocessor operation can be shortened, and the program for operating the valid flag becomes unnecessary. In the first aspect of the first invention, the cache flush circuit is
After the sleep signal becomes active, the sleep signal becomes inactive, and then a cache flush signal is generated and supplied to the initialization input terminal.

In a second aspect of the first invention, the cache has a lock flag for each of the valid flags, and is connected between the initialization input end of the valid flag and the output end of the cache flush circuit. The gate is opened when the content of the lock flag corresponding to the valid flag is a value indicating permission for rewriting. According to the second aspect, it is possible to inhibit / permit the lock flag value from changing the valid flag to a value indicating invalid by the cache flush signal.

According to the second aspect of the present invention, a micro having a cache memory and a cache having a valid flag for storing valid / invalid of stored contents for each address of the cache memory, the cache memory and a decoder for addressing the valid flag are incorporated. In a processor, a cache flash circuit that generates a cache flash signal after an externally supplied sleep signal is activated, and for each output end of the decoder, the output end and the gate of the valid flag corresponding to the output end A logic gate connected to the control input and supplying the output of the decoder or the cache flush signal to the gate control input.

Also according to the second aspect of the present invention, since the valid flag becomes a value indicating invalid by the cache flush signal, the time from the microprocessor stop request to the microprocessor stop can be shortened and the valid flag can be operated. A program for doing this is unnecessary. In the second aspect of the first invention or the second invention, the cache has a lock flag for each of the valid flags, and the cache includes the logic gate and the gate control input terminal of the valid flag corresponding to the logic gate. It has a gate connected between them and opened when the content of the lock flag corresponding to the valid flag is a value indicating permission of rewriting.

Also according to the second aspect, it is possible to prohibit / permit the lock flag value from changing the valid flag to a value indicating invalid by the cache flush signal. In the third aspect of the first or second invention, the cache flash circuit has a flag for permitting / prohibiting the generation of the cache flush signal. According to the third aspect, when the bus master is not connected to the microprocessor, or when the bus master is connected and the memory is not written to while the microprocessor is stopped, a value indicating prohibition is set in the flag. By setting it, the operation after the microprocessor is released can be speeded up, and it is not necessary to select the microprocessor with or without the cache flush function for each application.

In the fourth aspect of the first or second invention, the cache flush circuit generates the cache flush signal even when a microprocessor stop instruction or a cache flush instruction is executed. According to the fourth aspect, the effect of the first or second invention can be obtained even if the microprocessor stop instruction or the cache flush instruction is executed, so that the instruction efficiency is high.

In the fifth aspect of the first or second invention, the cache flush circuit generates the cache flush signal even when the bus right is released. According to the fifth aspect, the effect of the first or second invention can be obtained even when the microprocessor releases the bus right, which is efficient. The cache flash circuit includes a plurality of cascaded D flip-flops, and a logic gate that generates the cache flash signal according to the values of a data input terminal and a data output terminal of the final D flip-flop. The sleep signal is supplied to the data input terminal of the D flip-flop in the first stage, and the clock from the outside is supplied to the gate control input terminal of the D flip-flop in each stage. According to this structure, a plurality of stages of D flip-flops and a simple logic gate generate an appropriate cache flash signal according to the change of the sleep signal, and the structure of the cache flash circuit is simplified.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1A shows the configuration of a low power consumption type system including a microprocessor, such as a microcomputer, which is used in portable electronic devices and control devices.

Microprocessor 1 with a built-in cache
0 is a bus master 11, a memory 12, a system management unit 13 and an I / O interface 14.
Are connected via the bus 15. Bus master 11
Is another microprocessor, a DMA controller, or the like, and can access the memory 12. Memory 1
2 includes only RAM or ROM in this.

The system management unit 13 is
When the microprocessor stop request signal from the I / O interface 14 becomes active, the sleep signal * S
LP is activated and supplied to the microprocessor 10. FIG. 1B shows an internal configuration of the microprocessor 10. The microprocessor 10 includes a microprocessor core 20, an instruction cache 21, and a bus control circuit 22.
Is connected by an instruction bus 23, and the microprocessor core 20, the data cache 24, and the bus control circuit 22 are connected by a data bus 25. Instruction bus 23
The data bus 25 is connected to the bus 15 via the bus control circuit 22. The clock CLK0 and the sleep signal * SLP are externally supplied to the microprocessor core 20 and the cache flash circuit 26. The microprocessor core 20 supplies a clock CLK1 to the instruction cache 21, the bus control circuit 22, and the data cache 24 in order to operate them as necessary.

When the sleep signal * SLP from the outside becomes active or the cache flush signal FLS2 from the microprocessor core 20 becomes active, the cache flush circuit 26 outputs the cache flush signal FLS to the instruction cache 21 at the timing described later.
And the data cache 24. The cache flush signal FLS2 becomes active when the microprocessor core 20 executes a microprocessor stop instruction or a cache flush instruction.

A schematic structure of the data cache 24 is shown in FIG. The storage unit 30 includes a tag table 30T having tags TAGi and i = 1 to n, a valid flag column 30V having a valid flag (valid / invalid flag) Vi corresponding to each tag TAGi, and a lock corresponding to each tag TAGi. Flag L
A lock flag string 30L having i (rewrite prohibition / permission flag) and a cache memory 30W having words Wi1 and Wi2 corresponding to each tag TAGi.

The address A is divided into a tag address TAG, an index address IX and a word select bit W. The index address IX is the decoder 31
Is decoded and the i-th entry point of the storage unit 30 is designated, the contents of the tag TAGi, the valid flag Vi and the lock flag Li are read, and one of the word Wi1 and the word Wi2 is selected by the word select bit W. The contents are read out.

Contents of tag TAGi and tag address TAG
And are compared by the comparator 32, and if they match,
The output of the comparator 32 goes high. On the other hand, the content of the valid flag Vi is supplied to the control input terminal of the transfer gate 33. When the content of the valid flag Vi is '1', the transfer gate 33 is opened, the coincidence detection signal (cache hit) from the comparator 32 is supplied to the control input terminal of the transfer gate 34, and the transfer gate 34 is opened. , The content of the selected word Wi1 or word Wi2 is retrieved.
When the comparator 32 detects a mismatch, or the content of the valid flag Vi is “0” (invalid) even if a match is detected, when the content of the lock flag Li is “0”, the tag address TAG is the tag. Written to TAGi, valid flag V
The content of i is set to "1", and the data (instruction code) read from the memory 12 is written in the word Wi1 or the word Wi2 selected by the word select bit W.

The data cache 24 is similar to the instruction cache 21 and its explanation is omitted. FIG. 4 shows a configuration example of the valid flag column 30V. Each of the n outputs of the decoder 31 has a transfer gate 41 connected in series.
4n and 51-5n are supplied to the clock input terminals CK of the valid flags V1 to Vn. Valid flags V1 to V
Reference numeral n is a latch circuit, which is in a latch mode when the clock input terminal CK is at a high level and is in a through mode when the clock input terminal CK is at a low level. The valid flag write data is supplied to the data input terminal D of the valid flags V1 to Vn. The cache flush signal FLS is supplied to the clear input terminals CLR of the valid flags Vi to Vn via the transfer gates 61 to 6n, respectively. Transfer gate 41 to
The read / write signal R / W is supplied to the control input terminal of 4n, and the content LiD of the lock flag Li is supplied to the control input terminals of the transfer gates 5i and 6i (i = 1 to n). The data taken out from the non-inverting output terminal Q of the valid flags V1 to Vn is supplied to the selector 60, and the data selected by the output of the decoder 31 is read from the selector 60.

In the case of reading, the read / write signal R
/ W is set to a high level, the transfer gates 41 to 4n are closed, and the output of the valid flag Vi is selected by the selector 60 and read. In the case of writing, when the read / write signal R / W is set to the low level, the transfer gates 41 to 4n are opened, and the content LiD of the lock flag Li is '0' (rewrite permission), the i-th decoder 31 Is supplied to the clock input terminal CK of the valid flag Vi, and the valid flag V
The data to the data input terminal D of i is written in the valid flag Vi.

In the case of cache flush, the contents LiD of the lock flag Li are all "i" of "0".
The transfer gate 6i is opened, and a positive pulse cache flash signal FLS is applied to the clear input terminal CLR of the valid flag Vi.
Is supplied, and the content of the valid flag Vi is cleared to zero (invalid). Therefore, the program shown in FIG. 1 is unnecessary, and the iterative process of steps 4 to 6 of FIG. 6 is simultaneously achieved by one positive pulse FLS. Since this effect can be obtained even by executing the microprocessor stop instruction or the cache flush instruction, the instruction efficiency is high.

FIG. 2A shows a configuration example of the cache flush circuit 26. Cache flash circuit 26
Are connected in cascade with the D flip-flops 71 to 73, and
The signal at the data input terminal D and the non-inverting output terminal Q of the flip-flop 73 and the output of the flag 74 are AND gates 75.
1 and the output FLS1 of the AND gate 75,
The cache flush signal FLS2 from the microprocessor core 20 is supplied to the OR gate 76, and the cache flush signal FLS is taken out from the OR gate 76.

Next, the operation of the first embodiment constructed as described above will be explained based on the timing chart shown in FIG. Initially, the sleep signal * SLP is at a high level, and the D flip-flop 71 is driven by the clock CLK0.
Output of ~ 73 is high level, cache flush signal F
LS1 is at a low level.

When the sleep signal * SLP changes to the low level, the microprocessor core 20 turns off the instruction cache 21 and the data cache 24, then stops the clock CLK1 and releases the bus 15. Even if the sleep signal * SLP goes low, D
In the flip-flop 73, the data input terminal D never goes low and the non-inverted output terminal Q never goes high, so the cache flush signal FLS1 remains low. D flip-flops 71 to 71 depending on the clock CLK0
73 is stable when these non-inverting output terminals Q are at a low level.

In FIG. 1A, when the microprocessor stop request signal becomes inactive (the microprocessor stop release signal becomes active), the sleep signal * S
LP transitions to high level. The non-inverting output terminal Q of the D flip-flop 71 transitions to a high level at the rising edge of the clock CLK0, and D at the next rising edge of the clock CLK0.
The non-inverting output terminal Q of the flip-flop 72 transits to the high level. At this time, if the flag 74 is set to "1" and its output is at a high level, the cache flush signals FLS1 and FLS are at a high level, and the cache flush described above in FIG. 4 is performed. Then, the microprocessor core 20 turns on the cache as needed (by the program) and restarts the operation of the clock CLK1.

This cache flush prevents malfunctions due to the contents of the memory 12 being rewritten by the bus master 11 while the operation of the microprocessor 10 is stopped. When the bus master 11 shown in FIG. 1 is not connected, or when the bus master 11 is connected but writing to the memory 12 is not performed while the microprocessor is stopped, the flag 74 is set to "0". As a result, since the cache flush is not performed, the operation after the microprocessor is released is speeded up.

[Second Embodiment] FIG. 5 shows a structure of a second embodiment corresponding to FIG. This valid flag string 30VA is
Instead of the transfer gates 61 to 6n shown in FIG.
OR gates 81 to 8n are connected between the output ends of the OR gates and the input ends of the transfer gates 41 to 4n, respectively.
One of the input ends of ~ 8n is commonly connected and the cache flush signal FLS is supplied to it. The other points are the same as in the first embodiment.

In the case of reading and writing, the above first
Same as the embodiment. In the case of cache flush, the valid flag write data is set to "0", the read / write signal R / W is set to low level, and the transfer gates 41 to 41 are transferred.
4n is opened and the content LiD of the lock flag Li is "0".
For all i, the transfer gate 6i is opened, the cache flush signal FLS is supplied to the clock input terminal CK of the valid flag Vi, and "0" is written in the valid flag Vi.

The present invention includes various modifications other than the above. For example, the D flip-flop in FIG. 2A may have two or more stages. Further, the cache flush circuit may be configured to generate the cache flush signal during the period when the sleep signal is active. The valid flag in FIGS. 4 and 5 may be configured by a D flip-flop instead of the latch circuit. A logic gate may be used instead of the transfer gate in FIGS. Further, the configuration without the flag 74 in FIG. 2A or the configuration without the lock flag Li in FIG. 3 may be used.

[0035]

As described above, in both of the first and second aspects of the invention, the valid flag becomes a value indicating invalidity by the cache flush signal, so that the time from the microprocessor stop request to the microprocessor operation stop can be reduced. There is an effect that it can be shortened and a program for operating the valid flag becomes unnecessary.

According to the second aspect of the first or second aspect of the invention, it is possible to inhibit / permit the value of the lock flag from changing the valid flag to the value indicating invalidity by the cache flush signal. Third aspect of the first or second invention
According to the aspect, when the bus master is not connected to the microprocessor, or when the bus master is connected and the memory is not written to while the microprocessor is stopped, a value indicating prohibition is set in the flag. As a result, it is possible to speed up the operation after the microprocessor is released and it is not necessary to select a microprocessor with or without a cache flush function for each application.

According to the fourth aspect of the first or second invention, the effect of the first or second invention can be obtained even if a microprocessor stop instruction or a cache flush instruction is executed, so that the instruction efficiency is high. Produce an effect. According to the fifth aspect of the first or second aspect of the invention, the effect of the first or second aspect of the invention can be obtained even when the microprocessor releases the bus right, so that there is an effect of being efficient.

[Brief description of drawings]

FIG. 1A is a block diagram of a system including a microprocessor, and FIG. 1B is a block diagram showing an internal configuration of the microprocessor of FIG.

2A is a diagram showing a configuration example of a cache flash circuit in FIG. 1B, and FIG. 2B is a timing chart showing an operation of the first embodiment.

FIG. 3 is a schematic configuration diagram of a cache.

FIG. 4 is a diagram showing a configuration example of a valid flag string.

FIG. 5 is a diagram showing a configuration example of a valid flag string of the second embodiment.

FIG. 6 is a flowchart showing processing when stopping the operation of a conventional microprocessor.

[Explanation of symbols]

10 Microprocessor 11 Bus Master 12 Memory 20 Microprocessor Core 21 Instruction Cache 24 Data Cache 26 Cache Flash Circuit 30 Storage Unit 30T Tag Table 30V, 30VA Effective Flag Sequence 30L Lock Flag Sequence 30W Cache Memory 31 Decoder 32 Comparator 33, 34, 41- 4n, 51-5n, 61-6n Transfer gate 71-73 D flip-flop 74 flag

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hideaki Hideaki 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Hiroyuki Fujiyama 1015, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited

Claims (8)

[Claims] 1. A microprocessor including a cache having a cache memory and a valid flag holding a binary value indicating valid / invalid of a stored content for each address of the cache memory, wherein the valid flag holds the held value. A cache flash circuit having an initialization input terminal for forcibly setting the value indicating the invalidity and generating a cache flash signal after the sleep signal supplied from the outside becomes active and supplying the cache flash signal to the initialization input terminal. , A microprocessor having: 2. The cache flush circuit generates a cache flush signal and supplies it to the initialization input terminal after the sleep signal becomes inactive after the sleep signal becomes active. The microprocessor according to claim 1, wherein 3. The cache has a lock flag for each of the valid flags, is connected between the initialization input end of the valid flag and the output end of the cache flush circuit, and corresponds to the valid flag. 3. The microprocessor according to claim 1, further comprising: a gate opened when the content of the lock flag is a value indicating permission of rewriting. 4. A microprocessor incorporating a cache having a cache memory, a valid flag for storing valid / invalid of stored contents for each address of the cache memory, a cache memory and a decoder for addressing the valid flag, A cache flash circuit that generates a cache flash signal after an externally supplied sleep signal is activated, and for each output end of the decoder, the output end and the gate control input end of the valid flag corresponding to the output end. And a logic gate connected between the gate control input terminal and the output of the decoder or the cache flush signal. 5. The cache has a lock flag for each of the valid flags and is connected between the logic gate and the gate control input terminal of the valid flag corresponding to the logic gate. 5. The microprocessor according to claim 4, further comprising: a gate opened when the content of the lock flag corresponding to is a value indicating permission of rewriting. 6. The microprocessor according to claim 1, wherein the cache flush circuit has a flag for permitting / prohibiting generation of the cache flush signal. 7. The cache flush circuit according to claim 1, wherein the cache flush circuit generates the cache flush signal even when a microprocessor stop instruction or a cache flush instruction is executed. Microprocessor. 8. The cache flush circuit generates the cache flush signal even when the bus right is released, according to any one of claims 1 to 6.
Microprocessor described in one.