JPH0817236B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a switching element,
The present invention relates to an insulating gate type field effect transistor used for display devices such as integrated circuits and liquid crystals.

[0002]

2. Description of the Related Art Conventionally, an insulated gate field effect transistor of any type has been composed of a semiconductor portion forming a source region, a channel region and a drain region. Further, it is usual that the semiconductor forming the source region and the channel region and the semiconductor forming the drain region and the channel region are in direct contact with each other.

However, in the conventional insulated gate field effect transistor of the type in which the source region and the channel region are in contact with each other and the drain region and the channel region are in contact with each other, there is a problem of reverse leakage from the drain region to the source region and the drain withstand voltage is low. I have a problem.

[0004] The reverse leakage problem from the drain region to the source region, the curve Must be in the gate voltage as the original, as shown in FIG. _{2 (A) (V G)} - drain current of (I _D) In reality, the relationship causes a curve as shown in (B) due to reverse leakage from the drain region to the source region.

This phenomenon occurs under a gate voltage condition where a channel should not be originally formed, that is, a threshold voltage (V
_th ) Even under the following conditions, when the voltage between the source and the drain is raised to some extent, a phenomenon in which the drain current sharply increases (punch through current) occurs.

This phenomenon is explained to be caused by the influence of the reverse bias voltage at the drain junction on the source junction. This punch-through current flows between the source and drain along a path considerably deeper than the channel surface. Therefore, punch-through current can be prevented by increasing the impurity concentration along this path and increasing the resistance.

Further, the low drain withstand voltage means that the drain current (I _D ) which should originally have a sharp characteristic as shown in FIG. 3A under the condition of being lower than the threshold voltage. Figure 3 shows the relationship between the drain voltage and the drain voltage (V _D ).
This causes the characteristic of drawing a gentle curve as shown in (B). This cause is also due to the occurrence of the punch-through current described above.

V _D -I as shown in FIG.
_The insulated gate field effect transistor exhibiting the _D characteristic is in a slow leak state in which the drain current gradually flows even when a voltage equal to or lower than the threshold voltage is applied to the gate electrode, that is, even in a completely OFF state. As a result, there is a problem in the performance and reliability of the switching element.

As a method for improving the problem of punch-through current due to the drain withstand voltage, that is, the low insulation between the source and the drain, hydrogen as shown in FIG. 4, which is called a light-doped drain (LDD) technique, is used. There is a method of providing the offset gate region 49 which is the added semiconductor layer. FIG. 4 shows an insulating gate type including a quartz substrate 41, a polycrystalline silicon thin film 42, a silicon oxide film 43, a polycrystalline silicon electrode 44, a source region 45, a drain region 46, an aluminum electrode 47, and an offset gate region 49. It is a field effect transistor. The offset gate region is provided to alleviate the concentration of the electric field at this portion. There is also a method of providing a region lightly doped with an impurity imparting the same conductivity type as the source and drain at the same position as the offset gate region. This method is also a measure for relaxing the electric field concentration in the boundary region between the channel and the gate or the channel and the source. However, this method could not solve the problem of diffusion of hydrogen into the channel region and the problem of diffusion of impurities imparting conductivity type from the source and drain.

[0010]

The problems to be solved by the present invention include the problem of reverse leakage of current from the drain region to the source region and the low drain withstand voltage in the conventional insulated gate field effect transistor. Is a problem.

[0011]

According to the present invention, in an insulated gate field effect transistor, at least near a boundary between a source region and a semiconductor film under a gate electrode and near a boundary between a drain region and a semiconductor film under a gate electrode. A semiconductor device having a region in which at least one element selected from carbon, nitrogen, and oxygen is added to either one of them.

The vicinity of the boundary in the present invention means a portion (physical junction) where semiconductors (for example, I-type semiconductor and N-type semiconductor, P-type semiconductor and N-type semiconductor) having different characteristics (characteristics) are in contact with each other and a portion in contact therewith. Is an electrical junction portion in the vicinity of, or in the case where semiconductors having different properties are in contact with each other. The electrically coupled portion means a portion where the electric field is the strongest in which an electric interaction is performed through the place, or a joined portion as an electronic phenomenon caused by a difference in impurity concentration or a kind of impurity. is there.

One of the inventions disclosed in the present specification has a source region, a channel forming region, and a drain region made of silicon, and carbon, nitrogen, and nitrogen are provided near the boundary between the source region and the channel forming region. A region to which at least one kind of element selected from oxygen is selectively added is provided, and near the boundary between the channel forming region and the drain region, at least one selected from carbon, nitrogen, and oxygen is provided. A region to which one kind of element is selectively added is provided, and the two regions to which the element is selectively added have energy band widths of the source region, the channel forming region, and the drain region. It is characterized by having a larger energy band width.

According to another aspect of the invention, there is provided a source region, a channel forming region and a drain region made of silicon, and carbon is provided near a boundary between the channel forming region and the drain region.
A region to which at least one element selected from nitrogen and oxygen is selectively added is provided, and two regions to which the element is selectively added are the source region, the channel forming region, and the drain. The region is characterized by having an energy band width larger than the energy band width.

The insulated gate type field effect transistor having the structure of the present invention includes, for example, the glass substrate 1, the silicon oxide base film 38, the source region 5 ', the channel region 7', the drain region 6 ', and the gate oxide shown in FIG. An N-channel TFT composed of a silicon oxide film 3 ', which is a film, a gate electrode 4, an insulator 8, a source electrode 9', and a drain electrode 9 ", and includes a source region 5'and a semiconductor film 7 below the gate electrode. A carbon-added region “a” is provided along the source and drain region directions with the boundary 111 with the “(channel forming region in this case)” and the boundary 112 between the drain region and the semiconductor film 7 ′ as ends. It is a thing. In this example, the semiconductor film below the channel is the channel formation region. Further, in the manufacturing method of this example, phosphorus, which is an impurity imparting N-type conductivity, is implanted by the ion implantation method using the gate electrode 4 as a mask to form the source 5 ′ drain 6 ′ region having the N-type conductivity type. It is a thing. Therefore, the source 5'and drain 6'regions exist up to the boundaries 111 and 112, and the carbon-added region "II" is provided in the drain 6'region and the source 5'region.

An N-channel type T having such a configuration
The energy band structure of FT is schematically shown in FIG. In this case, it is the boundary between the source and the channel and the drain and the channel shown in FIG.
Since carbon-added regions II are provided from the regions 1 and 112 to the source 5'and drain 6'regions, the portion with a large band gap (52 in FIG. 5) is depleted due to the addition of carbon. It will be provided on the source and drain sides of the layer.

With the above structure, even if an electric current leaks in the opposite direction from the drain region 51 to the channel region 53 in FIG. 5, at least one element of carbon, nitrogen and oxygen (in this case, in this case). Since there is a bandgap crest 52 in the region where carbon is added, for example, 54 carriers cannot go to the channel region 53.
Therefore, in this case, even if a negative voltage is applied to the gate, the reverse leakage as shown in FIG. 2B does not occur and the ideal gate voltage (V _G ) as shown in FIG. 2A is generated. A drain current ( _ID ) relationship can be obtained.

Further, the width of the band gap of 52, which is a region to which at least one kind of element among carbon, nitrogen and oxygen shown in FIG. 4 is added, serves as a potential barrier and the drain breakdown voltage can be increased. The result, conventional current relationship becomes the characteristic as shown in FIG. 3 (B) for results in slow leak by not a little gate current (I _G) and the drain voltage (V _D) for the punch-through current Figure 3
It can be improved as in (A). Further, when the structure of the present invention is adopted, carbon, nitrogen, and oxygen bind to the dangling bonds in the carrier generation region (in this case, the boundaries 111 and 112 vicinity) and neutralize, so that the recombination center density is reduced. Therefore, the characteristics as a device can be improved.

The width of the bandgap crest 52 is to change the thickness in the lateral direction (direction parallel to the war connecting the source, channel and drain) of the carbon-doped region I'ro in FIG. The height of the peak can be controlled by changing the addition concentration. As described above, the present invention can be achieved under the technical idea of mitigating the electric field concentration, which is conceptually completely different from the aforementioned light-doped drain (LDD) technology.

A source region and a semiconductor region below the gate electrode,
By adding carbon, nitrogen, and oxygen between the drain region and the semiconductor region below the gate electrode, the semiconductor forming the source, drain, and channel regions is formed near the boundary between the source, drain region and channel region. A region having a wide energy band gap (for example, a portion 52 in FIG. 4) is a region made of silicon carbide, silicon nitride, and silicon oxide by adding the above-mentioned carbon, nitrogen, and oxygen when silicon is used as a semiconductor. Becomes Silicon carbide has a structure represented by Si _X C _1-X (0 ≦ X <1), and silicon nitride has a structure represented by Si ₃ N _4-X (0 ≦ X <4).
In the structure represented by, as the silicon oxide, SiO _2−X (0 ≦
A configuration represented by X <2) can be used.

Further, conventionally, when polycrystalline silicon or the like is used as a semiconductor, an impurity giving a P-type or N-type conductivity type drifts to a channel region via a grain boundary (GB) which is a grain boundary. Therefore, if an impurity that imparts one conductivity type is added to the source and drain regions at a high concentration in order to obtain high conductivity separation, the impurities drift to the channel region, and a device having stable performance cannot be obtained. It was However, in the case of the configuration of the present invention, since the region to which carbon, nitrogen, and oxygen are added becomes the blocking region, the drift of the impurity imparting one conductivity type from the source / drain region to the channel region does not occur. Therefore, even if a pentavalent impurity such as phosphorus is added to the source / drain regions in the case of an N-channel type and a trivalent impurity such as boron is added at a higher concentration than in the case of a P-channel type, diffusion of the impurity during thermal annealing is prevented. It can be prevented in the blocking region. As a result, σ = 10 ⁻¹ to 10
Source and drain regions having a conductivity of ³ (Ωcm) ⁻¹ can be obtained.

The feature of the present invention is not the conventional concept of alleviating the electric field concentration, but a wide band gap region containing carbon, nitrogen and oxygen is provided near the boundary between the channel and the drain where the electric field is concentrated. Therefore, the peak of the band gap that prevents carrier leakage is provided in this portion. In addition, the position of the crest of the band gap can be changed by changing the region to which carbon, nitrogen, and oxygen are added.

The constitution of the present invention is applied to each type of insulated gate field effect transistor such as stagger type, reverse stagger type, planar type and reverse planar type to improve the withstand voltage between the source and the drain and to punch through current. It goes without saying that the above can be prevented. Further, it goes without saying that the semiconductor device is not limited to the insulating gate type field effect transistor, but the present invention can be applied as a means for solving a problem (for example, a problem of slow leak) caused by local electric field concentration in the semiconductor device. Absent.

[0024]

[Embodiment] [Embodiment 1] The manufacturing process of this embodiment is shown in FIGS. In this embodiment, an N channel type T is formed on the glass substrate.
C / TFT with complementary FT and P-channel TFT
Here is a case of making. In addition, in the present specification, the reference numerals of the drawings used in the first embodiment are common throughout the present specification.

The complementary TFT in this embodiment is shown in FIG.
Is a complementary semiconductor device (C / TFT) composed of the P-channel field effect transistor 21 and the N-channel field effect transistor 11. FIG. 8 shows an example in which this C / TFT is used as a pixel drive element of a liquid crystal display device. In FIG. 8, the display section has a 2 × 2 matrix, and the peripheral circuit sections are shown at 16 and 17. One pixel 34 of this display unit connects gates of PTFT and NTFT to each other, and further, a line V _GG 2 in the Y-axis direction.
2 or V _{GG '} 22'. Also C / T
The common output of the FT is connected to the pixel electrode of the liquid crystal 12.
Input the PTFT (Vss side) to the X-axis direction line V _DD 1
8, connected to the input of NTFT the _{(V SS} side) Vss1
It is connected to 9.

Then, when V _DD 18 and V _GG 22 are "1", the liquid crystal potential 10 becomes "0", and when V _DD 18 is "1" and V _GG 22 is "0", the liquid crystal potential (V _LC ) 1
0 becomes "1". That is, V _GG and V _LC are “reverse phases”
Becomes Although shown in FIG. 8 is an inverter type C / TFT, if NTFT and PTFT are reversely arranged, it becomes a buffer type and V _GG and V _LC can be “in phase”. . Further, the peripheral circuit is made of such a TFT to which impurities such as oxygen are not added, and is sufficiently small (10 ¹⁹ cm ⁻³ or less), particularly C / TFT, and the mobility of each TFT is 20 to ²⁰⁰ cm ² /.
Vsec is set to operate at high speed.

The manufacturing process when the C / TFT shown in FIG. 7 is not manufactured will be described with reference to FIGS. 6 and 7. In FIG.
Magnetron RF (high frequency) on glass 1 such as AN glass and Pyrex glass that can withstand heat treatment at about 600 ° C
A silicon oxide film as the blocking layer (base film) 38 is formed to a thickness of 1000 to 3000 Å by using the sputtering method.

The process conditions are 100% oxygen atmosphere, film forming temperature 150 ° C., output 400-800 W, pressure 0.5 pa.
And Quartz or single crystal silicon is used as the target, and the film formation rate is 30Å / min.

On top of this, the total amount of oxygen, carbon or nitrogen is 7 × 10 ¹⁹ cm ^−3, preferably 1 × 10 ¹⁹ cm ^−3.
A silicon film added only below is formed by LPCVD (Low Pressure Vapor Phase) method, sputtering method or plasma CVD method. When forming by a reduced pressure vapor phase method, it is 450 to 550 ° C., which is 100 to 200 ° C. lower than the crystallization temperature, for example, 53.
Disilane (Si ₂ H ₆ ) or trisilane (Si
₃ H ₈ ) is supplied to the CVD apparatus to form a film. The pressure in the reaction furnace is 30 to 300 pa. Deposition rate is 30-100
Å / min. To control the threshold voltage (V _th ) of the NTFT and the PTFT to be approximately the same, boron is used in an amount of 1 × 10 ^{15 to} 5 × 10 ¹⁷ cm by using diborane.
^-3 may be added during film formation.

When the sputtering method is used, the back pressure before sputtering is set to 1 × 10 ⁻⁵ pa or less, single crystal silicon is used as a target, and argon is mixed with hydrogen at 50 to 80% by volume. For example, argon 20% by volume, hydrogen about 8
It is 0% by volume. The film forming temperature is 150 ° C. and the frequency is 13.
The frequency is 56 MHz, the sputter output is 400 to 800 W, and the pressure is 0.5 pa.

When a silicon film is formed by the plasma CVD method, the temperature is, for example, 300 ° C., and monosilane (SiH
₄ ) or disilane (Si ₂ H ₆ ) is used as a reactive gas. These were introduced into a PCVD device, and 13.5
A high frequency power of 6 MHz is applied to form a film.

In this embodiment, as shown in FIG. 6A, the semiconductor film 2 is formed only in a predetermined region on the first photomask.
2'is left and the other part is removed. The silicon oxide film 3 is further formed thereon under the same conditions as the underlying silicon oxide film 38 in the range of 500 to 2000 Å.
For example, it is formed to a thickness of 1000Å.

In the present embodiment, the source or drain region, which is a pair of impurity regions, has a very small amount of impurities such as oxygen, and crystallization proceeds more strongly. Further, a part thereof is provided over a lateral depth of 0 to 5 μm in the regions to be the source and the drain in the subsequent process. That is, ideally, it is preferable to set the width of the bandgap crest 52 in FIG. 5 to be as narrow as possible by setting it to 0. However, in consideration of a process problem, the width of the bandgap crest 52 is 0 to 5 μm in the lateral direction. It is preferable to provide over.

Thus, the amorphous silicon film 5 is formed.
After being manufactured to a thickness of 00 to 10000 Å (1 μm), for example 2000 Å, heat treatment, that is, thermal annealing is performed in a non-oxide atmosphere for 12 to 70 hours at a medium temperature of 500 to 750 ° C. that does not cause crystal growth. . For example, it is held at a temperature of 600 ° C. in a nitrogen or hydrogen atmosphere.

Since the silicon oxide film having an amorphous structure is formed on the substrate surface below the semiconductor film, no specific nuclei are present in this heat treatment and the whole is uniformly annealed by heating. That is, it has an amorphous structure at the time of film formation, and hydrogen is simply mixed therein. By this annealing, the semiconductor film in the channel formation region shifts from an amorphous structure to a highly ordered state, and a part thereof exhibits a crystalline state. In particular, a region having a relatively high degree of order during the film formation of silicon is particularly crystallized and tends to be in a crystalline state. However, since silicon existing between these regions forms a bond with each other, the silicon members pull each other. As a crystal, single crystal silicon (1
11) A (111) crystal peak having a lattice strain shifted to the low frequency side from the crystal orientation peak of 522 cm ^-1 is observed. The apparent grain size is 50 to 500 Å, which is similar to that of microcrystals, calculated from the half-width. However, in reality, there are many regions with high crystallinity and they have a cluster structure. It was possible to form a film having a semi-amorphous structure in which silicon was bonded to each other (anchoring).

For example, when the distribution in the depth direction is measured by SIMS (secondary ion mass spectrometry), oxygen is 3 × in the lowest region (the surface or a position apart from the surface (inside)) as an additive (impurity). 10 ¹⁹ cm ⁻³ and nitrogen 4 × 10 ¹⁷ cm ⁻³ are obtained. Also, hydrogen is 4 × 10 ²⁰
cm ^−3, which is 1 atom% when compared with silicon 4 × 10 ²² cm ⁻³ . This crystallization can be performed by heat treatment at 600 ° C. (48 hours) with a film thickness of 1000 Å when the oxygen concentration is 1.5 × 10 ²⁰ cm ⁻³ . When this is set to 5 × 10 ²⁰ cm ⁻³ , the film thickness is 0.3 to 0.5 μ.
If the thickness was increased to m, crystallization by annealing at 600 ° C. was possible, but if the thickness was 0.1 μm, heat treatment at 650 ° C. was necessary for crystallization. That is, the thicker the film thickness and the lower the concentration of impurities such as oxygen, the easier the crystallization was. As a result, this coating exhibits a state in which it may be said that it is substantially free of grain boundaries (referred to as (GB)). Carriers can easily move between each cluster through anchored points,
The carrier mobility is higher than that of so-called polycrystalline silicon in which GB is clearly present. That is, hole mobility (μh) = 10
˜50 cm ² / Vsec, electron mobility (μe) = 15˜
100 cm ² / Vsec is obtained.

On the other hand, when the film is polycrystallized by high-temperature annealing at 900 to 1200 ° C. instead of annealing at medium temperature as described above, segregation of impurities such as oxygen in the film occurs due to solid phase growth from nuclei. GB has a large amount of impurities such as oxygen, carbon, and nitrogen, and has a large mobility in the crystal.
Creates a barrier in the and prevents the movement of carriers there. And as a result, 5 cm ² / Vse
It is the actual situation that only mobility of c or less is obtained and the breakdown voltage is lowered due to drain leakage or the like at the crystal grain boundary.

That is, in the embodiment of the present invention, as described above, a silicon semiconductor having a crystalline semi-amorphous or semi-crystalline structure is used. The gate oxide film 3 may be formed by adding a small amount of fluorine.

In order to improve the interface characteristics between the silicon oxide and the underlying semiconductor film and remove the interface state, it is preferable to apply ultraviolet light at the same time to perform ozone oxidation. That is, if the combined use of the sputtering method and the photo CVD method under the same conditions as the formation of the blocking layer 38, the interface state could be further reduced.

After this, phosphorus is added to the upper side in an amount of 1 to 5 ×.
A silicon film having a concentration of 10 ²⁰ cm ⁻³ or this silicon film and a multi-layer film 49 of molybdenum (Mo), tungsten (W), MoSi ₂ or WSi ₂ are formed thereon. This multilayer film 49 has a thickness of 700 as in this embodiment.
If the production process is performed at a temperature below °,
Aluminum, aluminum and other metal compounds, or general metal compounds may be used.

A photoresist 35 is provided on the multilayer film 49, and the photoresist 35 is selectively removed by using a second photomask. As shown in FIG. 6B, the photoresist 35 is used as a mask. A part of the film 49 is removed. The resist 35 and the region partially removing the multilayer film 49 36,37,36 ', 37' with respect to, C, N or O, the O in this embodiment 1 × ¹⁰ 20 ~5 × ^10
The photoresist 35 and the multilayer film 49 are added as a mask by an ion implantation method so as to have a concentration of ²¹ cm ⁻³ ,
This region is converted to silicon oxide, that is, SiO _{2 -X} (0 ≦ X <
It is defined as the region whose composition is expressed in 2).

According to the SIMS measurement, the concentrations of these impurities were the lowest at the center of the film and the highest at both ends in the thickness direction. The concentration of impurities such as C, N or O in the central portion of the film is preferably 1 × 10 ¹⁹ cm ^{−3, and more} preferably 8 × 10 ¹⁹ cm ⁻³ or more. The voltage applied during this ion implantation is 30 to 50 KeV, for example 35 KeV. As a result, oxygen-added regions as shown in (B), (B), (B '), and (B') of FIG. 6B are formed. The lateral thickness of this region is 0.1 to 30 μm, preferably 1 to 10 μm, for example 2 μm. The thickness is 200 Å to 2 μm, preferably 500 to 2,000 Å, and in this embodiment, 1000.
Å.

This is patterned with a third photomask. And the gate electrode 4 for PTFT 4, NTFT
A gate electrode 4'for use in forming is formed to obtain the shape shown in FIG. In this embodiment, a part of the multilayer film 49, a part of which is removed, is used as it is as a gate electrode. Therefore, the oxygen added regions (a), (b), (a '),
(B ') One boundary part 61, 62, 61'62'
Coincide with both ends 62, 63, 62 ', 63' of the gate electrode.

In this embodiment, for example, the channel length is 1
0 μm, 0.2 μm of phosphorus-doped silicon as a gate electrode
m, and molybdenum is formed thereon to a thickness of 0.3 μm.

In FIG. 6D, the photoresist 3
1'is formed by using a photomask, and boron is applied to a region serving as the source 5 and the drain 6 for the PTFT by using the gate electrode 4 as a mask and a dose amount of boron of 1 to 2 × 10 ¹⁵ cm ^{−2 by} an ion implantation method. Added. Next in FIG.
As shown in (E), the photoresist 31 is formed using a photomask. And a source 5 for NTFT ', the drain 6' amount of phosphorus 1 × ¹⁰ 15 ^{cm -2} to again gate electrode 4 'to a region serving as a mask, is added by an ion implantation method. These are performed through the gate insulating film 3. However, in FIG. 6C, the silicon oxide on the silicon film is removed using the gate electrodes 4 and 4'as a mask, and then boron and phosphorus are ion-implanted directly into the silicon film using the gate electrodes 4 and 4'as a mask. May be.

In the case of the present embodiment, impurities such as boron and phosphorus that impart a P or N conductivity type are ion-implanted using the gate electrode as a mask to form the source and drain of the PTFT or NTFT. In the case of NTFT as shown in D), the boundary between the source and the channel is 6
1 ', the boundary between the drain and the channel is 62', which coincides with one boundary of the oxygen-doped impurity regions (a ') and (b'). That is, in this embodiment, the oxygen-doped impurity regions are present inside the source / drain regions which are semiconductors to which the impurity imparting one conductivity type is added. That is, the present embodiment has the same configuration as the example shown in FIG.

After the step of forming the gate electrode, the photoresist 31 is removed, and heat annealing is performed again at 630 ° C. for 10 to 50 hours. The source 5 and drain 6 of the PTFT, the source 5'and the drain 6'of the NTFT
Are activated to form P ⁺ and N ⁺ regions. Channel forming regions 7, 7'are formed as semi-amorphous semiconductors under the gate electrodes 4, 4 '.
In general, activating the source / drain regions is effective in improving the electrical characteristics of the device, but when thermal annealing for activation is performed, impurities imparting P or N type conductivity are removed. There arises a problem of unnecessary diffusion into the channel formation region. However, by adopting the configuration of the present invention, for example, in the case of the present embodiment, N ⁺ -I
Alternatively, a region to which carbon, nitrogen, or oxygen existing at or near the IN ⁺ interface becomes a blocking region, so that unnecessary diffusion of impurities at the time of thermal annealing can be prevented. The region to which carbon, nitrogen and oxygen are added serves as a blocking region because carbon, nitrogen and oxygen form an extremely strong bond with silicon.

Region (a) to which impurities such as oxygen are added
(B), (a ′), and (b ′) are regions where the bandgap corresponding to 52 in FIG. 5 is wider than the channel region, the source, and the drain region. Also, with this configuration, N ⁺ -I, P ⁺
Crystal grain boundaries are less likely to exist on the surface where -I exists, and as a result, the drain breakdown voltage can be further increased.

In this way, the C / TFT can be manufactured without applying a temperature of 700 ° C. or higher in all steps, even though it is a self-aligned method. Therefore, it is not necessary to use an expensive substrate such as quartz as the substrate material.

The energy band diagram of the NTFT produced in this example is similar to that shown in FIG.
This is obvious considering that this embodiment has the same structure as the NTFT shown in FIG. In this case, NT of FIG.
61 ', 6 which is the interface of N ⁺ -I or I-N ⁺ of FT
2'corresponds to 111 and 112 in FIG. In the energy band diagram of the PTFT manufactured in this example, the doping amount of impurities is exactly the same in the NTFT and the PTFT, and if the channels are both intrinsic semiconductors, FIG. 5 is symmetric with respect to the Fermi level ( _fe ). It roughly matches the one converted to.

In this embodiment, thermal annealing is performed as shown in FIG.
Perform (A) and (E) twice. However, the annealing in FIG. 6A may be omitted depending on the desired characteristics, and both may be combined by the thermal annealing in FIG. 6E to reduce the manufacturing time.
Further, in FIG. 7A, the interlayer insulator 8 is formed as a silicon oxide film by the above-described sputtering method. The silicon oxide film may be formed by using the LPCVD method or the photo CVD method. For example, it is formed to a thickness of 0.2 to 1.0 μm. After that, as shown in FIG. 7A, a window 32 for an electrode is formed using a photomask. Further, aluminum is formed to a thickness of 0.5 to 1 .mu.m on the whole by sputtering, and leads 9'and contacts 29, 29 'are formed using a photomask as shown in FIG. 7B.

The characteristics of such a TFT will be briefly described. PTFT
For, the mobility (μ) is 26 (cm ² / Vs), the threshold voltage is −4.3 V, and the drain breakdown voltage is −.
It becomes 33V. For NTFT, mobility (μ)
42 (cm ² / Vs), the threshold voltage is +
The drain withstand voltage becomes 3.9V and + 37V. This characteristic shows the case where the channel length is 10 μm and the channel width is 30 μm. By using such a semiconductor, it is possible to obtain a mobility, which is generally impossible, and a drain breakdown voltage can be obtained at a large level. Therefore, for the first time, the NTFT or C / T for the liquid crystal display device shown in FIG.
The FT can be configured.

This embodiment is an example of a liquid crystal display device, and in order to connect the output of this C / TFT to a pixel, an organic resin 34 such as polyimide is formed in FIG. Open the windows. Further, in order to connect the outputs of the two TFTs to the transparent electrode, ITO (indium tin oxide film) is formed by the sputtering method. Etch it with a photomask,
The transparent electrode 33 is formed. This ITO is room temperature to 150
The film was formed at a temperature of ℃ and annealed in oxygen or air at 200 to 300 ℃.

In this way, the PTFT 21 and the NTFT are
11 and the electrode 33 of the transparent conductive film are formed on the same glass substrate 1.

FIG. 9A shows an embodiment corresponding to FIG. V _DD 18, V _SS 19, V _DD '1 as X-ray
8. V _SS '19' is formed. V _GG 22 and V _GG '22 are formed as Y lines.

FIG. 9A is a plan view, but A-
A vertical sectional view of A ′ is shown in FIG. Further, a vertical cross-sectional view of BB 'is shown in FIG.

The PTFT 21 is connected to the X-ray V _DD 18 and the Y-line V
The PTFT 2 for another pixel is provided at the intersection with the _GG 22 and further at the intersection with the V _DD 18 and the V _GG '22'.
1A is similarly provided. NTFT 11 is V _SS 1
9 is provided at the intersection of V _GG 22. V _DD 1
Below the intersection of 8 ′ and V _GG 22, PTFTs for other pixels are provided. The present embodiment has a matrix structure using such C / TFT.
The PTFT is connected to the X-ray V _DD 18 via the contact 32 at the input end of the source 5, and the gate 4 is connected to the Y-line V _GG 22 having a multilayer structure. The output end of the drain 6 is connected to the pixel electrode 33 via the contact 29.

On the other hand, in the NTFT 11, the input end of the source 5'is connected to the X-ray V _SS 19 through the contact 32 ', the gate 4'is connected to the Y-line V _GG 22, and the output end of the drain 6'is contact 29'. Is connected to the pixel 33 through. Thus, one pixel is constituted by the pixel 33 made of the transparent conductive film and the C / TFT while being sandwiched between the two X-rays 18 and 19 (inside). By repeating such a structure horizontally and vertically, one example of a 2 × 2 matrix or an enlarged version of 640 × 640, 128
It is possible to make a liquid crystal display device having a large pixel size of 0 × 1280.

The salient feature here is that TF is applied to one pixel.
T is provided in a complementary configuration, the pixel 33 has a liquid crystal potential V _LC , which is either PTFT on and NTFT off, or PTFT off and NT.
The FT is fixed at either the on or the level. In FIG. 9, a known method is used in which an alignment film and an alignment treatment are applied on the transparent conductive film, and a certain space is provided between this substrate and the substrate having the other liquid crystal electrode (23 in FIG. 8). Are arranged with each other. Then, liquid crystal is injected or wired in the meantime to complete the device.

If TN liquid crystal is used as the liquid crystal material, it is necessary to form the alignment film on both of the transparent conductive films by rubbing treatment with a gap of about 10 μm. When FLC (ferroelectric) liquid crystal is used as the liquid crystal material, the operating voltage is ± 20 V, the cell interval is 1.5 to 3.5 μm, for example 2.3 μm, and the opposite electrode (23 in FIG. 8) is provided. Only the alignment film may be provided and the rubbing process may be performed. When the dispersion type liquid crystal or polymer liquid crystal is used, the alignment film is unnecessary,
To increase the switching speed, the operating voltage is ± 10
It is set to ± 15 V, and the cell interval is thinned to 1 to 10 μm.

In particular, when the dispersion type liquid crystal is used, since the polarizing plate is unnecessary, the light quantity can be increased both as the reflection type and the transmission type. Since the liquid crystal has no threshold, the C / T in which a clear threshold voltage is defined as shown in the C / TFT of the present invention.
By adopting the FT type, it is possible to eliminate large contrast and crosstalk (bad interference with adjacent pixels).

[Embodiment 2] This embodiment relates to a manufacturing method for obtaining the complementary C / TFT shown in FIG. The present embodiment is different from the first embodiment in that, as is clear from the first embodiment shown in FIGS. 6B and 6C, the portions to be the gate electrodes 4 and 4 ′ and the resist film thereon are masked. As an impurity, oxygen is ion-implanted into the semiconductor layers 2 and 2 ′, but in this embodiment, as shown in FIG.
As shown in (B), first, impurities such as C, N, and O are ion-implanted into the semiconductor layer using the resist film as a mask, and at least one element such as C, N, and O is 1 × 1.
It is added by an ion implantation method so as to have a concentration of 0 ^{20 to} 5 × 10 ²¹ cm ⁻³ . According to this method, impurity regions (52 in FIG. 5) to which C, N, O, etc. are added are used.
(Corresponding to a wide bandgap area shown in 1) can be provided in a range extending below the gate electrode. The manufacturing process of this example will be described below.

FIG. 10 shows a part of the manufacturing process of this embodiment. First, the same steps as in Example 1 are performed, and then a photoresist 91 is provided and patterning is performed using a photomask as shown in FIG. This photoresist 91
The removed impurity region determines the impurity region to which C, N and O are added. Therefore, according to this method, the impurity region can be provided below the gate electrode, which is impossible by the ion implantation method in the first embodiment.

Then, using this photoresist 91 as a mask, at least one element selected from carbon (C), nitrogen (N), and oxygen (O), that is, carbon in this embodiment, is ion-implanted in the same manner as in the first embodiment. Doping by the method.

A silicon oxide film 3 serving as a gate oxide film is formed thereon by sputtering in an atmosphere of 100% oxygen to a thickness of 1000Å in the same manner as in the first embodiment. Further, after this, phosphorus is added to the upper side at 1 to 5 × 10 ²⁰ cm 2.
A silicon film having a concentration of ^-3 or this silicon film and molybdenum (Mo), tungsten (W), M on the silicon film.
forming a multilayer film of oSi ₂ or WSi ₂ , or a multilayer film of aluminum, aluminum and another metal compound, or a metal compound,
Further, by patterning this multilayer film in the same manner as in Example 1, the gate electrodes 4 and 4'are provided to obtain NTFT and PTFT. A C / TFT can be obtained by going through the same steps as in Example 1 below.

In this embodiment, the carbon element is added to 1 × 10 ^{20 to} 5 × 10 ²¹ cm ⁻³ before providing the gate electrode.
Region doped by ion implantation (a)
(B) (a ') and (b') are provided, and the gate electrode is provided after that, so that the region to which carbon, which is an impurity for forming a band gap peak, is added is limited to the position of the gate electrode. There is no. When impurities such as carbon and nitrogen oxygen are added by ion implantation using the gate electrode as a mask as in Example 1, as shown in FIG. 6D, it is clear that impurities such as carbon and nitrogen oxygen exist under the gate electrode. It was not possible to form a semiconductor region (a portion corresponding to the crest of the bandgap indicated by 52 in FIG. 5) to which at least one kind of impurity was added. In Example 1, since an impurity imparting one conductivity type is added using the gate electrode as a mask, the channel formation region is formed under the gate electrodes 4 and 4'as shown by 7 and 7'in FIG. 6D. However, in the case of the structure of this embodiment, carbon is formed from the source regions 5 and 5'to the channel forming regions 7 and 7'as shown in FIG. 10C. Regions (b) and (a ′) of the silicon semiconductor to which carbon is added, regions (a) of the silicon semiconductor to which carbon is added from the drain regions 6 and 6 ′ to the channel forming regions 7 and 7 ′,
(B ') can be provided. In this case, the boundaries between the carbon-added regions source regions 5 and 5'and the channel forming regions 7 and 7'are 91 and 91 ', and the drain regions 6 and 6'and the channel forming regions 4 and 4'are formed. The border is 92,
92 '. Therefore, the boundary between the source / drain region and the channel forming region is present in the carbon-added silicon semiconductor region.

NT in the case of adopting the configuration of this embodiment
A schematic energy band diagram of FT is shown in FIG. As shown in the energy band diagram shown in FIG. 11, when the NTFT is manufactured by the manufacturing process of this embodiment, the position of the peak 101 of the energy band gap obtained by adding carbon, nitrogen and oxygen is shown in FIG. It can be provided in a portion closer to the channel formation region than the position of the peak 52 of the energy band gap of the NTFT manufactured by the manufacturing method in Example 1 shown. Moreover, even when the crests having the same band gap as in the case of the first embodiment are provided, the heights of the crests of the band gaps as the potential barriers can be relatively changed when the provided positions are different. For example, when comparing the vicinity of the boundary between the channel and the drain, 112 in FIG. 5 and 92 ′ in FIG. 10, the size of the band gap formed by adding carbon, nitrogen, and oxygen is the same. Despite this, it can be seen that the height as a potential barrier for carriers and electrons is different.

Further, in the manufacturing process of this embodiment, by forming a region to which at least one kind of carbon, nitrogen and oxygen is added under the position of the gate electrode, an NTFT and a PTFT as shown in FIG. / TFT can be manufactured. This C / TFT has 1 × 10 ²⁰ carbon
It is a region added with 5 × 10 ²¹ cm ⁻³ (a).
The positions of (b), (b '), and (b') are C / T in FIG. 10 (D).
It is only different from FT. As shown in FIG. 12, the impurity regions added with carbon in the channel forming region, that is, 91, 92, 91 ′ and 92 ′, which are boundaries between the sources 5 and 5 ′ and the channel forming regions 7 and 7 ′, are one end. It can be seen that the impurity region for forming the band gap peak is provided.

An energy band diagram of the NTFT as shown in FIG. 12 is shown in FIG. As can be seen from this figure, since the impurity region added with carbon is provided in the channel formation region, the peak 101 of the energy band gap is shown in FIG.
Compared to the case of (corresponding to the first embodiment) and FIG. 11 (corresponding to the second embodiment), it is provided closer to the channel formation region than the boundary 91 ′ of the source / channel and the boundary 92 ′ of the drain / channel. I understand. Also in this case, even if the band gap size of the region to which carbon is added is the same, but the position is different, the height of the band gap peak as a potential barrier is not enough for electrons and carriers (holes). It will be different.

Furthermore, the width and height of the crests of the band gap are controlled by the impurity concentration, the width in the lateral direction, the degree of activation, etc. of the region to which at least one element of carbon, nitrogen and oxygen is added. You can

[Embodiment 3] In this embodiment, as shown in FIG. 14, in the TFT manufactured in Embodiment 2, C,
This is the case where the region to which N and O are added exists near the surface of the semiconductor layer. Even with this configuration, the breakdown voltage between the source and drain can be increased. Of course, this impurity may reach the vicinity of the substrate, but in the case of adopting the configuration of the present embodiment and doping C, N, O impurities by the ion implantation method, as compared with the case of the first and second embodiments. Therefore, the energy of the ions can be reduced, and the invasion of the ions to unnecessary portions where the doping is not desired can be prevented. The reference numerals in the drawing are the same as those in FIG. Needless to say, the insulating gate type field effect transistor shown in this specification may be either a P-channel type or an N-channel type.

In the manufacturing method of this embodiment, the voltage applied at the time of ion implantation of C, N and O is 40 KeV or less, for example 25.
Example 2 is the same as Example 2 except that it is KeV. It goes without saying that the same configuration as that of the first embodiment may be adopted.

[Embodiment 4] In this embodiment, an N-channel or P-channel type insulated gate field effect transistor is provided with a carbon-doped region near the boundary between the drain region and the semiconductor region under the gate electrode. FIG. 15 shows the structure of a semiconductor device having the above structure. By adopting the structure of this embodiment, the withstand voltage can be increased with a simple structure. The reference numerals in the drawings are the same as those in the second embodiment.

The manufacturing method of this example was in accordance with the manufacturing method of Example 2. Therefore, the channel-drain boundary 92 '
A region to which carbon is added so as to include is provided from the channel to the drain.

According to the concept of the present invention, in the inverted stagger type field effect transistor as shown in FIG.
By adding impurities such as C, N, and O, which is the constitution of the present invention, to the portion indicated by 5 by ion implantation or the like in the same manner as in Example 1, the same effect as the constitution of the present invention can be obtained.

Further, as shown in FIG. 17, the structure of the present invention can be applied to a planar type insulated gate field effect transistor. In this case, a thin film of carbide, nitride, or oxide is formed between the channel and the source / drain at 10-50.
The effect of the present invention can be obtained by uniformly providing the thickness of 0Å, and if possible, making it as thin as possible. in this case,
It has a manufacturing characteristic that the above-mentioned carbide, nitride, oxide, or a composite thin film thereof may be provided in the manufacturing process of a conventional planar type insulated gate field effect transistor.

In the other application examples of the present invention shown in FIGS. 16 and 17, 121 is a glass substrate, 122 is a base silicon oxide film, 123 is a silicon oxide film which is a gate oxide film, 1
24 is a non-single crystal silicon semiconductor film, 125 is a region to which at least one of C, N and O is added, 126 is a drain region, 127 is a source region, 128 is a gate electrode, 12
Reference numeral 9 denotes a thin film made of at least one of C, N and O, or a thin film to which at least one is added.
Reference numeral 30 is an interlayer insulator, 131 is an aluminum electrode, S is a source electrode, G is a gate electrode, and D is a drain electrode.
The thin film 129 in this embodiment is provided by the PCVD method, but other methods such as the LPCVD method, the sputtering method and the light C method.
The VD method or the like may be used.

Although non-single crystal silicon is used as the semiconductor in the present invention, other semiconductors may be used.

[0079]

The provision of the regions to which carbon, nitrogen and oxygen are added according to the present invention is caused by the problem of reverse leakage between the source and drain and the low breakdown voltage between the source and drain. We were able to solve the problem of slow leak that occurs when the voltage is below the threshold voltage.

[Brief description of drawings]

FIG. 1 shows an example of the present invention.

FIG. 2 shows a relationship between a gate voltage and a drain current obtained by the configuration of the present invention and a relationship between a gate voltage and a drain current in the conventional configuration.

FIG. 3 shows the relationship between the drain voltage and the drain current obtained by the configuration of the present invention, and the relationship between the drain voltage and the drain current in the conventional configuration.

FIG. 4 shows a conventional example.

FIG. 5 shows an outline of a schematic energy band diagram in the constitution of the present invention.

FIG. 6 shows a manufacturing process of an example of the present invention.

FIG. 7 shows a manufacturing process of an example of the present invention.

FIG. 8 shows a configuration of an embodiment of the present invention.

FIG. 9 shows a configuration of an embodiment of the present invention.

FIG. 10 shows a manufacturing process of an example of the present invention.

FIG. 11 shows a schematic energy band diagram of an NTFT in an example of the present invention.

FIG. 12 shows a configuration of an example of the present invention.

FIG. 13 is a schematic energy band diagram of an NTFT according to an example of the present invention.

FIG. 14 shows a configuration of an example of the present invention.

FIG. 15 shows a configuration of an example of the present invention.

FIG. 16 shows another application example of the configuration of the present invention.

FIG. 17 shows another application example of the configuration of the present invention.

[Explanation of symbols]

4, 4 '... Gate electrode 5, 5' ... Source 7, 7 '... Semiconductor film under gate electrode 6, 6' ... Drain Y, B, B ', B' ...・ A region to which carbon, oxygen or nitrogen is added 111 ... Boundary between source and channel 112 ... Boundary between drain and channel

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location 9056-4M 618 C

Claims (2)

[Claims] 1. A source region and a channel forming region made of silicon.
And a drain region, and near the boundary between the source region and the channel forming region,
At least one element selected from carbon, nitrogen and oxygen
A selectively added region is provided near the boundary between the channel forming region and the drain region.
Is at least one element selected from carbon, nitrogen and oxygen.
A region to which the element is selectively added is provided, and two regions to which the element is selectively added are the so-called
The drain region, the channel formation region, and the drain region
Energy band width greater than energy band width
A semiconductor device having. 2. A source region and a channel forming region made of silicon.
And a drain region, and near the boundary between the channel forming region and the drain region.
Is at least one element selected from carbon, nitrogen and oxygen.
A region to which the element is selectively added is provided, and two regions to which the element is selectively added are the so-called
The drain region, the channel formation region, and the drain region
Energy band width greater than energy band width
A semiconductor device having.