JPH0817181B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a high speed bipolar transistor and a manufacturing method thereof.

[0002]

2. Description of the Related Art In order to realize a high speed bipolar transistor, it is necessary to reduce the base resistance and the capacitance between the base and the collector, and various proposals have been made for this subject. Figure 6 shows IEDM Tech. Digest pp.225.
-228 (1989), it is a cross-sectional view of the bipolar transistor, (a) ~ (c) of FIG. 7 is a cross-sectional view showing the manufacturing process stage.

To manufacture this semiconductor device, first, n is formed on the surface of a p-type semiconductor substrate (not shown) made of silicon.
A type-embedded region 201 is formed, an n-type epitaxial layer is formed thereon, and then an isolation insulating film 203 for isolating this transistor from other regions is formed to partition the n-type epitaxial region 202. An amorphous silicon layer 204 is deposited on the n-type epitaxial region 202 in a state of slightly protruding from the isolation insulating film [(a) of FIG. 7].

Next, the amorphous silicon layer 204 is crystallized by heat treatment at 950 ° C. to form a large grain size polysilicon layer 205 [(b) of FIG. 7]. Heat treatment temperature is 9
When the temperature is 50 ° C., many crystal nuclei are generated in the amorphous silicon layer 204, and crystallization progresses based on the crystal nuclei. Therefore, the n-type epitaxial region 202, which is single crystal silicon, is also polycrystallized.

Next, a p-type impurity is introduced into the large-grain polysilicon layer 205, and this is introduced into the p-large-grain polysilicon layer 2.
06, and then the n-type epitaxial region 202
The upper p-type large-grain polysilicon layer 206 is removed [FIG.
(C)].

After that, a p-type impurity is introduced into the n-type epitaxial region to form a base region 207 and an external base region 208 in the n-type epitaxial region 202, and then an insulating layer 209 is formed to form an insulating layer 209. An emitter opening is formed, and impurities are diffused from the emitter polysilicon 210 through the emitter opening to form an emitter region 21.
1 is formed, the semiconductor device of FIG. 6 is obtained.

In the semiconductor device thus formed, p-type large-grain polysilicon is used for the base lead portion, and this polysilicon layer has a layer resistance of 47 Ω / □, which is one of ordinary polysilicon layers. Since it is / 2 or less, it is possible to reduce the base resistance.

FIG. 8 is a sectional view of the second conventional example. This semiconductor device is manufactured as follows. An n-type epitaxial region 303 and a first insulating film 304a are formed on a p-type semiconductor substrate 301 having a buried n-type region 302 formed on its surface.
To form. After forming the opening in the first insulating film, p-type silicon is epitaxially grown. At this time, the p-type single crystal silicon layer 3 is formed on the n-type epitaxial region 303.
05, and a p-type polysilicon layer 306 is formed on the first insulating film 304a.

After patterning the p-type polysilicon layer, a second insulating film 304b is formed and an emitter opening is formed therein. After introducing the p-type impurity through the emitter opening, heat treatment is performed to form the external base region 307 and the base region 308. After forming a sidewall insulating film 309 on the side surface of the emitter opening, emitter polysilicon 310 containing phosphorus is deposited and heat-treated to form the emitter region 3.
11 is formed.

[0010]

In the above-mentioned first conventional example, when the amorphous silicon is crystallized, the amorphous silicon on the n-type epitaxial region 202 is also polycrystallized, but it is formed in the junction portion of the bipolar transistor. The presence of grain boundaries of silicon causes inconveniences such as generation of leak current and uneven diffusion of impurities. Therefore, in the first conventional example, it was necessary to completely remove polycrystalline silicon on the junction by etching. However, the first
In the conventional example, if the connection portion of the p-type large-grain polysilicon layer 206 with the n-type epitaxial region 202 is too large, the external base region 208 and the buried n-type region 201 approach each other, and the breakdown voltage between the base and the collector lowers. Therefore, when the thickness of the n-type epitaxial region 202 is 0.6 μm,
It was necessary to suppress the height of the connecting portion to 0.2 μm or less.

Therefore, if the etching time of the polycrystalline silicon on the junction is too long, the connection portion of the p-type large-grain polysilicon layer 206 with the n-type epitaxial region 202 becomes thin or disappears, resulting in a base resistance. Invited to increase. However, if the etching time is insufficient, polycrystalline silicon remains on the epitaxial layer, causing the above-mentioned inconvenience. That is, the first conventional example has a drawback that it is difficult to control the etching amount.

In the above-mentioned second conventional example, a part of the base lead portion is single-crystallized to exhibit a low resistance, but the other part is polysilicon having a higher layer resistance than the large grain polysilicon, There was a drawback that the base resistance was high as a whole.

In any of the conventional examples, the external base region is formed in the n-type epitaxial region forming the collector region, and is arranged to face the buried n-type region having a high impurity concentration. Therefore, a large parasitic capacitance is generated between the base and collector.

Therefore, an object of the present invention is to solve the above-mentioned drawbacks of the conventional example and to stably manufacture a semiconductor device having a low base resistance and a small base-collector parasitic capacitance. That is.

[0015]

To achieve the above object, in a semiconductor device of the present invention, a semiconductor region (10) of the first conductivity type surrounded by an insulating film (104) on the surface of a semiconductor substrate.
3) is formed, a low impurity concentration single crystal silicon layer (106) having an opening on the semiconductor region is formed on the semiconductor region and on the insulating film around the semiconductor region, and the semiconductor layer on the bottom surface of the opening is formed. The surface region of the first diffusion layer (11) of the first conductivity type that does not reach the side wall of the opening.
7) is formed, and a second diffusion layer (115) of the second conductivity type having a shape surrounding the first diffusion layer is formed around the sidewall of the opening and in the semiconductor layer below the first diffusion layer. , 118)
And a lower surface of the second diffusion layer, a top surface of which is in contact with a bottom surface of the second diffusion layer and a bottom surface of which reaches the semiconductor region. Layer (11
2) has been formed.

Further, the manufacturing method thereof includes a step of forming a first insulating film (104) having a shape surrounding the semiconductor region on the surface of a semiconductor substrate having a semiconductor region (103) of the first conductivity type on the surface, A step of forming an amorphous semiconductor layer (105) at least on the semiconductor region and on the first insulating film around the semiconductor region; and by heat treatment, a portion of the amorphous semiconductor layer that is in contact with the semiconductor region is single-crystallized. And converting the amorphous semiconductor layer in and around the semiconductor region into a single crystal silicon layer (106), and introducing impurities of the second conductivity type from the upper surface of the single crystal silicon layer. Forming a fourth diffusion layer (108) of the second conductivity type on the crystalline silicon layer; forming a second insulating film (110) on the single crystal silicon layer;
Part of the second insulating film and the single crystal silicon layer on the region surrounded by the insulating film is selectively etched to form an opening whose bottom surface is deeper than the lower part of the fourth diffusion layer. A step of introducing an impurity of the first conductivity type from the upper surface of the opening to form a third diffusion layer (112) of the first conductivity type, the lower part of which reaches the semiconductor region; and the sidewall of the opening. Forming a sidewall insulating film (114) on the
Forming a second diffusion layer (115, 118) of the second conductivity type by introducing impurities of the second conductivity type into the bottom and side surfaces of the opening; and forming a first diffusion layer on the region surrounded by the sidewall insulating film.
Forming a first diffusion layer (117) of the first conductivity type by introducing impurities of the conductivity type.

[0017]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a sectional view showing a first embodiment of the present invention. In FIG. 1, 101 is a p-type semiconductor substrate, 1
Reference numeral 02 denotes a buried n-type region formed on the surface of the semiconductor substrate, 103 denotes an n-type epitaxial region formed on the semiconductor substrate, and 104 denotes silicon oxide formed so as to surround the n-type epitaxial region. Is an element isolation region, and 106 is a low impurity concentration single crystal silicon region,
108 is a p-type single crystal silicon region formed in the surface region of the single crystal silicon region 106, 109 is a p-type large-grain polysilicon region, 110 is an insulating film, 111 is an insulating film 110 and a single crystal silicon region. Emitter openings formed in 108 and 106, 112 is an n-type silicon region, 11
4 is a BSG (Boro-Silic) on the side surface of the emitter opening 111.
a side wall insulating film formed by ate glass), 115 is a base region, 116 is n-type polysilicon, 117 is an emitter region, 118 is an external base region formed outside the base region 115 for extracting the base, 119 Is an insulating film, and 120 is an Al wiring.

Next, the manufacturing method of the first embodiment will be described with reference to FIGS. 2A to 2D which are sectional views of the steps. First, an embedded n-type region 102 is formed by selectively introducing an n-type impurity such as arsenic or antimony on the p-type semiconductor substrate 101. Next, an n-type epitaxial region 103 having a thickness of 0.4 μm and a specific resistance of 1 Ω · cm is formed. Next, thermal oxidation is performed using an oxidation resistant film such as a silicon nitride film as a mask to selectively form an element isolation region 104 of silicon oxide having a thickness of 0.6 μm. Next, high temperature heat treatment at about 900 ° C. is performed in a gas atmosphere of hydrogen, hydrogen chloride or the like to remove the natural silicon oxide film on the exposed portion of the n-type epitaxial region 103, and then silicon is deposited at a temperature of 500 to 550 ° C. Then, an amorphous silicon layer 105 having a thickness of 0.6 μm is formed [(a) of FIG. 2].

Next, heat treatment is performed at a temperature as low as possible, for example, 550 ° C. to 700 ° C., at which the amorphous silicon is crystallized. Preferably about 600 ° C., 1
Amorphous silicon is crystallized by performing heat treatment for 2 to 24 hours. At this time, since crystallization is performed epitaxially from the portion of the amorphous silicon in contact with the n-type epitaxial region 103, the n-type epitaxial region 1
03 and its periphery 3 to 5 μm of the element isolation region 1
04, a single crystal silicon region 106 is formed, and a large grain size polysilicon 107 having a grain size of about 5 to 10 μm is formed on the outer side of the region 104 by amorphous silicon which has not been epitaxially grown.

Next, boron is converted into energy: 10 ke
V, dose: 1E16 cm ^-2 single crystal silicon 1
06 and the large grain size polysilicon region 107 are ion-implanted to form a p-type single crystal silicon region 108 having a thickness of about 0.2 μm
A and p-type large-grain polysilicon regions 109a are formed [(b) of FIG. 2]. The p-type impurity may be introduced by means of introduction by heat treatment of the BSG film, thermal diffusion by vapor phase method, or epitaxial growth while introducing boron, instead of the ion implantation method.

Next, using the photoresist as a mask, the single crystal silicon region 106, the large grain polysilicon region 107, p.
The type single crystal silicon region 108a and the p-type large-grain polysilicon region 109a are selectively etched to form a silicon island region at the transistor formation location. next,
An insulating film 110 having a thickness of 0.2 μm is formed on the entire surface. Next, etching is performed using a photoresist as a mask to penetrate through the insulating film 110 and the p-type single crystal silicon region 108a, and further penetrate into the single crystal silicon region 106 by 0.1 μm deeper than a future expansion portion of this region 108a. The emitter opening 111 is formed. If the etching amount of the single crystal silicon region 106 is in the range of 0 to 0.2 μm, a large change in transistor characteristics does not occur. When a defect is generated on the silicon surface by etching, for example, the low-energy radical of CF ₄ causes the silicon surface to reach 2
It is advisable to remove the crystal defects by etching about 0 nm.

Next, phosphorus is added at an energy of 300 ke.
V, dose: 3E12 cm ^-2 , ion implantation was performed under the condition of n
A type silicon region 112 is formed. Next, a BSG film 113 having a thickness of 0.1 μm is formed using BSG containing 4 mol% of boron, and rapid thermal annealing (hereinafter, R
(Hereinafter referred to as TA), boron in the BSG film 113 is introduced into the n-type silicon region 112 and the single crystal silicon region 106 to form a base region 115. At this time, p
The p-type single crystal silicon region 108a and the p-type large-grain polysilicon region 109a are respectively formed by the downward diffusion of boron in these regions.
It becomes the p-type large-grain polysilicon region 109. That is, in this diffusion step, in the single crystal region having a small diffusion coefficient, boron diffusion stops in the single crystal silicon region 106, but in the polycrystalline region where the diffusion is fast, all of the large grain polysilicon region 107 is p-type. [(C) of FIG. 2].

Next, the BSG film 1 is anisotropically etched.
13 is etched to form a sidewall insulating film 114 on the sidewall of the emitter opening. Next, n-type polysilicon 116 containing arsenic at a concentration of about 10 ²¹ cm ⁻³ is formed, and this is patterned using a photoresist to form the emitter opening 1.
Only 11 parts are left. Next, RTA is performed at 1020 ° C. for 20 seconds to introduce arsenic in the n-type polysilicon 116 to the upper portion of the base region 115 to form the n-type emitter region 1.
Form 17. At this time, boron is further diffused into the base region 115 in the portion in contact with the sidewall insulating film 114,
The external base region 118 is formed [(d) of FIG. 2].
After that, an insulating film 119 is deposited on the entire surface, openings for leading out the respective electrodes of the transistor are formed, and an Al wiring 120 is formed, whereby the semiconductor device of this embodiment shown in FIG. 1 is completed.

In the above embodiment, the base region 115 and the external base region 118 are formed by the diffusion of boron from the BSG film 113, but they may be formed by an ion implantation method instead. Or base area 1
15 is formed by an ion implantation method, and the external base region 11 is formed.
8 may be formed by the sidewall insulating film 114 made of BSG.

In the semiconductor device configured as described above,
Since the base is mainly drawn out by the p-type single crystal silicon region 108 having a low layer resistance, the base resistance can be reduced. Further, the external base region 118 has a reduced size on the plane as compared with the conventional example, and the external base region 118 and the p-type single crystal silicon region 1 are provided.
Since the single crystal silicon region 106 having a low impurity concentration is interposed between 08 and the collector region, the base-collector parasitic capacitance can be suppressed to a low level. Here, when the single crystal silicon region 106 is n-type, a high impurity concentration p
Since the depletion layer hardly extends in the type single crystal silicon region 108 and the depletion layer extends to the single crystal silicon region 106 side, the impurity concentration of the single crystal silicon region 106 is 10 ¹⁵ cm 2.
^-3 or less or when the single crystal silicon region 106 is p-type, the depletion layer extends to both the n-type epitaxial region 103 and the single crystal silicon region 106, so that the impurity concentration of the single crystal silicon region 106 is 10 ^16. When it is less than cm ^-3 , it has a remarkable effect in reducing the parasitic capacitance between the external base and the collector.

Next, a second embodiment of the present invention will be described with reference to FIG. In the present embodiment, the sidewall insulating film 114 formed of a single material in the previous embodiment includes the sidewall insulating film 114a having a high impurity concentration on the outer peripheral side and the sidewall insulating film 114b having a low impurity concentration on the inner peripheral side. It has a two-layer structure.
As a result, the impurity concentration of the external base region 118 is set to p
It is possible to use a tilted type that increases as it approaches the type single crystal silicon region 108 and decreases as it approaches the base region 115, and it is possible to reduce the external base resistance and improve the emitter-base breakdown voltage.

Next, the manufacturing method of the second embodiment will be described. Forming the emitter opening 111, energy: 3
The steps up to ion implantation of phosphorus under the conditions of 00 keV and a dose of 3E12 cm ⁻² to form the n-type silicon region 112 are the same as those in the first embodiment. next,
BSG containing 9 mol% of boron is grown to a thickness of 0.05 μm, and the BSG film other than the sidewall of the emitter opening is removed by anisotropic etching to form a sidewall insulating film 114a. Next, perform RTA at 1030 ° C for 30 seconds,
The boron in the insulating film 114a is replaced with the single crystal silicon region 106.
To form an extrinsic base region 118.

Next, boron containing 4 mol% of B
SG is formed to a thickness of 0.05 μm, and 1000 ° C., 10
RTA is performed for 2 seconds to introduce boron in the BSG film into the single crystal silicon region 106 to form a base region 115.
After that, the semiconductor device of FIG. 3 is obtained through the same steps as those of the previous embodiment.

FIG. 4 is a sectional view showing a third embodiment of the present invention. In the semiconductor device of this embodiment, the element isolation region 1
The side surface of 04 is in contact with the side surface of the n-type silicon region 112. With this configuration, the extrinsic base regions 118 and p
The type single crystal silicon region 108 can be completely separated from the n-type epitaxial region 103 and the buried n-type region 102, and the base-collector parasitic capacitance can be further reduced.

FIG. 5 is a sectional view showing a fourth embodiment of the present invention. In this embodiment, the single crystal silicon region 106 is thin, and the bottom surface of the emitter opening 111 reaches the n-type epitaxial region 103.
In this embodiment, the entire transistor active region can be formed in the epitaxial region having fewer defects than the single crystal silicon region 106, so that the effect of improving the transistor characteristics can be expected.

[0031]

As described above, since the semiconductor device of the present invention has the low-concentration semiconductor and the element isolation region between the external base region and the collector region, it has a parasitic capacitance between the base and the collector. Can be reduced. Further, in the semiconductor device of the present invention, since the emitter region 117, the base region 115, and the external base region 118 are formed in self-alignment with the emitter opening 111, the emitter opening 111 is formed.
Even if the depth of the transistor changes slightly, the shape and characteristics of the transistor do not change significantly. That is, the present invention improves the stability of transistor characteristics against nonuniform etching of the emitter opening.

Further, in the semiconductor device of the present invention, since the base is drawn out by the p-type single crystal silicon region 108, the external base resistance is reduced. That is, the layer resistance of single crystal silicon is 25 Ω / □, which is much lower than 47 Ω / □ of the large-sized polysilicon of the first conventional example and 100 Ω / □ of the polycrystalline silicon of the second conventional example. According to the present invention, the base lead resistance can be reduced to about 1/2 of that of the first and second conventional examples.

[Brief description of drawings]

FIG. 1 is a sectional view of a first embodiment of the present invention.

FIG. 2 is a process cross-sectional view for explaining the manufacturing method according to the first embodiment of the present invention.

FIG. 3 is a sectional view of a second embodiment of the present invention.

FIG. 4 is a sectional view of a third embodiment of the present invention.

FIG. 5 is a sectional view of a fourth embodiment of the present invention.

FIG. 6 is a sectional view of a first conventional example.

FIG. 7 is a process sectional view for explaining the manufacturing method of the first conventional example.

FIG. 8 is a sectional view of a second conventional example.

[Explanation of symbols]

 101 p-type semiconductor substrate 102 buried n-type region 103 n-type epitaxial region 104 element isolation region 105 amorphous silicon layer 106 single crystal silicon region 107 large grain polysilicon region 108, 108a p-type single crystal silicon region 109, 109a p-type large Grain size Polysilicon region 110 Insulating film 111 Emitter opening 112 n-type silicon region 113 BSG film 114, 114a, 114b Side wall insulating film 115 Base region 116 n-type polysilicon 117 Emitter region 118 External base region 119 Insulating film 120 Al wiring 201 Embedding n-type region 202 n-type epitaxial region 203 isolation insulating film 204 amorphous silicon layer 205 large grain polysilicon layer 206 p-type large grain polysilicon layer 207 base region 208 external layer Base region 209 Insulation layer 210 Emitter polysilicon 211 Emitter region

Claims (7)

[Claims] 1. A first conductivity type semiconductor region (103) surrounded by an insulating film (104) is formed on a surface of a semiconductor substrate, and the semiconductor region is provided on the semiconductor region and on the insulating film around the semiconductor region. A low-concentration single-crystal silicon layer (106) having an opening is formed in the surface of the semiconductor layer at the bottom of the opening, and the first conductivity type first layer that does not reach the side wall of the opening is formed. A first diffusion layer (117) is formed, and a second conductivity type second layer having a shape enclosing the first diffusion layer is formed around the side wall of the opening and in the semiconductor layer below the first diffusion layer. Diffusion layers (115, 118) are formed, and the upper surface of the second diffusion layer is below the second diffusion layer.
A semiconductor device in which a third diffusion layer (112) of the first conductivity type is formed which is in contact with the bottom surface of the diffusion layer and reaches the inside of the semiconductor region. 2. A fourth diffusion layer (108) of the second conductivity type, which is not deeper than the depth of the opening, is formed in the surface region of the single crystal silicon layer of the second diffusion layer (118). The semiconductor device according to claim 1, wherein the semiconductor device is formed so as to be in contact with the upper surface. 3. The semiconductor according to claim 2, wherein a second-conductivity-type large-grain polysilicon region (109) in contact with the fourth diffusion layer is formed at an end of the single crystal silicon layer. apparatus. 4. A sidewall insulating film (11) is formed on a side surface of the opening.
4. The semiconductor device according to claim 1, wherein 4) is formed, and at least a part of the second diffusion layer is formed by using the sidewall insulating film as a diffusion source. 5. A semiconductor region of the first conductivity type on a semiconductor substrate.
(103) is provided, a low impurity concentration single crystal silicon layer (106) having an opening at a predetermined position is formed on the surface of the semiconductor region, and in the surface region of the semiconductor layer at the bottom of the opening is formed. , A first diffusion layer (117) of the first conductivity type that does not reach the side wall of the opening is formed, and in the vicinity of the side wall of the opening and in the semiconductor layer below the first diffusion layer, A second diffusion layer (115, 118) of the second conductivity type having a shape surrounding the first diffusion layer is formed, and the second diffusion layer (115, 118) is formed.
A third diffusion layer, the upper surface of which is in contact with the bottom surface of the second diffusion layer, is formed in the lower portion of the diffusion layer, and is not deeper than the depth of the opening in the surface region of the single crystal silicon layer. A semiconductor device in which a fourth diffusion layer (108) of the second conductivity type is formed in contact with the upper surface of the second diffusion layer (118). 6. A semiconductor region (10) of the first conductivity type is provided on the surface.
3) forming a first insulating film (104) in a shape surrounding the semiconductor region on the surface of the semiconductor substrate having 3), and forming an amorphous semiconductor layer (105) at least on and around the semiconductor region. 1) on the insulating film and heat treatment is performed to single crystallize the portion of the amorphous semiconductor layer that is in contact with the semiconductor region, and the amorphous semiconductor layer in the semiconductor region and its periphery is formed into a single crystal silicon layer. (106)
And a step of introducing impurities of the second conductivity type from the upper surface of the single crystal silicon layer to form a fourth diffusion layer (108) of the second conductivity type on the single crystal silicon layer. And a second insulating film (11) on the single crystal silicon layer.
0) and a part of the second insulating film and the single crystal silicon layer on the region surrounded by the first insulating film are selectively etched so that the bottom surface thereof is the fourth. Forming an opening deeper than the bottom of the diffusion layer of
Forming a from the first conductivity type third diffusion layer (112) which lower by introducing a first conductivity type impurity reaches the semiconductor region and the open upper surface, the opening bottom and side
The second conductivity type impurity is introduced into the surface to increase the second conductivity type second expansion.
Forming a diffusion layer (115, 118) and the opening
Forming a sidewall insulating film (114) on the sidewall, and forming a first sidewall on a region of the bottom surface of the opening surrounded by the sidewall insulating film.
A step of introducing a conductivity type impurity to form a first conductivity type first diffusion layer (117). 7. The method of manufacturing a semiconductor device according to claim 6, wherein the sidewall insulating film contains impurities of the second conductivity type.