JPH08163395A - Image processor - Google Patents

Abstract

PURPOSE: To accurately generate a horizontal synchronizing signal with an inexpensive circuit without using an expensive and complicated analog circuit. CONSTITUTION: A negative-polarity synchronizing signal separating circuit 10 detects a negative-polarity synchronizing signal NHSYNC from a ternary synchronizing signal included in an input picture signal to detect a value DNP of the digital signal which is the output from an A/D converter 3 corresponding to the section of the change from the negative polarity to the zero level of the signal NHSYNC. A value Db of the digital signal corresponding to the back porch part or the image signal is detected also. These two detection signals are inputted to a comparator 16 and are compared with each other, and the point of time when these two input signals coincide with each other is determined as the reference position of the ternary synchronizing signal (the reference position of a horizontal synchronizing signal BSYNC) in accordance with a sampling period FSC of the digital signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus for capturing an HDTV system video signal, performing predetermined image processing and outputting the image to an output device such as a color printer. is there.

[0002]

2. Description of the Related Art Conventionally, when an HDTV system video signal is input and analog signal processing is performed, a horizontal sync signal (HSYNC) reference position is detected, and various pulses or clocks (clamp pulse, sampling clock) are based on the detected reference position. Etc.), the reference phase of the ternary sync signal is detected by the analog signal.

[0003]

However, in the above-mentioned conventional example, in order to detect the reference phase of the ternary horizontal synchronizing signal by the analog signal, the analog circuit element, for example, the comparator, the filter or the like causes the phase shift. A circuit was needed to compensate. Further, in order to reduce this phase shift as much as possible, a high-speed comparator for detecting the reference phase and a filter circuit (element) having a highly accurate group delay characteristic are required, resulting in a problem that the cost of the device increases. there were.

The present invention has been made in view of the above-mentioned conventional example, and an object of the present invention is to provide an image processing apparatus which can detect a reference phase more accurately and at a reduced cost by using a digital circuit. .

[0005]

In order to achieve the above object, the image processing apparatus of the present invention has the following configuration. That is, input means for inputting an analog image signal including a ternary sync signal as a horizontal sync signal, separating means for separating a negative sync signal from the ternary sync signal, and converting the analog image signal into a digital signal. The conversion means, the first detection means for detecting the data value of at least one place outside the effective image area of the digital signal, the section in which the negative polarity synchronization signal changes from the negative polarity to zero level, and the section corresponding to the section Second detection means for detecting the data value of the digital signal, comparison means for comparing the data values detected by the first and second detection means, and a three-valued synchronization signal of the three-valued synchronization signal based on the comparison result. An image processing apparatus, comprising: a determining unit that determines a reference position, wherein the reference position is determined in accordance with a conversion reference cycle of the digital signal. .

[0006]

With the above structure, the present invention compares the digital signal value corresponding to the zero level of the ternary sync signal with the data value of at least one portion outside the effective image area of the digital signal, and based on the comparison result. Then, it operates so as to determine the reference position of the ternary synchronization signal in accordance with the conversion reference cycle of the digital signal.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described in detail below with reference to the accompanying drawings. [Common Embodiment] FIG. 1 is a block diagram showing the basic arrangement of an image processing apparatus according to a typical embodiment of the present invention. In FIG. 1, reference numeral 101 is an A / D converter that inputs a three-primary-color signal (RGB) that is an HDTV video signal, performs analog processing such as amplification, clamp, low-pass filtering, etc., and converts it into an 8-bit digital signal. Circuit, 102
Is the horizontal sync signal (HSYNC) separated by the G signal
, A clock signal generator for A / D converting the basic clock (sampling clock FSC) for image transmission by a voltage-controlled crystal oscillator and a voltage-controlled oscillator, and 103 is an RG converted to an 8-bit digital signal.
It is a serial-parallel (S / P) converter for converting the data rate of the B signal so as to match the access time of the frame memory to be described later, and performing bit division (here, 4 divisions, 32 bits).

A frame memory 104 stores a 32-bit RGB signal, and has a capacity of 16 M bits (2048 (horizontal) × 1024 (vertical) × 8 bit) for each color component. Further, 105 is a frame memory 104.
A memory controller for writing data to and reading data from the memory and generating address signals. 106
Is a parallel-serial (P / P) for converting into an 8-bit image signal of a data rate based on a 32-bit bit division signal of each color read from the frame memory 104.
The S) converter 107 is a D / A conversion circuit for converting the RGB digital signal converted into 8 bits into an analog signal and supplying the analog signal to the monitor. And 108 is each color 32
Bit-divided signal of 8 bits at a predetermined rate, RG
Converted to B signal, Ma (magenta), Cy (cyan),
An interface (I that converts data into Ye (yellow) and Bk (black) signals and transmits data to the color LBP (I
/ F).

Two embodiments for generating an accurate horizontal sync reference signal will be described below. [First Embodiment] FIG. 2 shows the A shown in FIG. 1 according to the present embodiment.
3 is a block diagram showing an internal configuration of a / D converter 101. FIG.
FIG. 3 is a time chart showing an input / output signal from each part of the A / D converter 101 shown in FIG. 2 for generating the horizontal synchronization reference signal. In this circuit, the RGB signal processing is the same for each color component except for the synchronization signal processing system, and therefore the G signal processing circuit will be described as a representative here.

The input analog image signal is supplied to an amplifier (Amp) 1 for compensating the loss of the transmission system, and 2
It is amplified with a gain of 6 times (6 dB). Next, the differential amplifier (Amp) 2 is supplied to the non-inverted input (+) of the differential amplifier (Amp) 2 and amplified to a predetermined level, and then the low-pass filter (LPF) 3 A
1/2 of the sampling clock (FSC) of the / D converter 8
The unnecessary band signal above (here, 30 MHz) is removed, and the buffer amplifier (Amp) 4 causes the A / D converter 8
The impedance is converted so that the impedance is sufficiently low with respect to the input capacitance of.

Here, the output signal of the buffer amplifier 4 is supplied to the sample hold (S / H) circuit 5, and the level of the front porch portion, which is the reference of the black level, is set to the negative level of the horizontal synchronizing signal (three-valued synchronizing signal). 1 of the horizontal sync signal by the clamp pulse (CP) (30 in FIG. 3) obtained from the negative sync signal (NHSYNC) separated by the sex sync signal separation circuit 10 via the monostable multivibrator (MM) 11. The pulse is sampled once and held for a horizontal sync period (from one pulse to the next).

The black level sampled and held is supplied to the non-inverting input (+) of the differential amplifier (Amp) 7, and the inverting input (-) thereof receives the reference voltage generated by the reference voltage generating circuit (REF) 6. (VREF) is supplied. The differential amplifier 7 outputs a difference signal (error signal) between the black level of the image signal and the reference voltage (VREF) and supplies it to the inverting input (-) of the differential amplifier 2 so that only the error signal level is the DC voltage of the image signal. The (DC) level is shifted. Therefore, at the output of the buffer amplifier 4, the black level of the image signal is feedback clamped so as to be the same as the reference voltage (VREF).

The analog signal whose feedback signal is clamped and the black level of the image signal is fixed to the reference voltage (VREF) is 8 bits by the sampling clock (FSC) generated by the clock signal generator 102 in the A / D converter 8. Is converted into a digital signal of S / P by the latch circuit 9.
Time adjustment with the converter 103 is performed. Next, a method of detecting the horizontal synchronization reference signal (HSYNC), which is a feature of this embodiment, will be described.

The negative sync signal (NHSYNC) of the horizontal sync signal (three-value sync signal) is first separated from the input video signal by the negative sync signal separation circuit 10 and then by the monostable multivibrator (MM) 12. A back porch pulse signal (B indicating a part of the back porch portion)
P) is formed. The output data of the A / D converter 8 is supplied to the latch circuit 14, and the BP signal rises (31 in FIG. 3).
Thus, the data is latched and the data value (Db) of the back porch portion is output. Further, the NHSYNC signal is generated by the monostable multivibrator (MM) 13 into a gate signal representing a part of the period from the negative polarity synchronization to the positive polarity synchronization.

The output data of the A / D converter 8 is supplied to the gate circuit 15, and the data is output only during the period ("H" period) in which the gate signal is at a high level, and 00H (16) during the "L" period. The data value (DNP) of the portion of the sync signal changing from the negative polarity (34 in FIG. 3) to the positive polarity (35 in FIG. 3) is obtained (32 in FIG. 3). The data value (Db) of the back porch portion and the output data value (DNP) of the gate circuit 15 are supplied to the comparator circuit 16 and compared for each cycle of the sampling clock (FSC). Here, when the data values of Db and DNP match, the output changes from "L" to "H" state, and when the data do not match, it returns to "L" state again, and the rising time point is the reference of the horizontal sync signal. Position horizontal sync reference signal (HSYN
C) is generated (33 in FIG. 3).

FIG. 4 is a block diagram showing an internal configuration of the clock signal generator 102 shown in FIG. Horizontal synchronization reference signal (HS) generated in the A / D conversion circuit 101
YNC) is supplied to one input of the phase comparator 20. In addition, a sampling clock (FSC) generated by the voltage controlled oscillator (VCO) 25 is counted down by a predetermined count, and a clock formed by the count is used as a read clock. The synchronization signal (HS1) is the phase comparator 20.
Are fed to the other input of the, and the respective phases are compared and the phase error is converted to a voltage level.

Next, the error voltage signal from the phase comparator 20 is supplied to the voltage controlled crystal oscillator (VCXO) 21 and the crystal oscillation is performed so that the desired oscillation frequency (17 MHz) is obtained at the center level of the change range of the error voltage signal. Oscillation is controlled using the child 22. The output signal of the VCXO 21 is the counter 2
3 counts down by a predetermined count (1/51
2) and converted to have the same frequency as the horizontal synchronizing signal and supplied to one input of the phase comparator 24. Further, HS1 is supplied from the synchronization signal generator 27 to the other input of the phase comparator 24, the respective phases are compared, and the phase error is converted into a voltage level.

Next, the error voltage signal from the phase comparator 24 is supplied to the voltage controlled oscillator (VCO) 25, and the desired oscillation frequency (74.2) is reached at the center level of the change range of the error voltage.
5M / 71.28MHz), the oscillation is controlled.
The sampling clock (FSC) is output. Now, the sampling clock (FSC) is supplied to the counter 26, and the sampling clock (7) is set so that the pixel array of the image data becomes a square lattice when output to the image output device of the BTA (Broadcasting Technology Association) standard or the color LBP.
4.25MHz or 71.28MHz switching,
The counter 26 according to the BTA signal or the CLC signal
Switch the count output value of. And this counter 2
Using the clock output from 6 as the read clock, P
A horizontal synchronization signal (HS) and a vertical synchronization signal (VS) are output from the synchronization signal generator 27 including a ROM or the like as pulses necessary for image processing.

Therefore, according to this embodiment, the digital circuit can be configured as described above without using a high-speed comparator or a filter circuit (element) having a high group delay characteristic, which is required for a high-precision analog circuit. Therefore, it is possible to generate an accurate horizontal synchronization reference signal having an accuracy required for image processing in each pixel unit. The circuit as described above is easy to integrate, and the integration contributes to reduction of manufacturing cost.

[Second Embodiment] In the first embodiment, the data value of the back porch portion or the front porch portion in the image signal is detected by the A / D conversion circuit 101, and this is used as a horizontal synchronization reference signal. Although the reference data value for obtaining (HSYNC) is adopted, in the present embodiment, the average data value of the negative polarity signal data value and the positive polarity signal data value of the horizontal synchronizing signal is calculated and this is set as the horizontal value. An example in which the reference data value for obtaining the synchronization reference signal is used will be described.

FIG. 5 shows an A / D converter 10 according to this embodiment.
2 is a block diagram showing the internal configuration of No. 1. In addition, FIG.
6 is a time chart showing input / output signals from each unit of the / D converter 101. Note that, in FIG. 5, the same circuit reference numerals are attached to the same circuit components as those shown in FIG.
The negative sync signal separation circuit 10 separates the negative sync signal (NHSYNC) of the horizontal sync signal, and the monostable multivibrator (MM) 30 represents the negative sync data representing a part of the negative sync signal. Detection pulse (DN
P) is formed. The output data of the A / D converter 8 is supplied to the latch circuit 32, and the data is latched at the rising edge of the DNP signal, and the data value (DN) of the negative polarity synchronizing signal portion is supplied.
Is output (61 in FIG. 6). Further, the NHSYNC signal is generated by the monostable multivibrator (MM) 31 into a positive polarity sync data detection pulse (DPP) representing a part of the position of the positive polarity sync signal. The output data of the A / D converter 8 is supplied to the latch circuit 33, data is latched at the rising edge of the DPP signal, and the data value (DP) of the positive sync signal portion is output (62 in FIG. 6).

The data values (DN and DP) of the negative polarity and positive polarity sync signal portions are average value circuit (AVE) 34, respectively.
And the average data value ((DN + DP) / 2) is calculated. Further, the NHSYNC signal is generated by the monostable multivibrator (MM) 13 into a gate signal representing a part of the period from the negative polarity (63 in FIG. 6) to the positive polarity (64 in FIG. 6). The output data of the A / D converter 8 is supplied to the gate circuit 15, the data is output only during the “H” period of the gate signal, and the “L” period is fixed to 00H (hexadecimal notation) and the negative polarity of the synchronization signal is obtained. The data value (DNP) of the portion changing from the positive polarity to the positive polarity is obtained.

The average data value ((DN + DP) / 2) and the output data value (DNP) of the gate circuit are the comparator circuit 1
6 and is compared for each cycle of the sampling clock (FSC). Here, when the data values of (DN + DP) / 2 and DNP match, the output changes from "L" to "H" state, and when the data do not match, it returns to "L" state again, and the rising time is set horizontally. A horizontal synchronization reference signal (HSYNC) that is the reference position of the synchronization signal is generated.

Therefore, according to this embodiment, an average data value of the negative polarity signal data value and the positive polarity signal data value of the horizontal synchronizing signal is calculated without using an expensive and complicated analog circuit, and based on this, the average data value is calculated. To generate a horizontal sync reference signal. In the present embodiment, the A / D conversion circuit 1
The configuration is such that the negative polarity signal data value and the positive polarity signal data value of the horizontal synchronization signal are detected by 01, the average data value is calculated, and this is used as the reference data value for obtaining the horizontal synchronization reference signal. However, the present invention is not limited to this. For example, the data values of the back porch portion and the front porch portion in the image signal may be detected, the average data value thereof may be calculated, and this may be used as the reference data value for obtaining the horizontal synchronization reference signal. .

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of one device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0026]

As described above, according to the present invention, 3
A digital signal value corresponding to the zero level of the value synchronization signal,
Since the digital signal is compared with at least one data value outside the effective image area, and the reference position of the ternary synchronization signal is determined in accordance with the conversion reference cycle of the digital signal based on the comparison result, the digital conversion is performed. It is possible to accurately and stably detect the reference position of the horizontal synchronizing signal in accordance with the processing unit of 1), that is, the unit of one pixel.

Further, according to the present invention, since the reference position of the horizontal synchronizing signal can be digitally determined, there is an advantage that the apparatus according to the present invention can be constructed without using an expensive and complicated analog circuit, and the production cost can be reduced. Contribute to.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic configuration of an image processing apparatus that is a typical embodiment of the present invention.

FIG. 2 is a block diagram showing an internal configuration of an A / D converter 101 according to the first embodiment.

3 is a time chart showing input / output signals from respective parts of the A / D converter 101 shown in FIG. 3 for generating a horizontal synchronization reference signal.

4 is a block diagram showing an internal configuration of a clock signal generator 102 shown in FIG.

FIG. 5 is a block diagram showing an internal configuration of an A / D converter 101 according to a second embodiment.

6 is a time chart showing input / output signals from respective parts of the A / D converter 101 shown in FIG. 5 for generating a horizontal synchronization reference signal.

[Explanation of symbols]

3 Low pass filter (LPF) 5 Sample and hold circuit (S / H) 6 Reference voltage generation circuit (REF) 10 Negative sync signal separation circuit 11, 12, 13, 30, 31 Monostable multivibrator (MM) 17 Vertical Synchronous signal separation circuit 101 A / D conversion circuit 102 Clock signal generator 103 S / P converter 104 Frame memory 105 Memory controller 106 P / S converter 107 D / A conversion circuit 108 Interface (I / F)

Claims (5)

[Claims] 1. An input unit for inputting an analog image signal including a ternary synchronizing signal as a horizontal synchronizing signal, a separating unit for separating a negative synchronizing signal from the ternary synchronizing signal, and a digital signal for the analog image signal. Conversion means for converting into a digital signal, first detection means for detecting at least one data value outside the effective image area of the digital signal, a section in which the negative polarity synchronizing signal changes from negative polarity to zero level, and the section Second detection means for detecting the data value of the digital signal corresponding to, comparison means for comparing the data values detected by the first and second detection means, and the three values based on the comparison result. An image processing apparatus, comprising: a determining unit that determines a reference position of a synchronization signal, wherein the reference position is determined in accordance with a conversion reference cycle of the converting unit. . 2. The image processing apparatus according to claim 1, wherein the analog image signal is an HDTV system video signal. 3. The image processing apparatus according to claim 1, wherein the at least one location outside the effective image area is a front porch portion or a back porch portion of an image. 4. The determining means determines the reference position based on a time point at which the data values detected by the first and second detecting means match.
The image processing device according to item 1. 5. The signal generating means for generating, based on the negative polarity synchronizing signal, a signal representing a part of a section corresponding to the positive polarity synchronizing signal of the ternary synchronizing signal, Third detecting means for detecting a data value of the digital signal corresponding to a section corresponding to the positive polarity of the positive polarity synchronizing signal; and the digital corresponding to the section corresponding to the negative polarity based on the negative polarity synchronizing signal. A fourth detecting means for detecting a data value of the signal; and an averaging means for obtaining an average value of the data values detected by the third and fourth detecting means, wherein the average value is output from the first detecting means. The image processing apparatus according to claim 1, wherein: