JPH08162859A - Multi-stage amplifier - Google Patents

Abstract

PURPOSE: To suppress deterioration in a gain due to negative feedback while keeping input matching performance of an amplifier circuit of a 1st stage in an excellent way the same as a conventional amplifier. CONSTITUTION: A middle stage amplifier circuit B forming a source ground circuit comprising a FET 11 or the like is coupled with a 1st stage amplifier circuit A comprising a FET 4 or the like via a coupling capacitor 10, and a final stage amplifier circuit C being a component of a source follower buffer circuit comprising a FET 17 is coupled with the middle stage amplifier circuit B via a coupling capacitor 16. A capacitance causing series feedback to a signal frequency band is set to a capacitor 24 grounding a source of the FET 11 of the middle stage amplifier circuit B in terms of AC and a feedback circuit comprising a DC block capacitor 25 and a feedback resistor 26 is provided between a gate of the FET 4 in the 1st stage amplifier circuit A and a source of the FET 11 in the middle stage amplifier circuit B.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high frequency multistage amplifier using field effect transistors.

[0002]

2. Description of the Related Art GaAs MESFETs (GaAs metal semiconductor field effect transistors) are widely used as amplifiers for high frequency transistors because they are superior in high frequency characteristics and low noise characteristics to Si bipolar transistors. In the high frequency band above the wave band (1 to 3 GHz), it is applied to a wideband high frequency monolithic amplifier integrated monolithically (IC).

Among wide band high frequency monolithic amplifiers, an amplifier to which a parallel negative feedback circuit is added has excellent wide band characteristics and input matching, and therefore, satellite broadcasting, satellite communication,
It is used in mobile communications such as cellular telephones and receivers such as CATV, and usually has a multistage configuration.

FIG. 5 is a circuit diagram showing an example of a conventional wide band high frequency monolithic amplifier, in which 1 is a signal input terminal,
2, 3 are DC blocking capacitors, 4 are field effect transistors, 5 and 6 are bias resistors, 7 are load resistors, 8 is feedback resistors, 9 is a capacitor, 10 is a coupling capacitor, 11 is a field effect transistor, 12, 13 Is the bias resistance, 1
4 is a load resistor, 15 is a capacitor, 16 is a coupling capacitor, 17 is a field effect transistor, 18 and 19 are bias resistors, 20 is a load resistor, 21 is a DC blocking capacitor, 22 is an output terminal, and 23 is a power supply terminal. .

In the figure, this example shows amplifier circuits A, B,
The first stage amplifier circuit A is a parallel negative feedback amplifier circuit, the middle stage amplifier circuit B is a source ground circuit, and the last stage amplifier circuit C is a source follower buffer circuit.

In the first-stage amplifier circuit A, feedback is applied from the drain of the FET 4 to the gate, in parallel with the load resistor 7 and with the DC blocking capacitor 3 and the feedback resistor 8, whereby a parallel negative feedback amplifier circuit is provided. It is composed. Here, the bias resistor 6 connected to the source and the bias resistor 5 connected to the gate determine the source current of the first stage FET 4, and the capacitor 9 connected in parallel to the bias resistor 6 connects this source to a high frequency. Is to be grounded.

The amplifier circuit B in the middle stage has an FET 11, a load resistor 14 connected to its drain, bias resistors 12 and 13 connected to its gate and source, and a source connected to this bias resistor 13 in parallel. The capacitor 15 which is grounded at a high frequency constitutes a source grounding circuit. The gate of the FET 11 is connected to the drain of the FET 4 via the coupling capacitor 10, so that the amplification circuit B in the middle stage is coupled to the amplification circuit A in the first stage.

The final stage amplifier circuit C comprises a FET 17, bias resistors 18 and 19 connected to its gate, and a load resistor 20 connected to its source, and its drain is directly connected to a power supply terminal 23. The source is connected to the output terminal 22 via the DC blocking capacitor 21,
It constitutes the buffer circuit of the source follower. Also, F
The gate of ET17 is coupled to the drain of FET11 with a coupling capacitance of 1
The amplifier circuit C at the final stage is coupled to the amplifier circuit B at the middle stage by being connected via 6.

The signal input from the input terminal 1 is supplied to the parallel negative feedback amplifier circuit A at the first stage via the DC blocking capacitor 2, amplified there, and further amplified by the source grounded circuit B at the middle stage, and finally at the final stage. The signal is output from the output terminal 22 via the buffer circuit C and the DC blocking capacitor 21.
Here, in the first-stage amplifier circuit A, the parallel negative feedback is used to match the input impedance with the input signal and improve the frequency characteristic of the first-stage amplifier circuit A.

[0010]

In the conventional multistage amplifier described above, parallel negative feedback is used in which feedback is performed from the drain of the FET 4 to the gate of the FET 4 in the first stage amplifier circuit A in order to match the input impedance. Impedance matching characteristics, for example, quasi-microwave band (1 to 3 GHz)
2 to 500 MHz to 3 GHz, the following two methods can be considered in the conventional amplification circuit using the parallel negative feedback.

The first method is to use the FET of the first-stage amplifier circuit A.
4 is a method of improving the input impedance matching characteristics in the low frequency band by adding an inductor or a capacitor to the gate of the fourth gate. The second method is to reduce the feedback resistance 8 of the parallel negative feedback circuit A in the first stage to reduce the feedback amount. It is a method of improving the input impedance matching characteristic in the low frequency band by increasing the value.

However, the first method has a problem that the input impedance matching characteristic in the high frequency range is deteriorated because the number of parts increases and an inductor or a capacitor whose impedance changes according to the frequency is used. Therefore, in order to improve the input impedance matching characteristic in the low frequency band, a means for increasing the feedback amount of the parallel negative feedback circuit A at the first stage is used as in the second method. However, in the second method, when the feedback amount of the parallel negative feedback circuit A in the first stage is increased, the gain in the entire signal band, particularly in the low band, is lowered even if the input impedance matching characteristic in the low band is improved. There is a problem.

An object of the present invention is to solve the above problem and to provide a multistage amplifier which has an input impedance matching characteristic equivalent to that of the case where the conventional parallel negative feedback circuit described above is used, but has less gain reduction due to negative feedback. To provide.

[0014]

In order to achieve the above object, the present invention uses a capacitor for grounding the source of the FET of the second stage amplifier circuit at a high frequency as a means for matching the input impedance. Set the capacitance value for series feedback to the band, connect a feedback circuit including a resistor between the gate of the FET of the first stage amplifier circuit and the source of the FET of the middle stage amplifier circuit, and connect the first stage amplifier circuit in parallel. Injection series negative feedback circuit.

[0015]

[Operation] By connecting a feedback circuit including a resistor between the gate of the FET of the first-stage amplifier circuit and the source of the FET of the middle-stage amplifier circuit, an input impedance equivalent to that when a conventional parallel negative feedback circuit is used. A matching characteristic is obtained, and a decrease in gain due to negative feedback is suppressed.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of a multi-stage amplifier according to the present invention, in which 24 is a capacitor, 25 is a DC blocking capacitor, and 26 is a feedback resistor, and parts corresponding to those in FIG. And redundant description will be omitted.

In this figure, this embodiment basically has the same configuration as the conventional example shown in FIG. 5, and has three amplifier circuits: a first-stage amplifier circuit A, a middle-stage amplifier circuit B, and a final-stage amplifier circuit C. This is a wideband high frequency monolithic amplifier with a stage configuration.
In the conventional example shown in FIG. 2, the negative feedback circuit including the feedback resistor 8 and the capacitor 3 is provided in the first-stage amplifier circuit A, but in this embodiment, instead of the negative feedback circuit, the middle-stage amplifier circuit B is used. A negative feedback circuit in which a DC blocking capacitor 25 and a feedback resistor 26 are connected in series is provided between the input terminal of the first-stage amplifier circuit A and the input terminal.

That is, the first-stage amplifier circuit A includes the FET 4 and
A negative feedback circuit including a load resistor 7, bias resistors 5 and 6 for determining the source current of the FET 4, and a capacitor 9 for grounding the source of the FET 4 in high frequency, and a negative feedback circuit including the feedback resistor 8 and the capacitor 3 in FIG. First-stage amplifier circuit A removed
It has the same configuration as. The middle-stage amplifier circuit B and the last-stage amplifier circuit C are respectively the middle-stage amplifier circuit B in FIG.
And the amplification circuit C at the final stage. The first-stage amplification circuit A and the middle-stage amplification circuit B are coupled by the coupling capacitor 10, and the middle-stage amplification circuit B and the final-stage amplification circuit C are coupled by the coupling capacitor 16.

Further, the negative feedback circuit consisting of a series circuit of the DC blocking capacitor 25 and the feedback resistor 26 is a gate of the FET 4 of the first amplification circuit A and the FET of the middle amplification circuit B.
11 is connected to the source of FET 11, and the capacitor 24 connected to the source of FET 11 of the amplification circuit B in the middle stage is provided with a capacitance value that is a series feedback for the band of the input signal from the input terminal 1. By making it hold, the first-stage amplifier circuit A constitutes a parallel injection series negative feedback circuit.

In this way, in this embodiment, the first-stage amplifier circuit A constitutes a parallel injection series negative feedback amplifier circuit, the middle-stage amplifier circuit B constitutes the source ground circuit, and the last-stage amplifier circuit C constitutes the source follower. Each buffer circuit is configured,
The input signal from the input terminal 1 is supplied to the parallel injection series negative feedback amplifier circuit A at the first stage via the DC blocking capacitor 2, amplified there, and further amplified at the source grounded circuit B at the middle stage, and the buffer circuit at the final stage. It is output from the output terminal 22 via C and the DC blocking capacitor 21.

FIG. 2 is a simulation of frequency characteristics between the case where the feedback circuit is not provided in FIGS. 5 and 1 and the conventional example shown in FIG. 5 in which the parallel negative feedback circuit is provided and the embodiment shown in FIG. The results are compared, and in each case, the constants of the feedback circuit are set so that the input matching characteristics are equal in the signal band.

According to the figure, the lower the frequency range, the smaller the decrease in gain due to the negative feedback in the embodiment in which the parallel injection series feedback shown in FIG. 1 is carried out, as compared with the conventional example shown in FIG. Recognize. As an example of the difference of this feedback system, 500M
In the signal band of Hz, the parallel injection series negative feedback of the above-mentioned embodiment is about 5 dB compared with the conventional parallel negative feedback shown in FIG.
The result was high.

As described above, according to this embodiment, the parallel injection series negative feedback is used in the first-stage amplifier circuit A for the purpose of matching the input impedance, so that the conventional parallel negative feedback circuit shown in FIG. 5 is used. It is possible to obtain a multi-stage amplifier in which the input impedance matching characteristic equivalent to that of the case of using is obtained and the decrease in gain due to negative feedback is small.

FIG. 3 is a circuit diagram showing another embodiment of the multistage amplifier according to the present invention, in which 27 and 28 are inductors, the parts corresponding to those in FIG. To do.

In the figure, the FE in the amplifier circuit A in the first stage is
A series feedback inductor 27 is connected to the source of T4, and a bias resistor 6 and a high frequency grounding capacitor 9 are connected to the other end of the inductor 27. By performing series feedback with the inductor 27, the feedback amount in the high frequency band is increased, the input impedance matching characteristic in the high frequency band is further improved, and the oscillation of the FET 4 in the high frequency band is prevented.

In addition, the inductor 402 is connected in series with the coupling capacitor 10 between the drain of the FET 4 in the first-stage amplifier circuit A and the gate of the FET 11 in the middle-stage amplifier circuit B.
Is set, and the inductance value of the inductor 402 is set to a value that causes series resonance in the high frequency range with the capacitance between the gate and the source of the FET 11 in the amplifier circuit B in the middle stage. A peaking circuit is formed by the capacitance between the gate and the source of the FET 11 to improve the gain characteristic in the high frequency range.

As described above, according to this embodiment, in the low range, the feedback amount of the parallel injection series feedback circuit is increased, and in the high range, the series feedback circuit by the inductor 27 is added to the FET 4 in the first-stage amplifier circuit A. By doing so, excellent input impedance matching characteristics can be obtained in a wide band from the low range to the high range. Further, by adding the inductor 28 to the coupling between the amplifiers A and B in the first and middle stages to form a peaking circuit, the gain characteristic in the high frequency band is improved and the gain deviation is reduced in the wide band from the low frequency band to the high frequency band. can do.

FIG. 4 is a circuit diagram showing still another embodiment of the multi-stage amplifier circuit according to the present invention. The parts corresponding to those in the above-mentioned drawings are designated by the same reference numerals and their duplicate description will be omitted.

As shown in FIG. 4, this embodiment is different from the embodiment shown in FIG. 3 in that the DC blocking capacitor 3 and the feedback resistor 8 are provided between the source and gate of the FET 4 in the first-stage amplifier circuit A. A negative feedback circuit composed of and is provided, and a parallel injection series negative feedback circuit composed of a capacitor 25 and a feedback resistor 26 and a double negative feedback circuit configuration are provided, whereby a parallel injection series feedback circuit alone is provided. It is possible to obtain even better input impedance matching characteristics.

Although the above-described embodiment has a three-stage configuration including the first-stage, middle-stage and last-stage amplifier circuits,
The present invention is not limited to this, and may have a configuration of four or more stages.

[0031]

As described above, according to the present invention,
Set the capacitance value that is series feedback to the signal frequency band to the capacitor that grounds the source of the FET in the middle stage amplifier circuit, and set the gate value of the FET in the first stage amplifier circuit and the source of the FET in the middle stage amplifier circuit. By using a parallel injection series negative feedback circuit with a capacitor between the two, compared to the case of using a conventional parallel negative feedback circuit, the input impedance matching characteristics are equivalent, but the gain reduction due to negative feedback is reduced. be able to.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a multistage amplifier circuit according to the present invention.

FIG. 2 is a diagram showing a difference in frequency characteristic depending on a feedback circuit method.

FIG. 3 is a circuit diagram showing another embodiment of the multistage amplifier circuit according to the present invention.

FIG. 4 is a circuit diagram showing still another embodiment of the multistage amplifier circuit according to the present invention.

FIG. 5 is a circuit diagram showing an example of a conventional multistage amplifier.

[Explanation of symbols]

 A first stage amplifier circuit B middle stage amplifier circuit, C last stage amplifier circuit 1 signal input terminal 2,3 DC blocking capacitor 4 FET 7 load resistor 8 feedback resistor 10 coupling capacitor 11 FET 14 load resistor 16 coupling capacitor 17 FET 20 Load Resistor 21 DC Blocking Capacitor 22 Signal Output Terminal 23 Power Supply Terminal 25 DC Blocking Capacitor 26 Feedback Resistor 27, 28 Inductor

Claims (4)

[Claims] 1. An amplifier circuit of at least two stages each formed on the same semiconductor substrate and having a field effect transistor, wherein a signal amplified by the amplifier circuit of the first stage is passed through a coupling capacitor to the amplifier circuit of the next stage. In the multistage amplifier adapted to supply the gate of the field effect transistor of
A source-grounded amplifier circuit in which a resistor and a capacitor are connected between grounds, wherein the capacitor in the first-stage amplifier circuit has a capacitance value that serves as a high-frequency ground for the signal frequency band, and The capacitors each have a capacitance value that provides series feedback to the signal frequency band, and the gate of the field-effect transistor in the first-stage amplifier and the source of the field-effect transistor in the second-stage amplifier circuit. A multi-stage amplifier comprising a parallel injection series negative feedback amplifier circuit in which a feedback circuit including a capacitor and a resistor is connected between the two, and the first-stage amplifier is input impedance matched to an input signal. 2. The multistage amplifier according to claim 1, wherein an inductor forming a series peaking circuit is provided as a coupling circuit of the first-stage amplifier circuit and the second-stage amplifier circuit. 3. The multistage amplifier according to claim 1, wherein a parallel negative feedback circuit including a feedback resistor is provided between the gate and the drain of the field effect transistor in the first stage amplification circuit. 4. The multistage amplifier according to claim 1, 2, or 3, wherein a bipolar transistor is used as an amplification element of the amplification circuit of each stage.