JPH08161829A - Digital information reproducing device and digital pll device - Google Patents

Abstract

PURPOSE: To obtain a digital information reproducing device which is operated by an asynchronous clock of a specified frequency and a digital PLL device which is operated by digital signal processing. CONSTITUTION: This digital information reproducing device includes an AD converter 6 which samples the reproduced signals front a recording medium 1 at a prescribed period, an arithmetic circuit 8 which calculates an approximation curve from (n) pieces of continuous sample values among the sample values sampled in such a manner and a reproducing means for reproducing recording information in accordance with the resulted approximation curve. The device also includes a subtractor 21 which calculates phase errors between the edge position to the asynchronous clock of the specified frequency of the reproduced signals and the phase value of the virtual synchronizing clock, a phase error cumulative calculating circuit 22 which makes cumulative calculation of the phase errors, a period register 23 which increases and decreases the periodic value of the virtual synchronizing clock according to the results of the cumulative calculation and means 24 to 27 which calculate the phase values of the virtual synchronizing clock in accordance with the periodic value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital information reproducing apparatus for reproducing information recorded on a recording medium such as an optical disk or a magnetic disk, and a PLL by digital signal processing.
The present invention relates to a digital PLL device that operates.

[0002]

2. Description of the Related Art FIG. 16 is a diagram showing a structure of a general digital information reproducing apparatus. In FIG. 16, reference numeral 51 is a recording medium such as an optical disk or a magnetic disk, and the information recorded on the recording medium 51 is optically or magnetically read by the sensor 52. The reproduced signal is amplified to a required level by the amplifier 53, and then the noise removal filter 54 removes high frequency noise or low frequency noise unnecessary for information reproduction. If necessary, a waveform equalizer 55 such as a transversal filter corrects the waveform to reduce the waveform interference in the signal. After this waveform correction, the reproduction signal is converted into a binary digital signal by the binarization circuit 56.

As the binarization circuit 56, in the case of mark position recording, the peak detection circuit for differentiating the reproduction signal to obtain the zero-crossing point, and in the case of mark edge recording,
A level slicing circuit is typically used to find the time when a predetermined slice level is crossed. In the PLL circuit 57,
A clock that is synchronized with the binarized digital signal is generated, and the discriminator 58 discriminates "1" or "0" from the binarized signal at the timing of the synchronous clock.
Then, the sync signal detection circuit 59 detects the timing at the beginning of the reproduced data string, and the decoder 60 outputs (1,
7) Codes, (2,7) codes, recording codes such as 8-9 codes, error correction codes, and information compression codes are decoded to restore the original digital reproduction data.

By the way, an analog low-pass filter or a VCO (voltage controlled oscillator) is usually used as the PLL circuit 57 of FIG.
Attempting to integrate the circuits after the waveform equalizer 55 with a digital IC causes a problem because analog components are included. Therefore, a digital PLL has been proposed, but normally a digital PLL requires an operating frequency (control clock) having a much higher recording frequency, and also requires a highly accurate variable delay element. for that reason,
When a digital PLL is used as the PLL circuit 57 of FIG. 16, it is necessary to operate the circuit at high speed, but such high speed operation is difficult.

Therefore, the applicant of the present invention has disclosed a binarization circuit and an information reproducing apparatus for solving the above problems.
It is disclosed in Japanese Patent No. 1822. FIG. 17 is a block diagram showing the information reproducing apparatus of the earlier application. As shown in FIG. 17, in the prior application, the PLL circuit is not used, and all the circuits are configured to operate with a constant asynchronous clock. Further, the AD converter 61 samples the reproduction signal with a constant clock, and the digital filter 62 and the CPU 6
The tri- and binarization circuits 64 also operate with the same constant clock.
In the FIFO 65, the binarized signals obtained by the binarization circuit 64 are aligned and output.

FIG. 18 shows an example of the binarization circuit 64 shown in FIG. 18, 71 and 72 are comparators for comparing the quantized reproduction signal calculated by the DF 62 of FIG. 17 with a reference value for binarization, and 73 and 74 are comparators 7 respectively.
One-shot multivibrator that outputs "L" level only for one sampling time from the time when the outputs of 1, 72 change from "H" level to "L" level, 75, 76
Is a latch circuit for temporarily holding the calculated quantized reproduction signal sent from the DF62 of FIG. 17, triggered by the output of the one-shot multivibrators 73, 74 changing from "H" level to "L" level, and 77 is It is a NAND gate that takes the logical sum of the one-shot multi-vibrators 73 and 74. Reference numeral 78 is an adder for adding the quantized reproduction signal levels held by the latch circuits 75 and 76, and 79.
Is a timing circuit for controlling the circuit in the subsequent stage according to the operation result of the adder 78, and 80 is the sampling clock 1/2
The frequency dividers 81, 82, 83, 84 for frequency division are respectively shown in FIG.
It is a logic gate that performs a logical operation as shown in. Furthermore,
Reference numeral 86 is a flip-flop that temporarily holds the output of the NAND gate 77.

Next, the operation of the prior application example of FIG. 17 will be described. First, an analog reproduction signal reproduced from an information recording medium (not shown) is processed by the A / D converter 61 to obtain the shortest code interval of the analog reproduction signal (hereinafter It is quantized into a digital reproduction signal at time intervals of half of (Tmin). A / D
In the digital reproduction signal quantized by the converter 61, waveform interference caused by high density recording is reduced by the digital calculation by the DF 62 and sent to the binarization circuit 64 in the state of the digital reproduction signal. At this time, the CPU 63 calculates an appropriate calculation coefficient for reducing the waveform interference of the analog reproduction signal according to the frequency component and the signal level of the analog reproduction signal reproduced from the information recording medium (not shown).
It is set to 2, and the best waveform interference reduction is attempted at any time. The digital reproduction signal sent to the binarization circuit 64 is
It is binarized into binary levels of "0" and "1". The binarized signal does not have a constant code phase, so the FIF
A binary codeword having a uniform phase is converted by O65 and converted into data by a decoder (not shown).

Next, taking the case where the reproduction signal reproduced from the information recording medium (not shown) in FIG. 17 is that of pit edge recording with 1-7 code modulation, the binarization circuit 64 is shown.
Will be described. Assuming that the maximum recording frequency of 1-7 code modulation pit edge recording is 6.25 MHz, the minimum code interval Tmin is 40 nsec. Therefore, one sampling interval is 20 nsec (sampling frequency =
50 MHz). Thus Tmin = 40nse
When a reproduction signal such as c is sampled at a sampling interval of 20 nsec, no matter what timing the reproduction signal is sampled, the number of times of sampling within Tmin is two. This means that the number of reproduction signals sampled from the time when the reproduction signal crosses the threshold value to the time when the reproduction signal next crosses the threshold value (hereinafter referred to as edge interval) is an integer multiple of 2. In FIG. 17, the number of samplings between edges is 4 times when the edge interval is 2T (80 nsec), and the edge interval of 3T (12
6 times at 0 nsec), and 16 times at 8T edge interval (320 nsec).

However, in reality, the edge interval of the reproduced signal is extremely rarely an integer multiple of Tmin due to various disturbances, which means that when the number of samplings between edges is 2T, the edge interval is four times. This means that the edge interval of 3T may not be 6 times, and similarly, the edge interval of 8T may not be 16 times. When the edge interval of each recording pattern when the edge interval changes in this way is defined as a regular edge interval ± (Tmin) / 2, 2T is 60 nsec or more and less than 100 nsec, and 3T is 100 n.
sec or more and less than 140 nsec, similarly 8T is 30
It becomes 0 nsec or more and less than 340 nsec, and the number of samplings between edges is amended as follows. That is, 2T
If the edge interval is 60 nsec or more and less than 100 nsec, 3 or 4 or 5 edge intervals of 3T are 100 nsec
If it is less than 140 nsec, 5 or 6 or 7, if the edge interval of 8T is 300 nsec or more and 340 nsec.
If it is less than 15, it will be 15, 16, or 17.

FIG. 19 shows the operation timing of the binarization circuit of FIG. The signal A represents a quantized reproduction signal which is the output of the DF 62 in FIG. 17, and in particular, what is indicated by a black circle is a sampling value when the comparator 71 or the comparator 72 crosses the threshold value as a result of comparison with the threshold value. Shows. The signal B is a sampling clock that determines the timing at which the reproduction signal reproduced from the information recording medium (not shown) in FIG. 17 is quantized by the A / D converter 61.
It is a clock of 0 MHz.

The signal C indicates the result of comparison between the quantized reproduction signal A calculated by the DF 62 and the threshold value by the comparator 71, and outputs "L" when the quantized reproduction signal> threshold value. Similarly, the signal D is output to DF by the comparator 72.
The result of comparison between the quantized reproduction signal A calculated by 62 and the threshold value is shown. When the quantized reproduction signal <threshold value, "L" is output. A signal E and a signal F indicate the outputs of the one-shot multivibrators 73 and 74, respectively, and a signal G indicates the output of the NAND gate 77 which takes the logical sum of the outputs of the one-shot multivibrators 73 and 74. The signal H and the signal I indicate the result obtained by dividing the sampling clock (signal B) by 1/2 by the frequency divider 80.
Is positive logic and the signal I is negative logic. Also, signal J is OR
The output of the gate 84 is shown, the signal K shows the output of the AND gate 85, and the signal L shows the output of the flip-flop 86.

Here, the number of samplings between edges when each edge interval is an integer multiple of Tmin is
4 samplings at 2T edge interval (80nsec) and 6 at 3T edge interval (120nsec)
Similarly, 14 samplings at the time of edge interval of 7T (280nsec), 8T
When the edge interval is (320 nsec), 16 samplings are performed. To explain the operation, first, DF6
The quantized reproduction signal A digitally calculated in 2 is supplied to the comparator 7
It is compared with a threshold value at 1, 72. As a result of this comparison, if the level of the quantized reproduction signal A crosses the threshold value, the comparators 71 and 72 change their outputs C and D from the “H” state to the “L” state or to the “L” state. Change from the state to the "H" state. Next, since the outputs C and D of the comparators 71 and 72 change from the “H” level to the “L” level,
In the one-shot multi-vibrators 73 and 74, the 1-shot multi-vibrators 73 and 74 are
The signals E and F that become "L" only during the sampling time are output, and the NAND gate 77 takes the logical sum of the outputs E and F of these one-shot multivibrators 73 and 74.

The output G of the NAND gate 77 is "H" only for one sampling from the time when the quantized reproduction signal crosses the threshold value. This means that the output G of the NAND gate 77 is "H". Means that the edge position of the reproduction signal exists within a certain time. Further, the sampling frequency of the reproduction signal is Tmi of the reproduction signal.
Since the time is half of n, the reproduced signal is binarized by converting the output signal G of the NAND gate 77 into a code word once every two samplings. Here, by dividing the sampling clock and using a signal (signal K) obtained by masking the sampling clock,
The flip-flop 8 outputs the output signal G of the NAND gate 77.
Binarization is achieved by temporarily holding it at 6.

As described above, in the prior application, as shown in FIG. 19, the reproduced signal values at two consecutive sampling points before and after the reproduced signal A exceeds the threshold value are stored in the latch circuits 75 and 76. Hold each and add the sum of both
Seeking in. From that value, the phase at which the threshold is passed, that is, the phase of the mark edge position with respect to the sampling clock, is obtained, and the mark length is determined using the number of clocks and the phase from one mark edge position to the next mark edge position. The reproduced data synchronized with a fixed clock is output according to the determined mark length.

Then, the following effects can be obtained in the digital information reproducing apparatus which operates with the asynchronous clock as shown in the prior application example. (1) Since the reproducing system can be made into a digital IC without using an analog IC such as a PLL-IC, the cost can be reduced. (2) Since the entire playback system can be integrated with a digital IC,
The size of the device can be reduced. (3) Since the tap gain of the transversal filter for waveform equalization can be easily switched by calculation, it is possible to easily deal with the difference in the characteristics of the recording medium. (4) It is possible to easily deal with frequency switching by calculation. (5) It is possible to cope with other differences in the recording condition and the reproducing condition by only the arithmetic processing without requiring a special circuit. (6) A single circuit with a single IC can support all types of models.

[0016]

By the way, in the above-mentioned prior application, the phase at the threshold crossing point is calculated and determined by adding the sample values before and after the threshold value. This means that the reproduced signal is approximated by a straight line that passes through the sample points at the two time points. In such a case, if the number of sample points is sufficiently large as shown in FIG. 19, the reproduced signal between the black point and the white point immediately before it in FIG. 19 is close to a straight line, and the error due to the linear approximation becomes small. It can be reproduced well.

However, when the number of sampling points decreases with respect to the reproduction signal frequency, the error due to the linear approximation increases, and the error occurrence rate of reproduction data increases.
That is, when the recording density or the recording speed is increased, the sampling frequency is relatively reduced with respect to the reproduction signal frequency due to the limitation of the IC speed, etc., and thus the reproduction performance is deteriorated and it is not possible to cope with the high density of information. It was

In view of the above-mentioned conventional problems, the present invention operates with an asynchronous clock having a constant frequency, and can reproduce information without lowering the reproduction performance even if the sampling frequency with respect to the reproduction signal frequency is low. It is an object of the present invention to provide a digital information reproducing device that can be used.

Further, according to the present invention, there is no restriction on the use of special parts and the operating frequency, and the digital P that can operate in the same manner as the analog PLL circuit by the digital signal processing.
It is an object to provide an LL device.

[0020]

SUMMARY OF THE INVENTION An object of the present invention is to provide a means for sampling a reproduction signal reproduced from an information recording medium at a predetermined cycle, and n consecutive sample values among the sampled sample values. The present invention is achieved by a digital information reproducing apparatus characterized by having a means for calculating an approximate curve and a reproducing means for reproducing recorded information based on the obtained approximate curve.

Another object of the present invention is to calculate a phase error between the edge position of the reproduced signal with respect to the asynchronous clock having a constant frequency and the phase value of the virtual synchronous clock, and a means for cumulatively calculating the phase error. And a means for increasing / decreasing the period value of the virtual synchronization clock according to a cumulative calculation result, and means for calculating the phase value of the virtual synchronization clock based on the period value. .

[0022]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a digital information reproducing apparatus of the present invention. In FIG. 1, the recording medium 1, the sensor 2, the amplifier 3, and the noise removal filter 4 are the same as those shown in FIG. 16, and the digital information recorded on the recording medium 1 is optically or magnetically detected by the sensor 2. Read by. Then, the read reproduction signal is amplified by the amplifier 3, the noise component is removed by the noise removal filter 4, and the signal is output to the AD converter 6.

The constant clock oscillator 5 is composed of a crystal oscillator or the like, and a clock signal of a constant frequency generated by the constant clock oscillator 5 is supplied to the AD converter 6 and the subsequent parts. The AD converter 6 samples the reproduction signal at a predetermined cycle according to the clock, and the sampled data is stored in the data buffer 7. Here, if the consecutive sampling times are simply t = −1,
When the sampling values of the reproduced signal at each time are represented as ₀ , ₁ , ₂ and y = y ₋₁ , y ₀ , y ₁ , y ₂ , a curve as shown in FIG. 2 is obtained. In this embodiment, FIG.
The reproduced signal waveform is curve-approximated by using the four x points, and a typical cubic curve, y = f (t) = at ³ + bt ² + ct + d, is used here as the curve approximation.

Here, when the above cubic curve is used, (t = −1, y = y ₋₁ ), (t = 0, y = y ₀ ),
One f (t) passes through four points (t = 1, y = y ₋₁ ) and (t = 2, y = y ₂ ). That is, y ₋₁ = f (−1) = − a + b−c + d y ₀ = f (0) = d y ₁ = f (1) = a + b + c + d y ₂ = f (2) = 8a + 4b + 2c + d a = (1/6) · (-y -1 + 3y 0 -3y 1 + y 2) b = (1/2) · (y -1 -2y 0 + y 1) c = (1/6) · (-2y The solution is ₋₁ −3y ₀ + 6y ₁ −y ₂ ) d = y ₀ .

The curve approximation calculation circuit 8 calculates these a, b, c and d. Since this calculation is performed for each sampling cycle, the data AD-converted by the AD converter 6 is stored in the data buffer 7 in the sampling order,
The curve approximation calculation circuit 8 reads out four consecutive data among these data as y _-1 , y ₀ , y ₁ and y ₂ and uses them to perform calculation to obtain a, b, c and d.
The curve-approximated signal data is appropriately processed according to the recording method. For example, with respect to a signal recorded by mark edge recording with RLL (run length limited) code such as (1,7) code, (2,7) code, 8-9 code, etc. As described above, it is necessary to determine the mark length by obtaining the intersection between the reproduction signal and the threshold value.

The edge position calculation circuit 9 calculates the intersection t = Z ₀ between the approximate curve and the threshold value. Here, when obtaining the intersection with the threshold value, the threshold value is set to y = 0.
Then, f (t) = 0, that is, the solution t = Z ₀ of at ³ + bt ² + ct + d = 0 can be obtained.
The formula for finding the solution of this cubic equation is generally known as Cardano's solution method. This formula is shown in Fig. 3, and three solutions of Z, Z ', and Z "in equations (1) and (2) are solutions to be obtained. In this case, the condition of y ₀ , y ₁ <0 is set in advance. If set, a zero-cross point exists within the range of 0 <t <1, so at this time, if 0 <Z ₁ <1, Z
Can be solved.

In this way, the edge position calculation circuit 9 performs the calculation and outputs the value of Z to the synchronous clock calculation circuit 10. However, since this calculation is complicated, the circuit scale is large and the processing time is also long. However, in the present embodiment only, this calculation is a calculation process for generating the synchronous clock, and the synchronous clock calculation Since the circuit 10 cumulatively calculates a plurality of phase data, the strictness of the Z precision is not so important depending on the calculation. Therefore, when there is a limitation on the scale of the arithmetic circuit or the processing time, this part may be calculated by conventional linear approximation instead of curve approximation. In that case, it may be approximated by a straight line passing through y ₀ and y ₁ , and specifically, the outputs y ₀ and y ₁ of the data buffer 7
Z = y ₀ / (y ₀ + y ₁ ) can be calculated and output using.

The synchronous clock calculation circuit 10 is a conventional PL.
The role of the L circuit is performed by arithmetic processing, and it constitutes a so-called digital PLL circuit. FIG. 4 shows an example of the synchronous clock calculation circuit 10, and FIG. 5 shows a conventional PLL circuit. The subtractor 21 in FIG. 4 functions as the phase comparator 28 in FIG. 5, and similarly, the phase error cumulative operation circuit 22 functions as the low-pass filter 29, and the cycle register 23, the phase register 24, the subtractor 25, and the positive / negative determination circuit. 26 and adder 27 are VCOs (voltage controlled oscillators)
Acts 30. Further, the synchronous clock calculation circuit 10 of FIG. 4 outputs the virtual synchronous clock phase value v, instead of outputting the synchronous clock of the PLL circuit.

More specifically, as shown in FIG. 6, the subtracter 21 first subtracts the virtual synchronization clock phase value v from the signal phase difference Z output from the edge position calculation circuit 9 to obtain the phase error value w. Output. Phase error cumulative operation circuit 22
Then, the phase error value w is fetched a plurality of times to calculate the average value. This is the same as the low-pass filter 29 of FIG. 5, and the virtual synchronization clock becomes more stable as the number of times of capturing increases,
The following speed with respect to the frequency fluctuation of Z becomes slow. An up / down counter is used as the period register 23, and the numerical value L is increased or decreased according to the phase error average value w. In this case, when the phase of the virtual synchronization clock is delayed compared to Z, if the value L of the period register 23 is decreased, the frequency of the virtual synchronization clock becomes higher, and conversely, the phase v of the virtual synchronization clock becomes larger than Z. If the value L of the period register 23 is increased while proceeding, the frequency of the virtual synchronization clock decreases.

The phase register 24 holds the virtual synchronous clock phase value v until the next calculation, and holds this held value S
Then, the subtractor 25 subtracts the sampling period value from S and outputs the obtained value to the positive / negative determination circuit 26 and the adder 27. Here, since the time is standardized by the sampling period, the sampling period value is 1. The value obtained by subtracting 1 from S of the subtracter 25 is set as u, and the positive / negative determination circuit 2
At 6, the sign of u is determined. Further, the adder 27 adds the output L of the period register 23 and the output u of the subtracter 25 only when the determination result of u of the positive / negative determination circuit 26 is negative,
The addition result is output as the virtual synchronization clock phase value v.
When the determination result of u is positive, the value of u is directly changed to v
Output as

FIG. 7 shows the timing of sampling and the timing of the virtual synchronous clock in the synchronous clock arithmetic circuit 10. The sampling time point is the sampling timing of the reproduced signal in the AD converter 6, the virtual synchronous clock is a clock that is not actually created, and is a virtual clock in the operation of the synchronous clock operation circuit 10. In FIG. 7, assuming that the phase register 24 holds the phase value S ₁ at the sampling time point 0, the subtracter 25 outputs a value u ₁ obtained by subtracting ₁ from S ₁ at the sampling time point 1. The positive / negative determination circuit 26 determines the positive / negative of u ₁ and outputs the determination result to the adder 27. Here, u ₁ is a negative (negative if u ₁ arrow leftward, in the case of rightward positive), by adding the period value L of the adder 27 in the u ₁ and cycle register 23, the results Output as the phase value v ₁ . This phase value v ₁ is held in the phase register 24 until the next calculation.

FIG. 8 shows the signal of each part at each sampling time point. Calculation 1 in FIG. 8 corresponds to sampling time 1 in FIG. 7, calculation 2 corresponds to sampling time 2, and calculation 3 corresponds to sampling time 3. In operation 1,
As described above, the output of the phase register 24 is S ₁ , the subtractor 2
The output of 5 is u ₁ , the output of the positive / negative determination circuit 26 is negative, and the output of the adder 27 is v ₁ .

Next, at the sampling time point 2, as shown in FIG. 7, in the subtractor 25, the sampling cycle value 1 from the previous phase value S ₂ (same as v ₁ ) held in the phase register 24.
Output the value u ₂ obtained by subtracting the, the sign determining circuit 26 u ₂
Is determined to be positive or negative. In this case, u ₂ is determined to be positive,
Since the adder 27 this time is positive u _2, and outputs the value of u ₂ directly as v _2. Of course, v ₂ is held in the phase register 24. At timing point 3,
As shown in FIG. 7, in the subtractor 25, the value u obtained by subtracting 1 from S _3
3 is output, and the positive / negative determination circuit 26 determines u ₃ to be negative. Therefore, in this case, the adder 27 adds the period value L ′ of the period register 23 and u ₃ and outputs the result as v ₃ , and in the same manner, the synchronous clock calculation circuit 10 similarly outputs the virtual synchronous clock at each sampling time point. The phase value is calculated. The signals of the respective parts at the sampling time points 2 and 3 are as in the operations 2 and 3 in FIG.

Next, in the level calculation circuit 11, as shown in FIG. 2, the curve-approximated signal level value at the time v of the synchronous clock calculation circuit 10 is calculated. That is, using a, b, c, d obtained by the curve approximation operation circuit 8 and v obtained by the synchronous clock operation circuit 10, Y = av ³ + bv ² + cv + d is calculated, and the obtained signal level is obtained. Waveform equalizer 1 with value Y
Output to 2. However, when v> 1, the next time is waited without performing the calculation.

The waveform equalizer 12 is used as necessary,
Especially when recording is performed by the partial response method, waveform equalization by the waveform equalizer 12 is essential. FIG. 9 shows a specific example of the waveform equalizer 12, which is configured to process the operation of the conventional transversal filter by calculation. C _-2 in _{FIG, C -1, C 0, C} 1, C 2 is a weighting factor, this factor is automatically switched by the characteristics and recording and reproduction condition recording medium 1 under the control of the CPU 16. For example, when the recording medium 1 is recorded by the PR (1,1) method, the output Y ′ of the waveform equalizer 12 is set to a value close to a ternary level, and PR (1,2,1) is set. ) System, the CPU 16 outputs an appropriate weighting coefficient Ci to the waveform equalizer 12 so that the output Y'has a value close to the five-valued level.

In the level judgment circuit 13, the signal level value Y
The level is determined for (Y ′ when waveform equalization is performed). In the case of normal binary recording, binary determination is performed, and in the case of recording by the partial response method, it is general to carry out Viterbi decoding for level determination. For example, in the level determination circuit 13, in the case of the PR (1,1) system, 3
After the value determination, binary data is generated by Viterbi decoding, and in the case of PR (1,2,1), binary data is generated by Viterbi decoding after performing five-value determination. Also,
FIFO (First In First Out Register)
14, the output signals are aligned in the same manner as the FIFO 65 of FIG. 17, and the decoder 15 also has the decoder 60 of FIG.
Similarly, the decoding of the recording code, the decoding of the error correction code, or the decoding of the data compression code is performed and the reproduction data is output.

In the present embodiment, a digital information reproducing apparatus which operates with an asynchronous clock can be realized, and the above (1) to (6)
As mentioned in the section above, not only can the playback system be converted to a digital IC, which can greatly contribute to the miniaturization and cost reduction of the device, but also to the difference in the characteristics of the recording medium, the frequency switching, and the difference in the recording / reproducing conditions. It is possible to deal with. Further, since the reproduction signal is approximated to the curve by the curve approximation calculation circuit based on the sample value of the reproduction signal, the signal processing error can be significantly reduced as compared with the prior application example, and the processing accuracy can be improved. . Therefore, since the reproduction error rate can be improved, the reproduction performance can be improved, and even if the sampling frequency with respect to the reproduction signal frequency is low, the signal processing error is small and the information can be sufficiently reproduced,
It is also possible to support high density information.

Furthermore, since the PLL operation is performed by the arithmetic processing in the synchronous clock arithmetic circuit, a highly accurate variable delay element like a conventional digital PLL or a high operating frequency is required. Without, it is possible to easily realize a digital PLL circuit by digital signal processing. Therefore, by using such a digital PLL circuit, it can be easily made into a digital IC with another reproducing system. Further, by constructing the digital information device by the digital PLL operation by such a synchronous clock operation circuit and the curve approximation of the reproduction signal by the curve approximation operation circuit, it is possible to easily cope with reproduction of multi-valued levels. it can. Especially this
This is effective in an embodiment of reproducing information of the multi-valued recording method which will be described later in detail with reference to FIG.

In the above description, the (1,7) code,
Although RLL codes such as (2,7) code and 8-9 code were assumed, the present invention is also applicable to reproduction of recording using a difference detection code such as 4/15 code and 4/11 code. You can FIG. 10 shows an example of the 4/15 code conversion table. This is a code mainly used in the recording of the sample servo system, and four of the 15 bits are "1", and when reproducing, four bits are determined as "1" in descending order of 15 bits. Is used for code conversion. In the 4/15 code, the PLL generates a synchronous clock with reference to a separately provided clock pit. Also in this method, by using the present invention, it is possible to detect data accurately without a PLL.

FIG. 11 is a block diagram showing an embodiment applicable to such a 4/15 code. In FIG. 11, the peak position calculation circuit 31 is a circuit that calculates the peak position of the clock pit, and its operation will be described later. The clock pit extraction circuit 32 is a circuit for removing pits other than correct clock pits by pattern matching. The synchronous clock calculation 10 is the same as that of FIG.
The LL circuit functions to calculate and output the virtual synchronization clock phase value v. Recording medium 1, sensor 2, amplifier 3, adhesive removal filter 4, constant clock oscillator 5, AD converter 6,
The data buffer 7, the curve approximation calculation circuit 8, the level calculation circuit 11, and the waveform equalizer 12 are the same as those in FIG. Further, the difference detection determination circuit 33 is a circuit that determines 4 bits in the descending order of the operation value Y ′ for 1 block of 15 bits as “1” and the rest as “0”. The data thus detected by the difference detection determination circuit 33 is sent to the 4/15 code decoding circuit 34, and inverse conversion is performed according to the conversion table of FIG. The FIFO 14 and the decoder 15 are the same as those in FIG. In this embodiment, since the data is detected by the difference detection method, there is an advantage that the reproduction reliability is high with respect to the low frequency noise of the reproduction signal and the DC level fluctuation.

Further, in the above embodiment, the cubic curve is used as the approximate curve, but in the case of mark position recording, it is conceivable that the curve is approximated by the quadratic curve. As a binarization circuit in mark position recording, a method of detecting a peak position by using a differentiation detection circuit including a differentiation circuit 25 and a hysteresis comparator 26 is generally used as shown in FIG. FIG. 13 shows a method of detecting the peak position of the reproduced signal in the differential detection circuit by quadratic curve approximation. To detect the peak position, as shown in FIG.
The values of three consecutive samples y _-1 , y ₀ , y ₁ sampled by the asynchronous clock are used. Here, a quadratic curve approximation, as y = f (t) = at 2 + bt + c, f (-1) = y 1, f (0) = y 0, f (1) = Substituting y _1, a, b, and c can be obtained as follows.

A = (Y _-1 + Y ₁ + 2Y ₀ ) / 2 b = (Y ₁ -Y _-1 ) / 2 c = Y ₀ Further, the peak position is t = -b / 2a, and the phase of this t is Output the value.

Such peak position calculation may be used in the embodiment shown in FIG.
It can also be used for 7) mark position recording and (2, 7) mark position recording reproduction. Further, in the above description, the quadratic curve y = at ² + bt + c is converted into y ₋₁ , y
_Although it was determined from three points of ₀ , y ₁ , y _-1 , y ₀ , y
_A quadratic curve y = 4 from ₁ and y ₂ using the least squares method.
It is also possible to obtain at ₂ + bt + c. in this case,
Although the calculation becomes complicated, a more accurate peak position can be obtained.

Next, an embodiment of the multi-value recording system will be described. The multi-value recording method is a method of modulating with a signal of three values or more for higher density. As a modulation method, for example, in the case of an optical disc, a method of making the modulation pulse width multi-valued, a method of making the pulse height multi-valued, and putting "1" and "0" between "1" and "0" There is a method of repeatedly recording at high speed and switching to high speed to record an intermediate value. 14 in FIG.
A 4B3T code is shown as an example of the value code. this is,
It is for converting 4-bit information into 3-valued 3-digits.

FIG. 15 is a block diagram showing an embodiment which can be applied to the information reproduction of the signal recorded by the multilevel recording system as described above. In FIG. 15, the level determination is performed by the ternary level determination circuit 35, and the ternary signal obtained by the binary decoding circuit 36 is inversely converted according to the encoding table of FIG. These two points are different in the embodiment of FIG. Further, in the edge position calculation circuit 9, since it is a ternary signal here and the slice level is 2, the calculation corresponding to it is necessary. As described above, in the multi-value recording method, the slice level becomes plural and the level determination circuit becomes complicated. However, in the present embodiment, the reproduction of the multi-valued signal can be easily realized only by changing the calculation. .

[0046]

As described above, the present invention has the following effects. (1) It is possible to realize a digital information reproducing apparatus that operates with an asynchronous clock of a constant frequency, thereby making it possible to reduce the size and cost of the apparatus, as well as the characteristics of recording media, frequency switching, and recording conditions. It can be easily adapted to different playback conditions or any model. (2) Since the reproduction signal processing is performed by curve approximation based on the sample value of the reproduction signal, the signal processing error can be reduced and the processing accuracy can be improved. Therefore,
Even if the sample frequency is lower than the reproduction signal frequency, the information can be sufficiently reproduced, which enables the information to be reproduced even when the recording density is increased or the recording speed is increased. Can also respond. (3) By digitally performing a PLL operation by arithmetic processing and performing reproduction signal processing by curve approximation,
It is possible to easily cope with the reproduction of multi-valued levels which has not been conventionally assumed. (4) Since the PLL operation is performed by arithmetic processing, a digital PLL that does not require a highly accurate variable delay element or a high operating frequency, has a simple configuration, and has no restriction on the operating frequency. A device can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a digital information reproducing apparatus of the present invention.

FIG. 2 is a diagram for explaining curve approximation of a reproduction signal in a curve approximation calculation circuit 8 of the embodiment of FIG.

FIG. 3 is a diagram showing Cardamo's solution method for obtaining a solution of a cubic equation.

FIG. 4 is a diagram showing a synchronous clock operation circuit 1 in the embodiment of FIG.
It is the block diagram which showed the specific example of 0.

FIG. 5 is a block diagram showing a conventional PLL circuit.

6 is a subtracter 21 of the synchronous clock calculation circuit 10 of FIG.
6 is a diagram for explaining a phase error value w between the signal phase value Z and the virtual synchronization clock phase difference v in FIG.

FIG. 7 is a diagram for explaining the operation of the synchronous clock operation circuit 10 of FIG.

8 is a diagram showing signals of respective parts for each operation of the synchronous clock operation circuit 10 of FIG.

9 is a diagram showing a specific example of the waveform equalizer 12 of the embodiment of FIG.

FIG. 10 is a diagram showing an example of 4/15 code conversion.

FIG. 11 is a block diagram showing another embodiment of the present invention.

FIG. 12 is a diagram showing a binarization circuit in mark position recording.

FIG. 13 is a diagram for explaining a method of detecting a peak position of a reproduction signal in a differential detection circuit by quadratic curve approximation.

FIG. 14 is a diagram showing conversion of a 4B3T code.

FIG. 15 is a block diagram showing still another embodiment of the present invention.

FIG. 16 is a block diagram showing a conventional digital information reproducing apparatus.

FIG. 17 is a block diagram showing an information reproducing apparatus of the applicant's earlier application.

18 is a block diagram showing a binarization circuit of the information reproducing apparatus in FIG.

19 is a time chart showing the operation of the binarization circuit of FIG.

[Explanation of symbols]

 1 Recording Medium 5 Constant Clock Oscillator 6 AD Converter 7 Data Buffer 8 Curve Approximation Calculation Circuit 9 Edge Position Calculation Circuit 10 Synchronous Clock Calculation Circuit 11 Level Calculation Circuit 12 Waveform Equalizer 13 Level Judgment Circuit 14 FIFO 15 Decoder 16 CPU 21 , 25 Subtractor 22 Phase error accumulation arithmetic circuit 23 Period register 24 Phase register 26 Positive / negative determination circuit 27 Adder 31 Peak position arithmetic circuit 32 Clock pit extraction circuit 33 Difference detection determination circuit 34 4/15 Code decoder 35 Three-value level determination Circuit 36 Binary Decoding Circuit

Claims (4)

[Claims] 1. A means for sampling a reproduction signal reproduced from an information recording medium at a predetermined cycle, and a means for calculating an approximated curve from consecutive n sample values of the sampled sample values. And a reproducing means for reproducing the recorded information based on the approximated curve. 2. The digital information reproducing apparatus according to claim 1, wherein the reproducing means substitutes the synchronous clock phase value into the approximate curve expression of the approximate curve calculating means to obtain the level value of the reproduced signal on the approximate curve. A digital information reproducing apparatus characterized by detecting data by performing a level judgment of a signal level value obtained by calculation. 3. A means for calculating a phase error between an edge position of a reproduced signal with respect to an asynchronous clock having a constant frequency and a phase value of a virtual synchronous clock, a means for cumulatively calculating the phase error, and a means for calculating the cumulative error. A digital PLL device comprising: a means for increasing / decreasing a cycle value of the virtual synchronization clock; and a means for calculating a phase value of the virtual synchronization clock based on the cycle value. 4. The digital PLL device according to claim 3, wherein the virtual synchronous clock phase value computing means holds the previous phase value, and a sampling cycle for sampling the reproduction signal from the previous phase value. A digital subtraction means, a means for judging whether the subtraction result is positive or negative, and a means for adding the period value of the virtual synchronous clock and the output of the subtracting means in accordance with the positive or negative judgment result. PLL device.