JPH08167661A - Semiconductor memory integrated circuit - Google Patents

Abstract

PURPOSE: To raise integration of a memory cell and to enable quick operation of a logic gate circuit by using n-type polysilicon for an n-channel MOS transistor and p-type polysilicon for a p-channel MOS transistor as a gate, respectively. CONSTITUTION: In a complementary logic gate of a memory cell 110 wherein quick operation is required, n-polysilicon of low work function is used as a gate for n-channel MOS transistors 11b, 11d, 11e, 11f and p-polysilicon of higher work function is used as a gate for p-channel MOS transistors 11a, 11c. Thereby, each threshold voltage of the n-channel MOS transistors 11b, 11d to 11f and the p-channel MOS transistors 11a, 11c can be practically reduced. In the process, an interval between the n-channel MOS transistors 11b, 11d to 11f and the p-channel MOS transistors 11a, 11c is set at 1μm or more.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to semiconductor devices, and more particularly to a semiconductor memory integrated circuit including a logic circuit including p-channel transistors and n-channel transistors formed on the same semiconductor substrate. Since MOS transistors have low power consumption, they are widely used in various applications such as logic integrated circuits and memory integrated circuits. In such a MOS integrated circuit, the current driving capability is improved in the logic integrated circuit, and the storage capacity is increased in the case of the memory integrated circuit, so that the integration density is improved by miniaturization. In particular, a semiconductor memory integrated circuit has a memory cell array formed by arranging memory cell transistors for storing information, and a logic circuit for selecting a memory cell transistor in the memory cell array and writing and / or reading information to the selected memory cell transistor. And are formed on the same semiconductor substrate.

In particular, in today's miniaturized semiconductor integrated circuits, a low power supply voltage is used in response to the miniaturization of elements in view of reliability problems caused by hot carriers, including semiconductor memory integrated circuits. However, since the use of such a low power supply voltage results in a decrease in signal logic amplitude, it is necessary to lower the threshold voltage of the MOS transistor in response to the decrease in power supply voltage in order to achieve the desired operation speed improvement. There is.

[0003]

2. Description of the Related Art An n-channel MOS transistor and a p-channel M, which have been conventionally used in semiconductor memory integrated circuits.
In a complementary MOS logic gate in which an OS transistor is combined, an n-type doped polysilicon pattern is generally used as a gate for both an n-channel MOS transistor and a p-channel MOS transistor. When n-type polysilicon is used as a gate electrode of a p-type MOS transistor as described above, a so-called buried channel in which a conductive region is formed by impurity doping in the vicinity of the surface of the channel region is used to suppress the threshold voltage of the transistor to a low level. The MOS transistor which it has is used. For example, in a p-channel type MOS transistor, a p-type region corresponding to a channel region is formed on the surface of an n-type substrate by ion implantation of impurities.

FIG. 14 shows an example of a MOS transistor having a buried channel of such a conventional structure. Referring to FIG. 14, the transistor is formed on an n-type Si substrate 1, and is a p ⁺ -type source region 1a and a drain region 1 separated from the source region by a channel region 1c.
b and a gate electrode 2 made of n ⁺ -type polysilicon formed on the channel region and separated by a gate oxide film (not shown). The surface of the substrate 1 is the channel region 1c. Correspondingly to p-type.

However, when a MOS transistor having such a buried type channel is used in an integrated circuit having a high integration density, for example, an electric field due to the drain voltage applied to the drain region 1b penetrates into the channel region 1c and the threshold of the transistor is reached. The so-called short channel effect in which the value voltage changes appears remarkably. In other words, in today's logic gates that are required to operate at high speed, as long as the buried channel structure is adopted, if the threshold voltage is lowered and the drain current is increased, the short channel is increased when the integration density is increased. There is a problem that it is difficult to suppress the effect.

In order to solve the problem of the conventional logic gate having the buried channel structure, in the MOS transistor having the normal surface channel structure as shown in FIG. 15, n-type polysilicon is used for the gate electrode of the n-channel transistor. A so-called dual-gate MOS transistor has been proposed in which p-type polysilicon is used for the gate electrode of the p-channel transistor. However,
15, parts corresponding to those in FIG. 14 are designated by the same reference numerals, and description thereof will be omitted. In the configuration of FIG. 15, it can be seen that the channel region 1c ′ is formed as a part of the surface of the n-type Si substrate 1 instead of the p-type channel region 1c.

Generally, the threshold voltage of a MOS transistor is
Pressure V_THIs an n-channel MOS transistor
Formula V_TH = (φ_M−φ_S) + 2φ_B+ √ [2ε_SqN (2φ_B+ V_BS)] / C_OX In the case of (1), and in the case of a p-channel MOS transistor, the formula V_TH = (φ_M−φ_S) + 2φ_B−√ [2ε_SqD (2φ_B+ V_BS)] / C_OX It is given by (2). However, φ_MIs the work function of the gate electrode,
φ_SIs the work function of the substrate, φ_BIs the Fermi potency of the substrate
Ar, ε_SIs the dielectric constant of silicon, q is the elementary charge, and N is n
D is the acceptor concentration of the channel MOS transistor
It represents the donor concentration of the p-channel MOS transistor. It
In addition, V_BSIs the substrate bias voltage, and C _OXIs the gate acid
Indicates the capacitance per unit area of the chemical film.

Referring to the equations (1) and (2), in the n-channel MOS transistor, by using the n ⁺ -type polysilicon for the gate electrode on the p-type substrate, the equation (1) is obtained.
The middle first term (φ _M −φ _S ) becomes negative and the first and third terms cancel each other out, resulting in a decrease in the threshold voltage V _TH . Similarly, in the p-channel MOS transistor as well, by using p ⁺ -type polysilicon for the gate electrode, the first and third terms in formula (1) cancel each other out, and the absolute value of the threshold value decreases.

The above theoretical explanation applies to the buried channel type MOS transistor shown in FIG. 14 and the dual gate type MOS transistor shown in FIG. 15 in the same manner. Since the depletion region associated with the pn junction is formed between the region 1a or the drain region 1b and the channel region 1c ', the short channel effect is substantially reduced.

However, when a general integrated circuit is formed on the same semiconductor substrate using the p-channel MOS transistor and the n-channel MOS transistor having the dual gate structure as shown in FIG. 15, the gate electrode is formed. polysilicon pattern is, because in the region where the n-channel MOS transistor is formed on the n ⁺ -type, in the region where the p-channel MOS transistor is formed is doped p ⁺ -type, n ⁺ -type MOS transistor and the p ⁺ A pn junction is formed at the boundary with the type MOS transistor, and the rectifying action of the pn junction causes a problem that a desired operation cannot be obtained or the operation becomes unstable. In order to avoid the formation of the pn junction in the gate electrode, it is necessary to form separate gate electrode patterns for the p-channel MOS transistor and the n-channel MOS transistor, but such a configuration complicates the wiring pattern. However, there are problems that the manufacturing cost of the semiconductor integrated circuit is increased and that the integration density is improved. The pn junction formed on the gate electrode pattern can be eliminated by forming a refractory metal silicide in a region of the gate pattern where the pn junction is formed. Such local formation of silicide is possible by applying a so-called salicide method which has been conventionally used to reduce the gate resistance. The inventor of the present invention previously proposed in Japanese Patent Application Nos. 6-27146 and 6-183159 a method of manufacturing an SRAM memory cell using the salicide method.

[0011]

However, since the impurity element in silicide has a diffusion coefficient several orders of magnitude higher than that in Si, silicide is generally formed at the junction between the p-type polysilicon pattern and the n-type polysilicon pattern. If this is the case, the heat treatment should be kept to a minimum to prevent unnecessary diffusion of impurities (eg RTA; Rapid Thermal Anneal
ing method), and it is necessary to secure a sufficient space between the n-channel MOS transistor and the p-channel MOS transistor. For example, when Co silicide is formed at the junction of the p-type polysilicon pattern and the n-type polysilicon pattern by annealing at 800 ° C. for 30 seconds, at least 1.0 μm is provided between the p-channel MOS transistor and the n-channel MOS transistor. , Preferably 2.
It is necessary to secure an interval of 0 micron or more. But,
If the distance between the p-channel MOS transistor and the n-channel MOS transistor is set large as described above, the integration density of the integrated circuit using the p-channel MOS transistor and the n-channel MOS transistor inevitably decreases.

Therefore, it is a general object of the present invention to provide a new and useful semiconductor integrated circuit which solves the above problems. A more specific object of the present invention is to provide a semiconductor memory integrated circuit including a logic circuit composed of MOS transistors having a low threshold voltage and a memory cell array having a high integration density.

[0013]

According to the present invention, there is provided a semiconductor substrate as set forth in claim 1; a first and a first semiconductor substrate formed on the semiconductor substrate, each of which is cross-connected to each other. A plurality of memory cells each composed of a flip-flop composed of two inverters; a semiconductor memory formed on the semiconductor substrate and comprising a complementary logic gate circuit composed of an n-channel MOS transistor and a p-channel MOS transistor In an integrated circuit: In each of the plurality of memory cells, the first and second inverters are both p-channel MO connected in series.
Each of the first and second inverters includes an S transistor and an n-channel MOS transistor, and each of the first and second inverters extends between the p-channel MOS transistor and the n-channel MOS transistor forming the inverter and has a gate of each MOS transistor. Serving as a single semiconductor pattern, the single semiconductor pattern having the same work function in both the p-channel MOS transistor and the n-channel MOS transistor forming the inverter; the complementary logic circuit. And the p-channel MOS transistor has a second semiconductor pattern as a gate electrode, and the first semiconductor pattern has the first semiconductor pattern as a gate electrode. Lower than 2 semiconductor patterns A semiconductor memory integrated circuit having a work function; wherein in the complementary logic circuit, the first semiconductor pattern and the second semiconductor pattern are short-circuited with a semiconductor metal compound, or As described in claim 2, in the complementary logic circuit, the gate electrode of the n-channel MOS transistor and the gate electrode of the p-channel MOS transistor are formed at a distance of at least 1 μm or more. 2. The semiconductor memory integrated circuit according to claim 1, wherein the metal compound extends at least 1 μm or more between the gate electrode of the n-channel MOS transistor and the gate electrode of the p-channel MOS transistor. Or as described in claim 3,
In the complementary logic circuit, the first semiconductor pattern and the second semiconductor pattern include a first region defined in a single semiconductor pattern and a second region separated from the first region. 3. A region is formed, and the metal compound is formed between the first region and the second region in the single semiconductor pattern. The semiconductor memory integrated circuit of
Alternatively, in the complementary logic circuit according to claim 4, both of the first and second semiconductor patterns are made of silicon, and the first semiconductor pattern is n.
5. The semiconductor memory integrated circuit according to claim 3, wherein the second semiconductor pattern is doped p-type, and the second semiconductor pattern is p-type doped, or the metal compound is silicided as described in claim 5. The semiconductor memory integrated circuit according to any one of claims 1 to 4 or, in the complementary logic gate circuit according to claim 6, the p-channel MOS transistor. The active region in which the
The semiconductor memory integrated circuit according to claim 1, characterized in that it is at least 1 μm away from an active region in which a channel MOS transistor is formed, or the first part constituting the memory cell as described in claim 7. The semiconductor memory integrated circuit according to claim 7, wherein the single semiconductor pattern is made of n-type polysilicon in each of the second and second inverters.

[0014]

According to the present invention, in a complementary logic gate which is required to operate at high speed, n-type polysilicon having a low work function is used as a gate for an n-channel MOS transistor, and a work function is improved for a p-channel MOS transistor. By using high p-type polysilicon as the gate,
The n-channel MOS transistor and the p-channel M
The threshold voltage of each of the OS transistors can be substantially reduced. At that time, in the semiconductor memory integrated circuit, the complementary logic gates forming the peripheral circuit are not required to have a particularly high integration density, unlike the memory cell array, so that the p-channel MOS transistor and the n-channel MOS transistor forming the complementary logic gates are not required. Transistor spacing can be set well, typically 1 micron or more. As a result, the p-type polysilicon pattern forming the gate electrode of the p-channel MOS transistor and the n-channel MOS are formed.
Even if a region made of a metal compound such as silicide is formed at the junction of the n-type polysilicon pattern forming the gate electrode of the transistor, the dopant in the n-type polysilicon pattern is p-type polysilicon pattern through the metal compound region. The problem of in-diffusion or similar diffusion of dopants in the p-type polysilicon pattern into the n-type polysilicon pattern is avoided.

On the other hand, in the first and second inverters forming the memory cell, the p-channel MOS transistor merely forms the load resistance of the n-channel MOS transistor, so that a particularly large current driving capability is not required. Therefore, by using an n-type polysilicon pattern for the gate electrode of the n-channel MOS transistor forming the flip-flop in the memory cell, it becomes possible to induce the state transition of the flip-flop with a signal having a low logic amplitude. The speed of writing information to the cell is improved. On the other hand, such an n-channel MOS
Since the p-channel MOS transistor connected in series with the transistor only acts as a load resistance as described above, even if the same n-type polysilicon pattern as that of the n-channel MOS transistor is used for the gate, it is disadvantageous in operation. Never be. That is, in each inverter, a single n-type pattern continuously extending between the n-channel MOS transistor and the p-channel MOS transistor is used as a gate electrode to realize a high integration density in a memory cell. In addition, the manufacturing process can be simplified. In other words, in the present invention, in the memory cell array which requires a particularly high integration density, the p-channel MOS is used.
High integration density can be achieved by forming the gate electrode, which continuously extends between the transistor and the n-channel MOS transistor, with a single n-type polysilicon pattern having the same work function.

That is, according to the present invention of claim 1, a semiconductor memory integrated circuit including a high speed logic gate circuit composed of MOS transistors having a low threshold voltage and a memory cell array having a high integration density is provided. A circuit can be constructed. According to the present invention as set forth in claims 2 and 6, by forming the p-channel MOS transistor and the n-channel MOS transistor at a distance of 1 μm or more in the logic gate circuit constituting the memory integrated circuit, the first and the second Interdiffusion of the dopants in the first semiconductor pattern and the dopants in the second semiconductor pattern is avoided when the second semiconductor pattern is short-circuited by forming a metal compound. In the memory integrated circuit, the complementary gate circuit that constitutes the peripheral circuit is not required to have high integration density as in the memory cell array, and thus the p-channel MOS transistor and the n-channel MOS transistor are formed separately from each other. There is no problem.

According to the third aspect of the present invention, the gate pattern of each of the p-channel MOS transistor and the n-channel MOS transistor forming the logic gate circuit is formed by a single semiconductor pattern. A desired logic gate circuit can be formed.
According to the present invention as set forth in claim 4, by doping the gate pattern of the n-channel MOS transistor forming the logic gate circuit to the n-type and the gate pattern of the p-channel MOS transistor to the p-type, a desired threshold value is obtained. The voltage can be reduced, and as a result, high-speed operation of the logic gate circuit can be realized.

According to the present invention of claim 5, by using a silicide as the metal compound, a polysilicon gate pattern extending between the p-channel MOS transistor and the n-channel MOS transistor is selected at an intermediate portion thereof. By selectively reacting with a refractory metal, a logic gate circuit having a desired structure can be easily formed by using a known side (self-aligned silicide) process. At that time, p-channel MOS transistor and n
Since it is formed 1 μm or more apart from the channel MOS transistor, it is possible to avoid mutual diffusion of the dopant between the n-type gate pattern and the p-type gate pattern due to the formation of the silicide.

According to a seventh aspect of the present invention, the gate pattern of the p-channel MOS transistor and the n-channel MOS transistor in the inverter forming the memory cell is a single n-type polysilicon pattern. The layout of the memory cells can be simplified, and a memory cell array with high integration density can be formed by a simple process.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings. FIG. 1 is a plan view showing the overall configuration of a semiconductor memory integrated circuit according to an embodiment of the present invention. Referring to FIG. 1, a semiconductor memory integrated circuit is formed on a Si substrate 10 and stores a memory cell 110 for storing information.
And a peripheral circuit 12 for selecting a memory cell in the memory cell array 11 or for writing and / or reading information in the selected memory cell. For example, the peripheral circuit 12 is supplied with the address data and reads the data read from the decoder that selects the corresponding bit line BL or the word line WL, or the selected memory cell 110 via the corresponding bit line BL. Includes a sense amplifier. Generally, the memory cell array 11
Are required to have a high integration density so that as much information as possible can be stored, whereas the peripheral circuit 12 is required to operate as fast as possible.

FIG. 2 is a circuit diagram showing the structure of the memory cell 110 which constitutes the memory cell array 11 in FIG. Referring to FIG. 2, the memory integrated circuit shown in FIG.
The memory cell 110, which constitutes M, includes a p-channel MOS transistor 11a and an n-channel MOS transistor 11
a first inverter 11A configured by connecting b and b in series
And a second inverter 11B configured by connecting a p-channel MOS transistor 11c and an n-channel MOS transistor 11d in series.
1A and 11B are cross-connected as usual to form a flip-flop. That is, the gate of the transistor 11a and the gate of the transistor 11b are commonly connected to the common connection node D2 of the transistors 11c and 11d, and the gates of the transistors 11c and 11d are commonly connected to the transistor 11a.
And the common connection note D1 of the transistor 11b.

Further, as in the case of a normal SRAM,
Node D1 is connected to bit line BL via n-channel MOS transistor 11e, and node D2 is complementary bit line / via n-channel MOS transistor 11f.
Connected to BL. Also, transistors 11e and 1
1f is controlled via the word line WL. That is,
By supplying write data to the memory cell 110 selected by activating the word line WL via the bit lines BL and / BL, the state of the flip-flops constituting the memory cell 110 is changed by the write data. Transition. On the other hand, when reading information from a memory cell, the word line W corresponding to the selected memory cell
The voltage of the nodes D1 and D2, which is activated on L and appears on the bit lines BL and / BL, is detected by the sense amplifier included in the peripheral circuit 12.

In the flip-flop constituted by the inverters 11A and 11B, the one driven according to the bit line voltage on the bit line BL or / BL is:
n-channel MOS transistors 11b and 11d, and p-channel MOS transistors 11a and 11c
Respectively constitute the load resistances of the transistors 11b and 11d, respectively. That is, in the memory cell 110, in order to write the write data at high speed, the n-channel MOS transistors 11b and 11 are used.
d is required to have a low threshold voltage, but p
Channel MOS transistors 11a and 11c need not necessarily have a low threshold voltage.
On the other hand, such a memory cell 110 is required to have a layout structure as simple as possible so that the memory cell array 11 has a high integration density.

On the other hand, in the SRAM memory integrated circuit shown in FIG. 1, the peripheral circuit 12 needs to operate at high speed in order to realize high-speed access. Peripheral circuit 12 generally includes a decoder or a latch circuit which is supplied with address data and selects a corresponding word line or bit line, or a sense amplifier. The circuits constituting peripheral circuit 12 are generally shown in FIG. Based on complementary logic gates.

Referring to FIG. 3, the complementary logic gate is
p-channel MOS transistor 12a and n-channel MO
The inverter 120 is formed by connecting the S transistors 12b in series, and the gate of the transistor 12a and the gate of the transistor 12b are commonly connected to the input terminal IN. The output terminal OUT is connected to the common connection node D3 of the transistors 12a and 12b.

FIG. 4 shows the memory cell array 1 shown in FIG.
1 shows the layout of the memory cell 110 in FIG. 1, and FIG. 5 is a sectional view taken along the line AA ′ in FIG. However, FIGS. 4 and 5 show only the flip-flop portion of the memory cell 110. Referring to FIG. 4, the Si substrate 10 is p
4 and is covered with a field oxide film 10F (see FIG. 5), which is not shown in FIG. 4, and has a substantially T-shaped active portion corresponding to the memory cell 110 on the field oxide film. Region 10A and substantially U-shaped active region 10
B is formed. However, as shown in the cross-sectional view of FIG. 5, the active region 10A is formed in the p-type substrate 10.
Formed in the mold well 10 ₁ .

Further, a pair of polysilicon patterns 111A and 111B extending substantially in parallel are formed on the field oxide film. Polysilicon pattern 111
A and 111B are the active regions 10A and 10B.
5, the surface of the substrate 10 is contacted through a thin gate oxide film (not shown) through the cross-sectional view of FIG.
In addition, the field oxide film 10F on the right side of the active region 10B
A polysilicon pattern forming the word line WL extends on the upper side in a direction substantially orthogonal to the polysilicon patterns 111A and 111B.

As a result of this structure, the active region 10A has
A channel region (not shown) of the p-channel MOS transistor 11a described with reference to FIG. 2 is formed corresponding to the polysilicon pattern 111B, and p ⁺ -type that forms the source and drain regions of the transistor 11a on both sides of the pattern 111B. A region (not shown) is formed. Similarly, the polysilicon pattern 111 is formed in the active region 10A.
The p-channel MOS transistor 11c corresponding to A
Channel region (not shown) is formed, and p ⁺ -type regions (not shown) forming the source and drain regions of the transistor 111c are formed on both sides of the pattern 111A. Similarly, in the active region 10B, a channel region of the transistor 11d corresponding to the polysilicon pattern 111A and a channel region of the transistor 11b corresponding to the polysilicon pattern 111B are formed. Among them, the drain region of the drain region and the transistor 11c of the transistor 11a is in the active region 10A, commonly formed by p ⁺ -type diffusion region between the polysilicon pattern 111A and the polysilicon pattern 111B, such p ⁺ -type diffusion Active area 1 corresponding to the area
A drain contact region 10a is formed at 0A.
Similarly, the drain region of the drain region and the transistor 11d of the transistor 11b is in the active region 10B, in common, it is formed by n ⁺ -type diffusion region between the polysilicon pattern 111A and the polysilicon pattern 111B, such n ⁺ -type diffusion Active area 10B corresponding to the area
A drain contact region 10b is formed on the top. As can be seen from the circuit diagram of FIG. 2, the power supply voltage V _DD is supplied to the contact region 10a and the contact region 10b is also supplied.
Is supplied with a reference voltage V _SS .

Each of the word line WL and the polysilicon patterns 111A and 111B has an insulating pattern 11 having an elongated planar shape corresponding to the respective pattern shape.
1C, the opening 111C ₁ is formed on the insulating pattern 111C at a position corresponding to the field oxide film 10F existing between the active regions 10A and 10B, corresponding to the polysilicon pattern 111A. An opening 111C ₂ is formed corresponding to the silicon pattern 111B, and a silicide layer 111a is formed on the surface of the polysilicon pattern 111A corresponding to the opening 111C ₁ . Similarly, the polysilicon pattern 111B
A silicide layer 111b is formed on the surface of the substrate corresponding to the opening 111C ₂ .

Further, on the field oxide film 10F, an elongated W or T having a branch 111d ₁ is formed so as to contact the source regions of the transistors 11c and 11d in the active regions 10A and 10B.
An iN pattern 111D ₁ (W pattern in the following description) is formed. Similarly, an elongated W pattern 111D ₂ having branches 111d ₂ so as to contact the source regions of the transistors 11a and 11b, respectively.
Is formed. At that time, the branch 111 of the pattern 111D ₁
d _1, the in silicide region 111b is connected to the polysilicon gate patterns 111B, branches 111d ₂ pattern 111D ₂ Similarly, the silicide region 1
At 11a, it is connected to the polysilicon gate pattern 111a.

That is, the W pattern 111D ₁ forms the inverter 11B shown in FIG. 2 by connecting the transistors 11c and 11d in series at their respective sources. Similarly,
The W pattern 111D ₂ connects the transistors 11a and 11d in series at their respective sources to form the inverter 11A shown in FIG. Furthermore, the branch 111d ₂ of W pattern 111D branches 111d ₁ of ₁ and W111D ₂ connecting cross and the inverter 11A and 11B, the results Figure 2
The flip-flop shown in is formed.

In FIG. 4, it can be further seen that in active region 10B, n-channel MOS transistors 11f and 11e are formed corresponding to the intersections of word lines WL. The bit lines BL, / B are formed in the active region 10B on the drain side of the transistors 11e and 11f.
Contact regions 10c and 10d for L are formed respectively.

In the memory cell having the structure shown in FIG. 4, the gate patterns 111A and 111B are both made of n ⁺ -type doped polysilicon, and as a result, the memory cell is formed into n-type as described later. It can be formed by simple patterning of the ⁺ type polysilicon layer. In other words, the memory cell shown in FIG. 4 can be manufactured with high integration density and at low cost. Further, by combining the n ⁺ -type polysilicon gates with the n-channel MOS transistors 11b and 11d forming the main part of the flip-flop, the transistors 11b and 11d can be formed.
It is possible to substantially reduce the threshold voltage of. On the other hand, the p-channel MOS transistor 11a
And 11c, the threshold voltage cannot be reduced, but
As described above, the transistors 11a and 11
It is not necessarily required to have a low threshold voltage, since c simply acts as a load resistance for transistors 11b and 11d.

Next, the configuration of the inverter 120 constituting the logic gate circuit 12 of FIG. 1 will be described with reference to the plan view of FIG. 6 and FIG.
This will be described with reference to the sectional view of FIG. However, FIG.
It is a sectional view taken along the line BB 'in the middle. Referring to FIGS. 6 and 7, the inverter 120 includes an active region 1 defined in the field oxide film 10F covering the surface of the Si substrate 10.
The active region 10H is formed corresponding to the n-type well 10 ₂ formed in the p-type substrate 10. That is, the active region 10G is p-type and the active region 10H is n-type. Also,
Similar to a normal MOS transistor, the active regions 10G and 10F are both thin gate oxide films (not shown).
Covered by

A gate pattern 121 made of polysilicon is formed on the field oxide film 10F in the active region 10G.
It is formed so as to extend continuously up to 10H. p
Portions of the type active region 10G on both sides of the gate pattern 121 are n ⁺ -type doped, and as a result, the region 10G has the n-channel MOS transistor 12b shown in FIG.
Is formed. Further, in the n-type active region 10H, the portions on both sides of the gate pattern 121 are p ⁺ -type doped,
As a result, the p-channel MO shown in FIG. 3 is formed in the region 10H.
The S transistor 12a is formed. As shown in FIG. 6, the active region 10G includes a drain contact 10G ₁ and a source contact 10 corresponding to the n ⁺ type diffusion region.
A drain contact 10H ₁ and a source contact 10H ₂ are formed in G _{2 and} in the active region 10H, corresponding to the p ⁺ type diffusion region. Source contact 10H
_{By connecting 1} and the source contact 10H ₂ with a conductor pattern, the inverter 120 shown in FIG. 3 is formed.

In the structure of FIG. 6, the polysilicon pattern 121 has a portion 12 extending over the p-type active region 10G.
1a is n-type, and part 1 extends over the n-type active region 10H
21b is p-type doped. As a result, the active region 10
Both the n-channel MOS transistor 12a formed in G and the p-channel MOS transistor 12b formed in the active region 10H have a low threshold voltage and a large current driving capability.

Further, in the structure of FIG. 6, in the polysilicon pattern 121, in order to prevent the n-type region 121a and the p-type region 121b from directly contacting each other to form a pn junction, the region is formed. A polysilicon region 121c is formed between 121a and 121b, and a region 121
From the area 121a to the area 121b on the surface of a to 121c.
The silicide region 121d is formed continuously.

Referring to the sectional view of FIG. 7, sidewalls 121u and 121v made of SiO ₂ are formed at both ends of the polysilicon pattern 121, and a silicide layer 121d is formed on the surface of the polysilicon pattern 121.
It can be seen that it extends from the regions 121a to 121b. The formation of the silicide region 121c is performed in the opening 1
It is formed by reacting the polysilicon pattern exposed at 22a with a refractory metal such as Co. The formation of such a silicide is typically performed at 800 ° C. for 30 seconds at RT.
According to the present invention, the distance S between the active region 10G and the active region 10H is at least 1 μm.
As described above, preferably set to 2 μm or more, the n-type dopant in the polysilicon region 121a and the p-type dopant in the polysilicon region 121b are interposed through the silicide region 121c through the heat treatment process for the silicide region 121c. It is possible to avoid the mutual diffusion. Although other similar logic gate circuits are formed in FIG. 6, the description thereof is omitted.

The memory cell 110 shown in FIGS.
The manufacturing process of the inverter 120 shown in FIGS. 6 and 7 will be briefly described. First, the manufacturing process of the memory cell 110 will be described with reference to FIGS. 8 (A) to (D), 9 (E) to (H) and FIG.
Description will be made with reference to (G) to (L). However, FIG.
9A is a plan view, and FIG. 9B is a line A in FIG. 8A.
FIG. 6A shows a cross-sectional view taken along the line A ′. Other Figures 8 (B) -10
The same correspondence relationship holds for (L).

First, in the steps of FIGS. 8A and 8B, the p-type Si substrate 1 having the n-type well 10 ₁ formed therein is formed.
0 on the surface of 0 by the LOCOS method
0F to define active areas 10A and 10B. Furthermore, on the surface of the active regions 10A and 10B,
A gate oxide film (not shown) having a thickness of typically about 7 nm is normally formed by a thermal oxidation process.

Next, in the steps of FIGS. 8C and 8D, a polysilicon layer 111 is deposited on the structure thus obtained by the CVD method to a thickness of typically 180 nm. Then, ion implantation is further performed to dope this into n ⁺ type. Further, a SiO ₂ film 112 is formed on the polysilicon layer 111 by CVD to have a thickness of 100 nm. As a result, the structures shown in FIGS. 8C and 8D are obtained.

Next, in the steps shown in FIGS. 9E and 9F, an opening 112A is formed in the SiO ₂ film 112 so that the regions 111a and 111b shown in FIG. 4 are exposed. Corresponding to the regions 111a and 111b, the openings 112A are staggered regions (112A).
It is composed of ₁ and (112A) ₂ . Furthermore, FIG.
In the steps shown in (G) and (H), the polysilicon layer 1
11 is patterned together with the SiO ₂ film 112 thereon to form the polysilicon gate pattern 111A shown in FIG.
And 111B are formed, and BF is formed in the active region 10A.
₂ ⁺ ions at an acceleration voltage of 25 keV of 2 × 10 ¹⁵ cm ^-2
P-channel MOS transistor 1
Source and drain regions 1a and 11c are formed. Similarly, 25 ⁺ As ⁺ ions are added to the active region 10B.
Ion implantation was performed at an acceleration voltage of keV and a dose of 2 × 10 ¹⁵ cm ⁻² , and n-channel MOS transistors 11b and 1
Form 1d source and drain.

Further, patterns 111A and 111B
Another SiO on top₂A film (not shown) is formed by CVD to about 1
It is deposited to a thickness of 00 nm, and this is subjected to reactive ion etching.
Regions 111a and 111b by the RIE method.
By etching vertically until exposed, the policy
The recon patterns 111A and 111B are the area 111
SiO except for a and 111b₂Covered with pattern 111C
A structure having the cross section shown in FIG. 9 (H) is obtained. Figure
9 (H), polysilicon is taken in the A-A ′ cross section.
While the surface of the pattern 111A is exposed,
The silicon pattern 111B is SiO₂Pattern 111
You can see that it is covered with C. In addition, the cross section of FIG.
Then, the sidewalls of the polysilicon patterns 111A and 111B
Also SiO ₂What is protected by the pattern 111C
Recognize.

In the steps of FIGS. 9G and 9H, as a result of the patterning of the polysilicon layer 111, the word line WL is formed in addition to the gate patterns 111A and 111B, and the As ⁺ ion ions described above are formed. In the implantation step, diffusion regions of the transistors 11e and 11f are formed in regions on both sides of the word line WL in the active region 10B. Next, in the steps of FIGS.
Co film (not shown) on the structure obtained in (G) and (H)
Is deposited by sputtering, and the structure thus obtained is reacted by an RTA process at 800 ° C. for 30 seconds to form a Co silicide layer 111a on the surface of the polysilicon pattern 111A.

Further, in the steps of FIGS. 10K and 10L, the W layer is deposited as a local wiring material to a thickness of about 80 nm, and by patterning this, the pattern 111D ₁ shown in FIG. 111D ₂ is formed. FIG.
As can be seen from the cross section of 0 (L), the W pattern 111
D ₁ extends across the polysilicon pattern 111B,
The silicide region 111a is connected to the transistors 11a and 1a.
Connect to source region 1b. Similarly, although not appearing in the cross-sectional view of FIG. 10L, the W pattern 111D ₂ extends across the polysilicon pattern 111A and connects the silicide region 111b to the source regions of the transistors 11c and 11d. As a result, the two inverters 11A,
The memory cell 110 shown in FIG. 2 in which 11B are cross-connected is formed.

Next, the manufacturing process of the inverter 120 constituting the logic gate circuit shown in FIGS.
This will be described with reference to (C), FIG. 12 (D), (E) and FIG. 13 (F). In the step of FIG. 11A, the field oxide film 10F forms the active regions 10G and 10H on the p-type Si substrate 10 in which the n-type well 10 ₂ is formed by the normal LOCOS method as described above. Formed to define. Furthermore, active regions 10G and 10H
A gate oxide film (not shown) having a thickness of typically 7 nm is formed on the upper surface of the polysilicon pattern 1 by a normal thermal oxidation process, and is further patterned.
The polysilicon layer forming 21P is formed by the CVD method.
It is deposited to a thickness of about 180 nm.

Next, in the step of FIG.
A resist exposing the active region 10G on the structure of (A).
Active layer of the polysilicon layer 121P by forming a mask
As in the part corresponding to 10G⁺Ions are typically added
High-speed voltage 25 keV, dose 2 × 10^Fifteencm^-2Inject with
Then, this is doped to be n-type. Next, the process of FIG.
In connection with the process of forming a memory cell shown in FIG.
Described as SiO₂The film 112 is formed on the entire surface of the substrate by the CVD method.
Deposited by and then removed from the logic gate circuit area
Is done. Therefore, the structure thus obtained is logical
In the portion where the gate circuit is formed, FIG.
Will be the same as Further obtained in this way
A resist mass exposing the active region 10H on the structure.
To form an active region 10H of the polysilicon layer 121P.
BF in the part corresponding to₂ ⁺Ions are typically accelerated
Pressure 25 keV, Dose amount 2 × 10 ^Fifteencm^-2Inject with
It is doped p-type.

Next, in the step of FIG. 12D, the polysilicon layer 121P is patterned to form the gate pattern 121.
Forming a further use of the gate pattern 121 as a self-aligned mask, the active region 10H of the wells 10 _2, p
The p ⁺ type source region 10HS and the drain region 10HD of the channel MOS transistor 12a are formed by ion implantation of BF ²⁺ . However, FIG. 12D is a cross-sectional view taken in a plane perpendicular to the extending direction of the polysilicon gate pattern in the active region 10H. An ion implantation process using the same gate pattern 121 as a self-alignment mask is also performed in the active region 10G, and the n-channel MO
An n ⁺ type source region and a drain region (not shown) of S transistor 12b are formed.

Further, an SiO ₂ film (not shown) is deposited so as to fill up the polysilicon pattern 121, and the structure thus obtained is subjected to a general anisotropy which acts substantially perpendicularly to the main surface of the substrate. Etching is performed, and FIG.
As shown in (E), sidewalls 121w and 121x are formed on both sides of the polysilicon pattern 121. However, although FIG. 12E is a sectional view taken along a plane orthogonal to the extending direction of the polysilicon pattern 121 as in FIG. 12D, the active region 10G and the active region 10H in FIG.
12D showing a cross-sectional view in the active region 10H in that it is a cross-section on the field oxide film 10F located in the middle of.

Next, in the structure of FIG.
By depositing the refractory metal layer 124 such as the above and heat-treating it by the RTA process, the structure shown in FIG. 7 in which cobalt silicide is formed on the entire surface of the gate region is obtained. Here, the refractory metal layer 124 is not limited to Co, and other refractory metals such as W and Mo can also be used.

In the structure of FIG. 7, by setting the length S of the polysilicon pattern region 121c to 1 μm or more, preferably 2 μm or more, the n-type dopant and the p-type polysilicon region in the n-type polysilicon region 121a are set. The p-type dopant in 121b is the silicide region 12
The problem of mutual diffusion through 1c is avoided, and the n-channel MOS transistor formed in the active region 10G and the p-channel MOS transistor formed in the active region 10H are both low threshold voltage and large current drive capability. Have. Since such a logic gate circuit is formed in the peripheral circuit portion 12 of the memory semiconductor integrated circuit as shown in FIG. 1, increasing the distance between the active regions 10F and 10G in this way reduces the integration density. But no problem occurs.

Although the present invention has been described above with reference to the preferred embodiments, the present invention is not limited to such embodiments, and various modifications and changes can be made within the scope of the present invention.

[0053]

According to the present invention as set forth in claim 1, a semiconductor memory integrated circuit having a high speed logic gate circuit composed of MOS transistors having a low threshold voltage and a memory cell array having a high integration density is provided. A circuit can be constructed. More specifically, by using an n-type polysilicon pattern for the gate electrode of an n-channel MOS transistor forming a flip-flop in a memory cell, it is possible to induce a state transition of the flip-flop with a signal of low logic amplitude. Therefore, the writing speed of information to the memory cell is improved. On the other hand, since the p-channel MOS transistor connected in series to the n-channel MOS transistor only acts as a load resistance, there is no operational disadvantage even if the n-type polysilicon pattern is used for the gate. In each inverter, by using a single gate pattern that continuously extends between the n-channel MOS transistor and the p-channel MOS transistor, it is possible to realize a high integration density in the memory cell, and The manufacturing process can be simplified.

According to the present invention as set forth in claims 2 and 6,
By forming a p-channel MOS transistor and an n-channel MOS transistor at a distance of 1 μm or more in a logic gate circuit forming a memory integrated circuit, thereby forming a metal compound for the first and second semiconductor patterns. Interdiffusion of the dopants in the first semiconductor pattern and the dopants in the second semiconductor pattern during short circuit is avoided. In a memory integrated circuit, a complementary gate circuit that constitutes a peripheral circuit is not required to have a high integration density like a memory cell array, and thus a p-channel MOS transistor and an n-channel M
There is no problem even if they are formed separately from the OS transistor.

According to the third aspect of the present invention, the gate pattern of each of the p-channel MOS transistor and the n-channel MOS transistor forming the logic gate circuit is formed by a single semiconductor pattern. A desired logic gate circuit can be formed.
According to the present invention as set forth in claim 4, by doping the gate pattern of the n-channel MOS transistor forming the logic gate circuit to the n-type and the gate pattern of the p-channel MOS transistor to the p-type, a desired threshold value is obtained. The voltage can be reduced, and as a result, high-speed operation of the logic gate circuit can be realized.

According to the fifth aspect of the present invention, by using silicide as the metal compound, the polysilicon gate pattern extending between the p-channel MOS transistor and the n-channel MOS transistor is selected at the intermediate portion thereof. By selectively reacting with a refractory metal, a logic gate circuit having a desired structure can be easily formed by using a known side (self-aligned silicide) process. At that time, p-channel MOS transistor and n
Since it is formed 1 μm or more apart from the channel MOS transistor, it is possible to avoid mutual diffusion of the dopant between the n-type gate pattern and the p-type gate pattern due to the formation of the silicide.

According to a seventh aspect of the present invention, the gate pattern of the p-channel MOS transistor and the n-channel MOS transistor in the inverter forming the memory cell is a single n-type polysilicon pattern. The layout of the memory cells can be simplified, and a memory cell array with high integration density can be formed by a simple process.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a semiconductor memory integrated circuit according to the present invention.

FIG. 2 is a circuit diagram showing a configuration of a memory cell of the semiconductor memory integrated circuit of FIG.

FIG. 3 is a circuit diagram showing complementary logic gates that form a logic gate circuit of the semiconductor memory integrated circuit of FIG.

FIG. 4 is a plan view showing a layout of the memory cell of FIG. 2 on a semiconductor substrate.

5 is a cross-sectional view showing a cross section of the memory cell of FIG. 4 taken along the line AA ′.

FIG. 6 is a plan view showing a layout of the complementary logic gate of FIG. 3 on a semiconductor substrate.

FIG. 7 is a cross-sectional view showing a cross section of the complementary logic gate of FIG. 6 along the line BB ′.

8A to 8D are views (No. 1) showing a step of forming the memory cell of FIG. 4;

9 (E) to 9 (H) are views (No. 2) showing a process of forming the memory cell of FIG.

10 (I) to (L) are views (No. 3) showing steps of forming the memory cell of FIG. 4;

11A to 11C are views (No. 1) showing a step of forming the complementary logic gate of FIG. 7.

12 (D) and 12 (E) are views (No. 2) showing a process of forming the complementary logic gate of FIG. 7.

13F is a view (No. 3) showing a step of forming the complementary logic gate of FIG. 7. FIG.

FIG. 14 is a diagram showing a configuration of a conventional MOS transistor having a buried channel.

FIG. 15 is a diagram showing a configuration of a conventional MOS transistor having a surface channel.

[Explanation of symbols]

1, 10 Si substrate 1a, 1b diffusion region 1c buried channel 1c 'surface channel second polysilicon gate electrode 101, 10 ₂ wells 10a, 10b, 10c, 10d, 10G 1, 10
G ₂ , 10H ₁ , 10H ₂ contact region 10A, 10B active region 10F field oxide film 11 memory cell array 11A, 11B inverter 11a, 11c p-channel MOS transistor 11b, 11d, 11e, 11f n-channel MOS transistor 12 peripheral circuit 12a p-channel MOS transistor 12b n-channel MOS transistor 110 memory cell 111A, 111B polysilicon gate pattern 111a, 111b silicide region 111C ₁ , 111C ₂ opening 111D ₁ , 111D ₂ local wiring pattern 120 complementary inverter circuit 121 polysilicon gate pattern 121a n ⁺ -type region 121b p ⁺ -type region 121c silicide regions 121P polysilicon layer 122 insulating layer pattern 122A insulating layer 12 a opening 123 resist pattern 123a resist opening portion 124 a refractory metal layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 27/092

Claims (7)

[Claims] 1. A semiconductor substrate; a plurality of memory cells formed on the semiconductor substrate, each of which comprises a flip-flop composed of first and second inverters, which are cross-connected to each other; and on the semiconductor substrate. In a semiconductor memory integrated circuit formed and comprising a complementary logic gate circuit composed of an n-channel MOS transistor and a p-channel MOS transistor: in each of the plurality of memory cells, the first and second inverters , Each including a p-channel MOS transistor and an n-channel MOS transistor connected in series, and each of the first and second inverters includes the p-channel MOS transistor and the n-channel MO transistor forming the inverter.
The semiconductor pattern includes a single semiconductor pattern extending between the S transistors and acting as a gate of each MOS transistor, the single semiconductor pattern including a p-channel MOS transistor and an n-channel MO transistor forming the inverter.
All S-transistors have the same work function; the n-channel MO forming the complementary logic circuit.
The S transistor has a first semiconductor pattern as a gate electrode, and the p-channel MOS transistor has a second semiconductor pattern.
Of the semiconductor pattern as a gate electrode, the first semiconductor pattern has a lower work function than the second semiconductor pattern; in the complementary logic circuit, the first semiconductor pattern and the second semiconductor pattern are provided. The semiconductor pattern is a semiconductor memory integrated circuit characterized by being short-circuited with a semiconductor metal compound. 2. In the complementary logic circuit, the gate electrode of the n-channel MOS transistor and the gate electrode of the p-channel MOS transistor are at least one.
The metal compound is formed with a distance of at least 1 μm, and the metal compound extends at least a distance of at least 1 μm between the gate electrode of the n-channel MOS transistor and the gate electrode of the p-channel MOS transistor. The semiconductor memory integrated circuit according to claim 1, wherein 3. The complementary logic circuit according to claim 1, wherein
And the second semiconductor pattern form a first region defined in a single semiconductor pattern and a second region separated from the first region, and the single semiconductor pattern In the pattern, the first region and the second region
3. The semiconductor memory integrated circuit according to claim 1, wherein the metal compound is formed between the semiconductor memory integrated circuit and the region. 4. In the complementary logic circuit, the first
4. The second and third semiconductor patterns are both made of silicon, the first semiconductor pattern is n-type doped, and the second semiconductor pattern is p-type doped. Semiconductor memory integrated circuit. 5. The semiconductor memory integrated circuit according to claim 1, wherein the metal compound is silicide. 6. In the complementary logic gate circuit, an active region in which the p-channel MOS transistor is formed is separated from an active region in which the n-channel MOS transistor is formed by at least 1 μm. Item 2. A semiconductor memory integrated circuit according to item 1. 7. The semiconductor memory integrated circuit according to claim 7, wherein in each of the first and second inverters forming the memory cell, the single semiconductor pattern is made of n-type polysilicon.