JPH08167576A - Forming method of heteroepitaxial semiconductor substrate, compound semiconductor device provided therewith, and manufacture thereof - Google Patents

Abstract

PURPOSE: To prevent the surface of a second III-V compound semiconductor layer from getting rough so as to obtain a hetero-epitaxial substrate with an even surface by a method wherein aluminum is added to the second III-V compound semiconductor layer formed on a first III-V compound semiconductor layer. CONSTITUTION: A first III-V compound semiconductor layer 22a is deposited as thick as 10 to 20nm on an Si substrate 22 kept at 300 to 400 deg.C. A second III-V compound semiconductor layer 22b is deposited as thick as 200 to 700nm at 500 to 600 deg.C on the first III-V compound semiconductor layer 22a. Furthermore, a third III-V compound semiconductor layer 22c is deposited as thick as 0.5 to 1.5pμm on the second III-V compound semiconductor layer 22b, when aluminum is added to the second II-V compound semiconductor layer 22b. By this setup, the surface of the second III-V compound semiconductor layer 22b is prevented from getting rough, and a hetero-epitaxial substrate provided with an even surface can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to semiconductor devices, and more particularly to a compound semiconductor device having a heteroepitaxial semiconductor substrate and a method for manufacturing the same. Group III-V compound semiconductors are characterized by a band structure that gives high electron mobility, and are widely used in high-speed semiconductor devices such as MESFETs, HEMTs, and HBTs. Further, many compound semiconductors have a direct transition type band structure, and are therefore widely used in optical semiconductor devices.

Generally, such a compound semiconductor device has a Ga
A compound semiconductor wafer, which is formed on a compound semiconductor wafer cut out from an ingot of a III-V group compound semiconductor crystal such as As, or on a compound semiconductor layer formed by epitaxial growth on a Si wafer, but cut out from the ingot The former method using the method has a problem in that it is difficult to grow a large crystal, which increases the manufacturing cost of the semiconductor device. In addition, since compound semiconductor substrates are generally heavy and fragile, it is difficult to handle them, and there arises a problem that the yield tends to be lowered particularly when a wafer having a large diameter is used. On the other hand, in the latter configuration,
It is considered that a large-diameter Si wafer, which is inexpensively manufactured by the established technology, can be used as a substrate base, and the manufacturing cost of the compound semiconductor device can be significantly reduced.

[0003]

On the other hand, there is a significant difference in lattice constant and thermal expansion coefficient between Si and a compound semiconductor crystal such as GaAs. As a result, when a compound semiconductor layer is epitaxially grown on a Si wafer, various differences occur. Difficulties arise. For example, there is about 4% strain between the lattice constant of Si and the lattice constant of GaAs. Similarly, Si
There is a doubling between the coefficient of thermal expansion of 1 and the coefficient of thermal expansion of GaAs. In such a state, S
Even if a GaAs layer is simply deposited on the i substrate, a desired high quality single crystal layer cannot be obtained.

In order to solve this problem and grow a single crystal layer of a III-V group compound semiconductor on a Si substrate, JP-A-59-59
-19762 has a first temperature on the Si substrate lower than the normal growth temperature, typically about 400 to 500 ° C.
The step of depositing a GaAs layer of, and then the first G
The second G is formed on the aAs layer at a normal temperature of about 700 ° C.
A method for manufacturing a heteroepitaxial substrate is proposed, which comprises a step of epitaxially growing an aAs layer. According to this method, during the low temperature growth, the first GaAs layer is formed on the Si substrate as a crystal layer in a state considered to be close to an amorphous state. further,
By growing the second GaAs layer on the first GaAs layer at a normal growth temperature of about 700 ° C., the first GaAs layer has a predetermined orientation with respect to the crystal orientation of the substrate. Crystallize as a single crystal layer having. As a result, a single-crystal GaAs layer as a whole is formed as an epitaxial layer on the Si substrate from the first and second GaAs layers.

Further, Japanese Patent Application Laid-Open No. 1-290220 discloses that a process in the range of 550 to 600 ° C. is performed between the step of forming the first GaAs layer and the step of forming the second GaAs layer. Discloses a method for manufacturing a heteroepitaxial substrate in which a GaAs layer is deposited to reduce the defect density in the epitaxial layer.

[0006]

By the way, in the heteroepitaxial substrate formed by such a conventional two-step or three-step growth process, irregularities are generally formed on the surface in many cases. This is considered to be because when the crystal layer grows, three-dimensional growth occurs instead of the desired two-dimensional growth, and as a result, an island structure is formed in the compound semiconductor crystal layer. Such unevenness is transferred to the active layer of the semiconductor device formed on the heteroepitaxial substrate and deteriorates the operating characteristics of the semiconductor device. In particular, in a high-speed semiconductor device such as HEMT, which operates on the principle of high-speed transport of electrons in a two-dimensional electron gas, such irregularities of the active layer cause undesirable effects such as carrier scattering.

Further, in the conventional hetero-epitaxial substrate, the sheet resistance of the obtained substrate is generally 300 to 40.
The value becomes as low as 0 Ω / □, which causes a problem that element isolation in an integrated circuit formed on a substrate becomes defective. It is considered that this is because the heat treatment is performed in arsine (AsH ₃ ) in the prebaking step of removing the oxide film on the Si substrate surface in the conventional heteroepitaxial substrate manufacturing process. More specifically, in the conventional process for manufacturing a heteroepitaxial substrate, As in arsine is typically 1000 ° C.
As a result of the heat treatment carried out at a moderate temperature, it diffuses to the surface of the Si substrate and is doped to be n-type. In order to avoid the problem of undesired As doping of the Si substrate, it has been proposed to perform prebaking in H ₂ without using arsine in the prebaking of the Si substrate in the related art. At most 600-700 Ω /
□ Only improved to a certain degree. This is because the compound semiconductor layer near the Si substrate interface contains dislocations at a very high density, and Si in the Si substrate is transferred to GaA through the dislocations.
It is thought that this is because it diffuses in the s layer and is doped. Therefore, the conventional heteroepitaxial substrate has a problem that sufficient element isolation cannot be obtained when forming an integrated circuit of a compound semiconductor device with a high integration density.

Therefore, the present invention provides a novel and useful heteroepitaxial semiconductor substrate that solves the problems of the conventional techniques, a compound semiconductor device using such a heteroepitaxial semiconductor substrate, and a method of manufacturing such a compound semiconductor device. That is the general purpose. A more specific object of the present invention is to provide a method for manufacturing a semi-insulating hetero-epitaxial substrate having a high resistivity, which suppresses the three-dimensional growth of a III-V group compound semiconductor layer on the surface of a Si substrate. Another object of the present invention is to provide a compound semiconductor device and a method for manufacturing such a compound semiconductor device.

[0009]

According to the present invention, there is provided the above-mentioned object of providing a first substrate on a Si substrate as described in claim 1.
Depositing a III-V group compound semiconductor layer by setting a substrate temperature in a first temperature range; and depositing a second III-V group compound semiconductor layer on the first III-V group compound semiconductor layer. And setting the substrate temperature to a second temperature range higher than the first temperature range, and depositing; a third III-V compound on the second III-V compound semiconductor layer. A step of depositing a semiconductor layer by setting a substrate temperature in a third temperature range higher than the second temperature range, and depositing the semiconductor layer in the second group III-V compound semiconductor layer. Is A
The first temperature is in the range of 300 to 400 ° C., and the second temperature is It is in the range of 500 to 600 ° C, and the third
Is in the range of 650 to 750 ° C. According to the method of manufacturing a compound semiconductor device according to claim 1, or as described in claim 3, the first III-
Depositing a Group V compound semiconductor layer, and the second III-
2. The method of manufacturing a compound semiconductor device according to claim 1, further comprising a temperature raising step of raising the substrate temperature while the supply of the vapor phase raw material is interrupted, between the step of depositing the group V compound semiconductor layer. Or according to claim 4, wherein each of the first to second III-V group compound semiconductor layers contains Ga, and the second III-V group compound semiconductor layer is formed. The vapor phase raw material to be included contains triethylgallium as a vapor phase raw material of Ga.
The method of manufacturing a compound semiconductor device according to claim 3, or the third semiconductor device according to claim 5.
In the step of depositing the III-V group compound semiconductor layer, the vapor phase raw material of Ga is changed from triethylgallium used as the vapor phase raw material in the deposition of the second III-V group compound semiconductor to another vapor phase raw material. 5. The method for manufacturing a compound semiconductor device according to claim 4, further comprising a switching step of switching, or the another vapor phase raw material is trimethylgallium as described in claim 6. 5. The method for manufacturing a compound semiconductor device according to claim 5, or, as described in claim 7, each of the first to third group III-V compound semiconductor layers is selected from the group consisting of Al, Ga and In. The compound according to claim 1, wherein at least one selected element is included as a group III element, and at least one element selected from the group consisting of As and P is included as a group V element. 9. The method of manufacturing a semiconductor device, or as described in claim 8, wherein the first and second III-V compound semiconductor layers have substantially the same composition. The method of manufacturing a compound semiconductor device according to claim 9 or the step of depositing the second group III-V compound semiconductor layer according to claim 9, wherein the thickness of the second group III-V compound semiconductor layer is Is 200
10. The method according to claim 1, wherein the second step is performed so as to fall within the range of 700 nm to 700 nm, or as described in claim 10.
The step of depositing the III-V group compound semiconductor layer is performed by the second step.
The method according to claim 9, wherein the III-V compound semiconductor layer is formed to have a thickness of about 500 nm, or the compound semiconductor device manufacturing method according to claim 11 is performed. The III-V compound semiconductor layer of No. 1 is A
2. The method of manufacturing a compound semiconductor device according to claim 1, wherein the first group III-V compound semiconductor layer is deposited, The surface of the Si substrate is treated with H ₂ ,
The method for manufacturing a compound semiconductor device according to claim 1, further comprising a step of removing an oxide film on the surface of the substrate.
Or the first III-V according to claim 13;
2. The method of manufacturing a compound semiconductor device according to claim 1, further comprising a step of treating the surface of the Si substrate with HF to remove an oxide film on the surface of the substrate before depositing the group compound semiconductor layer. Alternatively, as set forth in claim 14, the steps of forming the first and second III-V group compound semiconductor layers include the steps of forming the first and second III-V compound semiconductor layers, respectively.
15. The method of manufacturing a compound semiconductor device according to claim 1, wherein a molecule containing oxygen is used as a vapor phase raw material for forming the group V compound semiconductor layer, or claim 15.
2. The compound semiconductor device according to claim 1, wherein in the step of depositing the second compound semiconductor layer, one of trimethylaluminum and triethylaluminum is used as a vapor phase raw material of Al. Depending on the manufacturing method or as described in claim 16, Si
A substrate; a first III-V formed on the surface of the Si substrate and having a thickness that enables direct deposition on the surface of the Si substrate
A group III compound semiconductor layer; a second group III-V compound semiconductor layer formed on the first group III-V compound semiconductor layer; formed on the second group III-V compound semiconductor layer Third
A compound semiconductor device comprising a group III-V compound semiconductor layer; and one or more compound semiconductor layers formed on the third group III-V compound semiconductor layer and carrying active elements. 14. The compound semiconductor according to claim 13, wherein the III-V group compound semiconductor layer contains Al and has a thickness that minimizes surface roughness of the second III-V group compound semiconductor layer. By device or claim 1
19. The compound semiconductor semiconductor device according to claim 16, wherein the second III-V compound semiconductor layer has a thickness of about 500 nm, as described in claim 7, or claim 18. 18. The compound semiconductor device according to claim 17, wherein the third III-V group compound semiconductor layer has a root mean square surface roughness of 4.0 nm or less. Like the above S
17. The compound semiconductor device according to claim 16, wherein the i substrate has a specific resistance of 1000 Ω · cm or more, or as described in claim 20, further includes an insulating substrate, and the Si substrate is the 16. The compound semiconductor device according to claim 15, which is supported by the surface of an insulating substrate, or as described in claim 21, wherein the first and second compound semiconductor layers contain oxygen. The compound semiconductor device according to claim 16 or the first group III-V compound semiconductor layer is set on a Si substrate, and the substrate temperature is set to a first temperature range. And depositing; the first
Depositing a second III-V group compound semiconductor layer on the III-V group compound semiconductor layer by setting a substrate temperature in a second temperature range higher than the first temperature range; II of 2
A third III-V compound semiconductor layer is formed on the group IV compound semiconductor layer, and the substrate temperature is set to a third temperature higher than the third temperature range.
And a step of depositing by setting the temperature range of the second heteroepitaxial semiconductor substrate.
The III-V group compound semiconductor layer contains Al and is solved by a method for manufacturing a heteroepitaxial semiconductor substrate.

[0010]

According to the features of the present invention described in claims 1, 2, 16 and 22, by adding Al into the second compound semiconductor layer, the three-dimensional growth of the semiconductor layer is suppressed, and instead, The two-dimensional growth is promoted. As a result of such two-dimensional growth of the semiconductor layer, the surface roughness of the second compound semiconductor layer is suppressed, and a heteroepitaxial substrate having a flat surface can be obtained. With such a flat heteroepitaxial substrate, it is possible to maximize the performance of the compound semiconductor device formed on the substrate. Moreover, since a large-diameter Si wafer that can be manufactured at low cost can be used as the Si substrate, it becomes possible to form an integrated circuit of a high-speed compound semiconductor device or an optical semiconductor device at low cost.

According to a feature of the present invention as set forth in claim 3, the second group III-V compound semiconductor layer is grown after the first group III-V compound semiconductor layer is grown from the vapor phase raw material. By stopping the supply of the vapor phase raw material when the substrate temperature is raised, the surface roughness of the second III-V compound semiconductor layer can be suppressed. According to a feature of the present invention as set forth in claim 4, the use of triethylgallium as a vapor phase source of Ga promotes two-dimensional growth of a semiconductor layer, and the second compound is used in a temperature range of 500 to 600 ° C. It becomes possible to grow a semiconductor layer.

According to the features of the present invention described in claims 5 and 6, in growing the third compound semiconductor layer,
By using a vapor phase raw material other than triethylgallium as the vapor phase raw material of Ga, it is possible to suppress the surface roughness of the third compound semiconductor layer. According to a feature of the present invention described in claim 7, each of the first to third III-V group compound semiconductor layers contains at least one of Al, Ga and In as a group III element, It becomes possible to form a mixed crystal containing at least one of As and P as an element, and as a result, a compound semiconductor layer having an optimum band structure as a high-speed semiconductor device can be grown on such a semiconductor layer. It will be possible.

According to a feature of the present invention described in claim 8, by forming the first and second compound semiconductor layers to have substantially the same composition, the first and second compound semiconductor layers are formed. Can be formed as a substantially single epitaxial layer. Claims 9, 16 and 18
According to a feature of the described invention, said second containing Al
By setting the thickness of the compound semiconductor layer in the optimum range of 200 to 700 nm, it is possible to reduce the surface roughness of the second compound semiconductor layer to a root mean square roughness of 4 nm or less.

According to the features of the present invention as set forth in claims 10 and 17, the thickness of the second compound semiconductor layer is about 500.
By setting the thickness to nm, it is possible to minimize the surface roughness of the second compound semiconductor layer to a root mean square roughness of about 2.4 nm. According to a feature of the present invention described in claim 11, by including Al also in the first III-V compound semiconductor semiconductor layer, the two-dimensional growth of the first III-V compound semiconductor layer is performed. The surface roughness of the first III-V group compound semiconductor layer can be suppressed. As a result, the surface roughness of the first III-V group compound semiconductor layer is generated on the surfaces of the second and third III-V group compound semiconductor layers formed on the first III-V group compound semiconductor layer. It will not be transcribed.

According to the features of the present invention as set forth in claims 12 and 13, an oxide film for removing an oxide film on the surface of the substrate, which is executed prior to depositing the first III-V compound semiconductor layer. By performing the removal step in an As-free environment, unnecessary doping of the Si substrate surface can be avoided. According to the features of the present invention described in claims 14 and 21, oxygen is added when depositing the first to third compound semiconductor layers, and the oxygen forms a deep level in the compound semiconductor crystal. The deep levels pin the Fermi level in the semiconductor crystal, which results in the semiconductor crystal being semi-insulating. By supplying oxygen in the form of molecules that make up the vapor phase feed, it is possible to avoid unnecessary contamination of the deposition equipment.

According to a feature of the present invention described in claim 19,
A semi-insulating heteroepitaxial substrate having a high resistivity of 1000 Ω · cm or more can be formed. According to a feature of the present invention described in claim 20, by forming the Si substrate on yet another insulating substrate, excellent isolation between elements can be obtained for a compound semiconductor device formed on a heteroepitaxial substrate. You can

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings. First, the structure of the MOCVD apparatus used in the present invention will be described with reference to FIG. Referring to FIG. 1, the MOCVD apparatus has a horizontal reactor 20 whose pressure is reduced via an exhaust port 20a. A carbon susceptor 21 that holds a substrate 22 in the reactor 20 and heats it
However, a high frequency coil 24 that heats the susceptor 21 by high frequency excitation is provided around the reactor 20.

Trimethylaluminum (TMA) is supplied to the reactor 20 via a valve 27a as a vapor phase raw material of Al together with H ₂ carrier gas. Reactor 2
Further, arsine is supplied to the 0-mixer 26 via a valve 27g, and trimethylgallium (TMG) via a valve 27e or triethylgallium (TEG) via a valve 27c is supplied as a gas phase raw material of Ga. It Further, H ₂ is supplied to the reactor 20 as a carrier gas. Further, a controller 28 is provided to control the excitation of the valves 27a to 27g and the high frequency coil 24.

The method of manufacturing a heteroepitaxial substrate according to the first embodiment of the present invention will be described below with reference to FIG. 1 and the structure of the obtained heteroepitaxial substrate as shown in FIG.
Will be described with reference to. In this embodiment, a (100) Si substrate having a main surface inclined by 2 ° in the [011] direction is held as a substrate 22 on the susceptor 21, and a valve 27d is opened to supply H _{2 in the} reactor 20 to 10 to 10. 15SL
Introduced at a flow rate of M, typically 12 SLM. further,
The pressure inside the reactor 20 is set to 76 Torr by exhausting the reactor 20 through the exhaust port 20a, and the high frequency coil 24 is driven to move the substrate 22 on the susceptor 21 to 900 to 1100 ° C, typically 1000 °. Heat to temperature C and prebak for 10-30 minutes. As a result of such prebaking, the oxide film is removed from the surface of the substrate 22.

Next, the pressure inside the reactor 20 is adjusted to 76 Tor.
The temperature of the substrate 22 is kept at 300 to 400 ° while being maintained at r.
C, typically 350 ° C, TMA, TEG,
And arsine 2-3SCCM, 2-4SC respectively
CM and 120-160 SCCM flow rate, S
The first AlGaAs layer 22a (FIG. 2) on the i substrate 22
To a thickness of 10 to 20 nm, typically 15 nm. TMA, TEG and arsine flow rates are typically 2.5 SCCM, 3 SCCM and 140 S respectively.
Set to CCM. The resulting AlGaAs layer 22a typically have a composition represented by Al _{0. 2} Ga _0.8 As. The AlGaAs layer 22a thus formed is very thin and contains Al, so that it has a surface having good flatness. Further, the layer 22a is so thin that it may be simply formed of GaAs.

Next, the supply of the source gases of Al and Ga is interrupted, and the substrate temperature is kept at 500 to 600 ° C., typically 550 °, while the reactor internal pressure is kept at 76 Torr.
Raise to C temperature. In this state, TMA, TEG
And arsine in 0.2-0.3 SCCM,
The second AlGaAs layer 2 is supplied into the reactor 20 at a flow rate of 0.5 to 1.5 SCCM and 50 to 70 SCCM.
2b is formed to a thickness of 200 to 700 nm, typically 500 nm. See the structure in FIG. In a typical example, T
The flow rates of MA and TEG are 0.25 SCCM,
Set to 1.0 SCCM. In this case, layer 22b typically has a composition represented by Al _0.2 Ga _0.8 As.
Conventionally, in this step, the surface of the hetero-epitaxial substrate was roughened. However, as will be described later in detail, the present invention solves the problem of surface roughening by introducing Al into the layer 22b. Further, after the layer 22a is formed, the surface roughness of the layer 22b is also suppressed by stopping the supply of the source gas in the temperature raising step of raising the substrate temperature before depositing the layer 22b.

After the AlGaAs layer 22b is formed in this way, the substrate temperature is kept at 760 to 750 ° C. while maintaining the reactor internal pressure at 76 Torr, typically 70.
Raise to a temperature of 0 ° C. Further, the gas phase raw material of Ga is switched from TEG to TMG, and TMG is set to 2.0 to 3.
A flow rate of 0 SCCM, typically 2.5 SCCM, and arsine at a flow rate of 30-40 SCCM are introduced into the reactor 20, respectively, and the GaAs layer 22c is added at 0.5-0.5.
Deposit to a thickness of 1.5 μm, typically 1.0 μm. See the structure in FIG. At that time, in the structure of FIG.
In order to reduce defects on the surface of the layer 22c to a defect density of 10 ⁸ cm ^-2 or less necessary for forming a semiconductor device and at the same time prevent cracks from occurring in the heteroepitaxial substrate, the heteroepitaxial substrate including the layers 22a to 22c is included. The total thickness of the upper III-V compound semiconductor layer is 1 to 2 μm.
m, typically about 1.5 μm.

3A and 3B show the results of observing the surface of the layer 22c on the heteroepitaxial substrate formed by the above method with an atomic force microscope.
It is a figure compared with the case of the heteroepitaxial substrate of the structure which does not contain Al in b. However, FIG. 3 (A)
Is a conventional one, and FIG. 3B shows a heteroepitaxial substrate according to the present invention. In FIGS. 3 (A) and 3 (B), the bright portion indicates the convex portion and the dark portion indicates the concave portion. FIG.
As can be seen by comparing (A) and (B), in the present invention,
The area of bright areas is substantially reduced, indicating that the surface roughness of layer 22c is substantially reduced. In the illustrated example, in the case of the conventional example of FIG. 3 (A), 50 μm × 50
It was confirmed that the root mean square surface roughness in the μm region was 3.0 nm, whereas it was reduced to 2.4 nm in the present invention.

FIG. 4 shows the structure of FIG. 2 in which the thickness of the layer 22b is changed while keeping the sum of the thickness of the layer 22b and the thickness of the layer 22c at 1.5 μm, and the root mean square surface roughness of the layer 22c is changed. The results are shown measured as a function of the thickness of layer 22b.
However, although the result of FIG. 4 is the case where the layer 22b does not contain Al, the tendency shown in FIG. 4 is effective also in the case of the present invention in which Al is contained in the layer 22b.

Referring to FIG. 4, the root mean square surface roughness of layer 22c decreases as the thickness of layer 22b increases and reaches a minimum when layer 22b has a thickness of about 500 nm. As the thickness of layer 22b increases further, the root mean square roughness of layer 22c increases again. In the example of FIG. 4, the layer 22b is made of Al.
Therefore, the minimum value of the root mean square surface roughness of the layer 22c is about 3 nm. However, in the present invention, as described above, by introducing Al into the layer 22b, the root mean square roughness can be reduced. The minimum value of the height is reduced to 2.4 nm.

FIG. 5 is a diagram showing the effect of the pre-baking step carried out in the present invention on the sheet resistance of the heteroepitaxial substrate. However, black circles correspond to prebaking performed in an arsine atmosphere as in the conventional case, and white circles correspond to prebaking performed in an H ₂ atmosphere. Referring to FIG. 5, experimental results shown as a conventional example show that the first and second III-V group compound semiconductor layers 22a,
22b corresponds to the case where both are grown without introducing Al, so that both layers 22a and 22b are composed of GaAs. In the illustrated example, the layer 22a is
The Si substrate 22 is prebaked at a temperature of 1000 ° C. and then deposited at a temperature of 400 ° C. and the layer 22b is deposited on the layer 22a at a temperature of 650 ° C. Also, the layer 22c is 70
It is deposited at a temperature of 0 ° C. A for layers 22a and 22b
When pure GaAs not containing 1 is used, the sheet resistance on the surface of the Si substrate 22 should exceed 1 kΩ / □ regardless of whether prebaking is performed in an arsine atmosphere or H ₂ atmosphere. There is no.

On the other hand, the result shown as the invention (1) in FIG. 5 shows the case of the heteroepitaxial substrate of the embodiment of the invention described above, and the layers 22a and 22b both contain Al. There is. In this case, the sheet resistance is 1 kΩ / □ as long as prebaking is performed in an arsine atmosphere.
However, it can be seen that a high sheet resistance of 3 to 4 kΩ / □ can be realized by performing the pre-baking in an H ₂ atmosphere.

Further, the result shown as the invention (2) in FIG. 5 corresponds to the second embodiment of the invention,
The results are shown for the case where oxygen is introduced into the layers 22a and 22b. Oxygen doping of the III-V group compound semiconductor layer can be performed by introducing an organic metal containing oxygen into the molecule when depositing the layers 22a and 22b, or by ion implantation of oxygen. In this example, the layers 22a and 22b had a thickness of 15 nm and 0.5 μm, respectively, and were oxygen-doped with tertiary butyl arsine (TBAs) containing oxygen. The layer 22c is formed to have a thickness of 1.0 μm. As can be seen in FIG. 5, layers 22a and 2
By introducing oxygen into 2b, no improvement is observed when prebaking is performed in an arsine atmosphere, but when prebaking is performed in an H ₂ atmosphere, it is better than in the first embodiment of the present invention. It can be seen that even higher sheet resistance can be obtained.

To summarize the results of FIG. 5, the Si substrate 22 was prebaked in an H ₂ atmosphere to produce Si
Mutual doping of the substrate or the III-V group layer on the substrate is avoided, and a sheet resistance of the heteroepitaxial substrate exceeding 1000 Ω / □, which has been difficult in the past, can be obtained. In addition, the same result shows that the surface of the Si substrate 22 is
It can also be obtained by treating with F.

In the embodiments described above, the compound semiconductor layers 22a and 22b are not limited to AlGaAs, but may be AlGaP, AlGaAsP, InGaA.
It may be a mixed crystal of any composition of In-Ga-Al-As-P system such as 1P, InGaAlAs or InGaAlAsP. In addition, along with this, the compound semiconductor layer 22
In addition to GaAs, c is InAs, InP, GaP,
It may be an In-Ga-Al-As-P-based mixed crystal such as AlAs or AlP.

Further, the compound semiconductor layers 22a, 22
b and 22c as a raw material of group V element Upon depositing, not arsine only, it is also possible to use phosphine (PH ₃₎ or an organic arsenic or organic phosphorus. Such organic arsenic includes tertiary butyl arsine (tBA
s), trimethyl arsenic (TMAs), triethyl arsenic (TEAs), diethyl arsenic hydride (DEA)
s), ethylarsine (EAs) and the like. Also,
Tertiary butyl phosphine (tB
P), trimethyl phosphorus (TMP), triethyl phosphorus (T
EP) and diethyl phosphorus hydride (DEP).

FIG. 6 shows a structural example of a HEMT integrated circuit formed on the heteroepitaxial substrate of the present invention. Figure 6
, D-type H connected in series with each other.
The Si substrate 2 is composed of an EMT and an E-type HEMT.
No. 2 Si substrate 31 and AlGaAs corresponding to the AlGaAs layer 22a formed on the substrate 31
The layer 31a and the AlGaA formed on the layer 31a
The AlGaAs layer 31b corresponding to the s layer 22b, and the layer 31
G corresponding to the GaAs layer 22c formed on b
It is formed on a heteroepitaxial substrate composed of the aAs layer 31c.

On the heteroepitaxial substrate, the undoped GaAs layer 32 is used as a buffer layer for the GaAs.
It is epitaxially grown to a thickness of 50 μm in contact with the layer 31c, and undoped AlGaAs is formed on the buffer layer 32.
The layer 33 is epitaxially grown as an element isolation layer to a thickness of 300 nm. Further, an undoped GaAs layer 34 is epitaxially grown as an active layer to a thickness of 100 nm on the element isolation layer 33, and an electron supply layer 35 made of n-type AlGaAs is formed to a thickness of 50 nm on the active layer 34. To be done. As a result, in the active layer 34, the active layer 3
The two-dimensional electron gas 34a is formed along the heterojunction surface between the No. 4 and the electron supply layer 35.

A first contact layer 36 made of n-type GaAs is epitaxially grown to a thickness of 5 nm on the electron supply layer 35, and a second contact layer 37 made of n-type AlGaAs is further formed on the contact layer 36. Is 5 nm
Epitaxially grown to a thickness of. A cap layer 38 made of n-type GaAs is formed on the contact layer 37. Further, in the layers 36 to 38, a portion corresponding to the gate region of the D-type HEMT is removed by selective etching stopped on the surface of the layer 35, and a Schottky electrode made of Al or the like is formed as a gate electrode of the D-type HEMT. It
Further, the layer 38 has a portion corresponding to the gate region of the E-type HEMT removed by selective etching stopped on the surface of the layer 37 thereunder, and the Schottky electrode 10 made of Al or the like.
Is formed as a gate electrode of the E-type HEMT. Ohmic electrodes 11, 12 and 13 are formed on the cap layer 38 on both sides of the electrodes 9 and 10. Among them, the ohmic electrode 11 acts as a source electrode of the D-type HEMT, the ohmic electrode 13 acts as a drain electrode of the E-type HEMT, and the ohmic electrode 12 acts as the D-type HEM.
It acts as a drain electrode of T and at the same time acts as a source electrode of EHEMT.

Since the HEMT shown in FIG. 6 is formed on a heteroepitaxial substrate having a flat surface, the unevenness of the heterojunction interface between the active layer 34 and the electron supply layer 35 is substantially reduced, Therefore, the increase of scattering of electrons in the two-dimensional electron gas is suppressed. As a result, the HEMT, even when formed on a heteroepitaxial substrate, exhibits performance comparable to that formed on a substrate made of a compound semiconductor bulk crystal.

FIG. 7 is a modification of the HEMT shown in FIG. 6, in which a Si substrate 31 forming a heteroepitaxial substrate is formed on an insulating support substrate 30 made of an insulator. With this structure, it is possible to form a compound semiconductor integrated circuit having a so-called SOI structure.
By using the heteroepitaxial substrate according to the present invention in combination with the SOI structure, it is possible to manufacture a high-density compound semiconductor integrated circuit having excellent element isolation characteristics at a low cost.

[0037]

According to the features of the present invention described in claims 1, 2, 16 and 22, by adding Al to the second compound semiconductor layer, three-dimensional growth of the semiconductor layer is suppressed. Instead, two-dimensional growth is promoted. As a result of such two-dimensional growth of the semiconductor layer, the surface roughness of the second compound semiconductor layer is suppressed, and a heteroepitaxial substrate having a flat surface can be obtained. With such a flat heteroepitaxial substrate, it is possible to maximize the performance of the compound semiconductor device formed on the substrate. Moreover, since a large-diameter Si wafer that can be manufactured at low cost can be used as the Si substrate, it becomes possible to form an integrated circuit of a high-speed compound semiconductor device or an optical semiconductor device at low cost.

According to the feature of the present invention described in claim 3, the second III-V group compound semiconductor layer is grown after the first III-V group compound semiconductor layer is grown from the vapor phase raw material. By stopping the supply of the vapor phase raw material when the substrate temperature is raised, the surface roughness of the second III-V compound semiconductor layer can be suppressed. According to a feature of the present invention as set forth in claim 4, the use of triethylgallium as a vapor phase source of Ga promotes two-dimensional growth of a semiconductor layer, and the second compound is used in a temperature range of 500 to 600 ° C. It becomes possible to grow a semiconductor layer.

According to the features of the present invention described in claims 5 and 6, in growing the third compound semiconductor layer,
By using a vapor phase raw material other than triethylgallium as the vapor phase raw material of Ga, it is possible to suppress the surface roughness of the third compound semiconductor layer. According to a feature of the present invention described in claim 7, each of the first to third III-V group compound semiconductor layers contains at least one of Al, Ga and In as a group III element, It becomes possible to form a mixed crystal containing at least one of As and P as an element, and as a result, a compound semiconductor layer having an optimum band structure as a high-speed semiconductor device can be grown on such a semiconductor layer. It will be possible.

According to a feature of the present invention described in claim 8, by forming the first and second compound semiconductor layers to have substantially the same composition, the first and second compound semiconductor layers are formed. Can be formed as a substantially single epitaxial layer. Claims 9, 16 and 18
According to a feature of the described invention, said second containing Al
By setting the thickness of the compound semiconductor layer in the range of 200 to 700 nm, it is possible to reduce the surface roughness of the second compound semiconductor layer to a root mean square roughness of 4 nm or less.

According to the features of the present invention as set forth in claims 10 and 17, the thickness of the second compound semiconductor layer is about 500.
By setting the thickness to nm, it is possible to minimize the surface roughness of the second compound semiconductor layer to a root mean square roughness of about 2.4 nm. According to a feature of the present invention described in claim 11, by including Al also in the first III-V compound semiconductor semiconductor layer, the two-dimensional growth of the first III-V compound semiconductor layer is performed. The surface roughness of the first III-V group compound semiconductor layer can be suppressed. As a result, the surface roughness of the first III-V group compound semiconductor layer is generated on the surfaces of the second and third III-V group compound semiconductor layers formed on the first III-V group compound semiconductor layer. It will not be transcribed.

According to the features of the present invention as set forth in claims 12 and 13, an oxide film for removing an oxide film on the surface of the substrate, which is executed prior to depositing the first group III-V compound semiconductor layer. By performing the removal step in an As-free environment, unnecessary doping of the Si substrate surface can be avoided. According to the features of the present invention described in claims 14 and 21, oxygen is added when depositing the first to third compound semiconductor layers, and the oxygen forms a deep level in the compound semiconductor crystal. The deep levels pin the Fermi level in the semiconductor crystal, which results in the semiconductor crystal being semi-insulating. By supplying oxygen in the form of molecules that make up the vapor phase feed, it is possible to avoid unnecessary contamination of the deposition equipment.

According to a feature of the present invention described in claim 19,
It is possible to form a semi-insulating heteroepitaxial substrate having a high resistivity of 1000 Ω · cm or more. According to a feature of the present invention described in claim 20, by forming the Si substrate on yet another insulating substrate, excellent isolation between elements can be obtained for a compound semiconductor device formed on a heteroepitaxial substrate. You can

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an MOCVD apparatus used in the present invention.

FIG. 2 is a diagram showing a configuration of a heteroepitaxial substrate according to first and second embodiments of the present invention.

3 (A) and 3 (B) show the results of observing the surface of the heteroepitaxial substrate manufactured by the conventional method and the surface of the heteroepitaxial substrate according to the first embodiment of the present invention with an atomic force microscope, respectively. FIG.

FIG. 4 is a diagram showing the relationship between the surface roughness of a heteroepitaxial substrate and the thickness of a semiconductor layer forming the substrate.

FIG. 5 is a diagram showing the sheet resistance values of the heteroepitaxial substrates according to the first and second embodiments of the present invention in comparison with the conventional heteroepitaxial substrate.

FIG. 6 is a diagram showing the structure of a HEMT formed on a heteroepitaxial substrate according to the third embodiment of the present invention.

7 is a diagram showing a modification of the HEMT of FIG.

[Explanation of symbols]

 9, 10 Gate electrode 11-13 Ohmic electrode 20 Reactor 21 Susceptor 22, 31 Si substrate 22a, 31a AlGaAs layer 22b, 31b AlGaAs layer 22c, 31c GaAs layer 24 High frequency coil 27a-27h Valve 28 Controller 32 GaAs buffer layer 33 AlGaAs element Separation layer 34 Active layer 34a Two-dimensional electron gas 35 Electron supply layer 36, 37 Contact layer 38 Cap layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location H01L 21/338 29/812 27/095 (72) Inventor Satoshi Okubo Satoshi Ueda, Nakahara-ku, Kawasaki-shi, Kanagawa Address: 1015, within Fujitsu Limited (72) Inventor, Kazuaki Takai Address: 1015, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Within Fujitsu Limited

Claims (22)

[Claims] 1. A step of depositing a first III-V group compound semiconductor layer on a Si substrate while setting a substrate temperature to a first temperature; and on the first III-V group compound semiconductor layer. To the second
Depositing a III-V group compound semiconductor layer by setting a substrate temperature to a second temperature higher than the first temperature; and depositing a third III-V compound semiconductor layer on the second III-V group compound semiconductor layer. And a step of depositing a III-V group compound semiconductor layer by setting a substrate temperature to a third temperature higher than the second temperature, wherein the second group III-V group semiconductor is manufactured. The compound semiconductor layer contains Al, The manufacturing method of a compound semiconductor device characterized by the above-mentioned. 2. The first temperature is in the range of 300 to 400 ° C., the second temperature is in the range of 500 to 600 ° C., and the third temperature is in the range of 650 to 750 ° C. 2. The method for manufacturing a compound semiconductor device according to claim 1, wherein: 3. The supply of the vapor phase raw material is interrupted between the step of depositing the first III-V group compound semiconductor layer and the step of depositing the second III-V group compound semiconductor layer. 2. The method for manufacturing a compound semiconductor device according to claim 1, further comprising a temperature raising step of raising the substrate temperature in the state. 4. Each of the first to second III-V group compound semiconductor layers contains Ga, and the second III-V compound semiconductor layer comprises:
The method for producing a compound semiconductor device according to claim 1, wherein the vapor-phase raw material forming the group V compound semiconductor layer contains triethylgallium as a vapor-phase raw material of Ga. 5. The step of depositing the third III-V group compound semiconductor layer, wherein the vapor phase raw material of Ga is used as a vapor phase raw material in the deposition of the second III-V group compound semiconductor. 5. The method of manufacturing a compound semiconductor device according to claim 4, further comprising a switching step of switching to another vapor phase raw material. 6. The method of manufacturing a compound semiconductor device according to claim 5, wherein the another vapor phase raw material is made of trimethylgallium. 7. Each of the first to third III-V group compound semiconductor layers contains at least one element selected from the group consisting of Al, Ga and In as a group III element, and As. 2. The method of manufacturing a compound semiconductor device according to claim 1, further comprising at least one element selected from the group consisting of P and P as a group V element. 8. The method of manufacturing a compound semiconductor device according to claim 7, wherein the first and second III-V compound semiconductor layers have substantially the same composition. 9. The step of depositing the second group III-V compound semiconductor layer is performed such that the thickness of the second group III-V compound semiconductor layer falls within a range of 200 to 700 nm. The method for manufacturing a compound semiconductor device according to claim 1, wherein 10. The step of depositing the second III-V compound semiconductor layer is performed such that the thickness of the second III-V compound semiconductor layer is about 500 nm. 9. The method for manufacturing a compound semiconductor device according to claim 8. 11. The method for manufacturing a compound semiconductor device according to claim 1, wherein the first III-V group compound semiconductor layer contains Al. 12. A step of treating the surface of the Si substrate with H ₂ to remove an oxide film on the surface of the substrate prior to depositing the first group III-V compound semiconductor layer. The method for manufacturing the compound semiconductor device according to claim 1. 13. A step of treating the surface of the Si substrate with HF to remove an oxide film on the surface of the substrate prior to depositing the first group III-V compound semiconductor layer. Item 2. A method for manufacturing a compound semiconductor device according to item 1. 14. In the step of forming the first and second III-V group compound semiconductor layers, oxygen is used as a gas phase raw material for forming the first and second III-V group compound semiconductor layers, respectively. 2. The method of manufacturing a compound semiconductor device according to claim 1, wherein the contained molecule is used. 15. The compound semiconductor device manufacturing method according to claim 1, wherein in the step of depositing the second compound semiconductor layer, one of trimethylaluminum and triethylaluminum is used as a vapor phase raw material of Al. Method. 16. A Si substrate; a first group III-V compound semiconductor layer formed on the surface of the Si substrate and having a thickness that enables direct deposition on the surface of the Si substrate; of
A second III-V group compound semiconductor layer formed on the III-V group compound semiconductor layer; and a third III-V group compound semiconductor layer formed on the second III-V group compound semiconductor layer A compound semiconductor device comprising one or more compound semiconductor layers formed on the third III-V compound semiconductor layer and carrying an active element, wherein the second III-V compound semiconductor layer Contains Al,
14. The compound semiconductor device according to claim 13, wherein the compound semiconductor device has a thickness that minimizes surface roughness of the second III-V compound semiconductor layer. 17. The compound semiconductor semiconductor device according to claim 16, wherein the second III-V compound semiconductor layer has a thickness of about 500 nm. 18. The compound semiconductor device according to claim 16, wherein the third group III-V compound semiconductor layer has a root mean square surface roughness of 4.0 nm or less. 19. The compound semiconductor device according to claim 16, wherein the Si substrate has a specific resistance of 1000 Ω · cm or more. 20. The compound semiconductor device according to claim 16, further comprising an insulating substrate, wherein the Si substrate is supported by the surface of the insulating substrate. 21. The compound semiconductor device according to claim 16, wherein the first and second compound semiconductor layers contain oxygen. 22. A step of depositing a first III-V group compound semiconductor layer on a Si substrate while setting a substrate temperature in a first temperature range; and the first III-V group compound semiconductor layer. above,
The second III-V compound semiconductor layer is formed at the substrate temperature of the first
Depositing in a second temperature range higher than the temperature range; and a third III-V compound semiconductor layer on the second III-V compound semiconductor layer, and a substrate temperature of the third III-V compound semiconductor layer. A method of manufacturing a heteroepitaxial semiconductor substrate, comprising: setting a temperature within a third temperature range higher than a third temperature range and depositing the third temperature range, wherein the second III-V compound semiconductor layer contains Al. A method for manufacturing a heteroepitaxial semiconductor substrate, comprising: