JPH08166428A - Test circuit - Google Patents

Abstract

PURPOSE: To test an arbitrary one of a plurality of propagation paths other than a preset one. CONSTITUTION: The test circuit comprises a combination circuit 30 to be tested, scan FFs 20-1,..., 20-3 for inputting a data and a scan signal to the combination circuit 30, scan FFs 20-4,..., 20-5 for outputting a data and a scan signal from the combination circuit 30, and a circuit 40 for generating clock to the the scan FFs 20-4,..., 20-5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit, and more particularly to a test circuit for a digital semiconductor integrated circuit which operates at high speed.

[0002]

2. Description of the Related Art As a conventional AC characteristic test circuit in a semiconductor integrated circuit, there is a method using a ring oscillator. FIG. 5 is a diagram showing an AC characteristic test circuit using a conventional ring oscillator.

In the method using a ring oscillator as shown in FIG. 5, a ring oscillator in which an odd number of inverters are connected in a ring shape is built in a semiconductor integrated circuit, and the desired oscillation frequency is measured. They were testing whether the characteristics were built in.

FIG. 6 is a diagram showing another example of an AC characteristic test circuit in a conventional semiconductor integrated circuit. Figure 6
The circuit shown in (1) is disclosed in JP-A-63-73170.

In the conventional example shown in FIG. 6, a shift register 301-i is provided outside a combinational circuit 330 to be tested.
(I = 1, 2, ..., N) and an input scan flip-flop (hereinafter referred to as “input scan FF”) having normal data input, scan input, data holding and inverting functions.
302-i (i = 1, 2, ..., N) and an output scan flip-flop (holding and outputting an output signal corresponding to the input signal from the input scan FF 302-i to the combinational circuit 330). Below "output scan FF"
304-i (i = 1, 2, ..., N) and a specific propagation path 300-i (i =) in the combinational circuit 330.
1, 2 ,. ． ． , N) corresponding to each of the input scan FF 302 and the input scan FF 302.
-1/2 the frequency of the clock signal 306 supplied to
A clock control circuit 305 is provided to reduce the frequency.

Below, the combination circuit 3 having the above-mentioned configuration is used.
A procedure for testing the AC characteristic of the propagation path 300-1 among the propagation paths in 30 will be described.

First, the control mode of the input scan FF 302-i is set to the scan control mode, and the propagation path 300-1
And a signal for activating a path required for the test is input as an input signal to the input scan FF 302-i provided on the input side of the path to be activated.

Next, the control mode of the input scan FF 302-i is set to the inversion control mode, and the shift register 301-
A value for inverting the input value of only the input scan FF 302-1 is input to 1. As a result, the inversion control signal from the shift register 301-1 becomes the logical value "1", and the value of the input scan FF 302-1 is inverted. As a result, the output value obtained by inverting the value of only the input scan FF 302-1 is captured by the output scan FF 304-i as the output of the combinational circuit 330.

Here, the clock signal 307 input to the output scan FF 304-1 has a known propagation path 300-1 with respect to the clock signal 306 input to the input scan FF 302-1 by a clock delay circuit (not shown). By being input with a delay of the minimum value of the propagation delay time of, the scan signal propagated in the combinational circuit 330 is output from the output scan FF 304-1 with a delay of the minimum value of the propagation delay time after being input, Propagation path 3
The AC characteristics of 0-1 are tested.

FIG. 7 is a diagram showing another example of the AC characteristic test circuit in the conventional semiconductor integrated circuit. Figure 7
The circuit shown in (1) is disclosed in JP-A-63-175780.

In the conventional example shown in FIG. 7, the value is inverted by replacing the shift register 301-i with a counter 313 and a decoder 318 in comparison with the conventional example shown in FIG. 6 and counting up the input clock. The input scan FF to be changed is sequentially changed.

[0012]

However, in the above-mentioned conventional test circuit, the propagation path to be tested in the combinational circuit is determined in advance, and the input scan FF and the output scan corresponding to each of the propagation paths. Since only the FFs are provided and the propagation delay times corresponding to them are set, it is not possible to test the propagation paths other than the predetermined propagation paths. Therefore, there is a problem in that it is not possible to determine by a test a defect in a place other than a specific propagation path, for example, a defect that occurs accidentally such as a defect of a contact or a through hole.

The present invention has been made in view of the problems of the above-mentioned conventional technique, and it is possible to perform a test on an arbitrary propagation path other than a preset propagation path among a plurality of propagation paths. It is an object of the present invention to provide a test circuit capable of

[0014]

In order to achieve the above object, the present invention provides a test circuit for performing an AC characteristic test by supplying test data to an internal combinational circuit by using a scan path. On the side,
It is provided with a plurality of input scan flip-flops for inputting normal data, scan input, holding and inverting data, and outputting normal data, scanning output, holding and inverting data on the output side of the combinational circuit,
A plurality of output scan flip-flops that can be combined with each of the plurality of input scan flip-flops are provided, and a delay time of a corresponding propagation path is set by a combination of the input flip-flops and the output flip-flops. A clock generating circuit for inputting a clock signal to the output flip-flop is provided.

Further, each of the plurality of input flip-flops and the plurality of output flip-flops is connected to the first and second latch circuits to which different clock signals are input and the output stage of the second latch circuit. And a third latch circuit for controlling the selection circuit.

Further, the clock generation circuit is provided with a delay adjustment buffer circuit, whereby the delay time of the propagation path corresponding to the combination of the input flip-flop and the output flip-flop is arbitrarily set. To do.

[0017]

According to the present invention configured as described above, when the propagation path is tested, the combination of the scan flip-flop provided on the input side and the scan flip-flop provided on the output side of the combinational circuit is arbitrarily set. Moreover, since the delay time of the propagation path corresponding to the set combination can be adjusted, the propagation path is not limited to a specific propagation path, and the propagation path can be freely selected for the test.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the test circuit of the present invention.

As shown in FIG. 1, the test circuit in this embodiment has a combinational circuit 30 to be tested and scan FFs 20-1 to 20-2 which are input scan FFs for inputting data and scan signals to the combinational circuit 30.
0-3, scan FFs 20-4 to 20-5 that are output scan FFs that output data and scan signals to the combinational circuit 30, and each scan FF 20-1.
20 to 5-5 and a clock generating circuit 40 for generating a clock.

Each connection will be described below.

Regarding the propagation path of the scan signal, the scan input terminal of the scan FF 20-1 is connected to the scan signal input terminal 1 to which the scan signal for the test circuit is input, and the scan FF 20-i (i = 1, 2, 1) at the preceding stage is connected. ，
3, 4, 5) are sequentially connected to the scan input terminal of the next-stage scan FF 20- (i + 1), and the scan output terminal of the scan FF 20-5 is connected to the scan signal output terminal 2 of the test circuit. ing.

Regarding the data propagation path, the scan FFs 20-1 and 20-2 provided on the input side of the combinational circuit 30.
The data signal input terminals 0-3 are connected to the data signal input terminals 3-1 to 3-3 of the test circuit, respectively, and the scan F
The data signal output terminals of F20-1 to 20-3 are connected to the data signal input terminals of the combination circuit 30, and the data signal output terminals of the combination circuit 30 are scan FFs 20-4 to.
Connected to the data signal input terminal of 20-5, scan F
The data signal output terminals of F20-4 to 20-5 are connected to the data signal output terminals 4-1 to 4-2 of the test circuit, respectively.

Further, the scan mode control terminals of the scan flip-flops 20-1 to 20-5 are connected to the scan mode control terminals 7 to which a control signal for switching the test or the normal operation of the combinational circuit is inputted.

Regarding the clock generation circuit 40,
The phase adjustment terminals are connected to the clock phase adjustment terminals 8-1 to 8-2 to which the adjustment signals of the clock phase difference are input, and the clock input terminals are connected to the clock input signal terminal 9 to which the clock signal is input, The test mode input terminal is connected to the test mode switching terminal 10, and the clock 1
Output terminal is clock monitor terminal 11 and scan FF
It is connected to the clock 1 input terminal of 20-1 to 20-5,
The clock 2 output terminal is connected to the clock monitor terminal 12 and the clock 2 input terminals of the scan FFs 20-1 to 20-5. FIG. 2 is a circuit diagram of the scan FF in the test circuit shown in FIG.

Scan FFs 20-1 to 20-1 in this embodiment
Each of 20-5 (see FIG. 1) includes a 2-input 1-output selection circuit 110 that selects the normal mode or the test mode, a latch circuit 108 that is a first latch circuit, and a second circuit as shown in FIG. Circuit 109 which is the latch circuit of
And a latch circuit 112 which is a third latch circuit and a 1-input 2-output selection circuit 111.

Each connection will be described below.

In the latch circuit 112, the scan mode switching terminal 7 is connected to the input terminal, the clock monitor terminal 12 is connected to the clock terminal, and the control input terminal of the 2-input 1-output selecting circuit 110 is connected to the output terminal. The control terminal of the 1-input 2-output selection circuit 111 is connected.

Regarding the 2-input 1-output selection circuit 110,
The data signal input terminal 3 is connected to the first input terminal,
The scan signal input terminal 1 is connected to the second input terminal, and the input terminal of the latch circuit 108 is connected to the output terminal.

In the latch circuit 108, the clock monitor terminal 11 is connected to the clock terminal, and the input terminal of the latch circuit 109 is connected to the output terminal.

In the latch circuit 109, the clock terminal is connected to the clock terminal, and the output terminal is connected to the input terminal of the 1-input / 2-output selection circuit 111. Regarding the 1-input 2-output selection circuit 111,
The data signal output terminal 4 is connected to the output terminal of the
The scan signal output terminal 2 is connected to the output terminal of the.

FIG. 3 is a circuit diagram of the clock generation circuit in the test circuit shown in FIG.

The clock generation circuit 40 in this embodiment
(See FIG. 1) is a buffer circuit 208 as shown in FIG.
And an inverter circuit 210 and a 2-input 1-output selection circuit 2
09, a delay adjustment buffer circuit 206, and a 4-input 1-output selection circuit 207.

Each connection will be described below.

In the buffer circuit 208, the clock signal input terminal 9 is connected to the input terminal and the clock monitor terminal 11 is connected to the output terminal.

The clock signal input terminal 9 is connected to the input terminal of the inverter circuit 210, and the first input terminal of the 2-input 1-output selection circuit 209 is connected to the output terminal.

Regarding the 2-input 1-output selection circuit 209,
The output terminal of the 4-input 1-output selection circuit 207 is connected to the second input terminal, and the test mode switching terminal 1 is connected to the control terminal.
0 is connected.

In the delay adjusting buffer circuit 206, the clock signal input terminal 9 is connected to the input terminal,
The input terminals of the 4-input / 1-output selection circuit 207 are connected to the output terminals.

Regarding the 4-input 1-output selection circuit 207,
The clock phase adjustment terminal 8-1 is connected to the first clock terminal, and the clock phase adjustment terminal 8-2 is connected to the second clock terminal.

Next, the clock generation circuit 40 (see FIG. 1)
The clock generation operation by the will be described.

FIG. 4 is a waveform diagram of a clock generated by the clock generation circuit shown in FIG. 3, where (a) is a waveform diagram when no delay is generated and (b) is a waveform when delay is generated. It is a figure.

When the input value to the test mode switching terminal 10 (see FIG. 3) is the logical value "0", the normal operation state occurs, and as shown in FIG. 4 (a), the clock monitor which is the first output terminal. The same signal as the input signal is output to the terminal 11 (see FIG. 3), and an inverted signal of the input signal is output to the clock monitor terminal 12 (see FIG. 3) which is the second output terminal.

When the input value to the test mode switching terminal 10 (see FIG. 3) is the logical value "1", as shown in FIG. 4B, the clock monitor terminal 11 (FIG. 3) which is the first output terminal. The same signal as the input signal is selected by the clock phase adjusting terminals 8-1 to 8-2 (see FIG. 3) at the clock monitor terminal 12 (see FIG. 3) which is the second output terminal. A signal delayed by the input delay amount as compared with the input signal is output. The operation of the test circuit in this embodiment will be described below. First, the flow of the test in this embodiment will be described.

Scan mode: Write a value such that the measured path can be measured in all FFs. At this time, the clock generation circuit 40 is set to the test mode so that the frequency of the input clock is made sufficiently slow and the delay value is made sufficiently large to prevent malfunction.

Normal mode: The written value is read from all the FFs, and the combinational circuit 30 is set so that the measured path can be tested. The conditions of the clock generation circuit 40 are the same as.

Scan mode: The scan mode is set again, and only the input to the measured path is inverted. The conditions of the clock generation circuit 40 are the same as.

Normal mode: The written value is read from all FFs. At this time, the clock generation circuit 40 is set to the test mode, and the frequency of the input clock is made sufficiently slow. However, the delay value is set to be the specified time of the measured path.

Scan mode: The FF is set to the scan mode, the read value is shifted, and the result is read from the FF to determine pass / fail. At this time, the conditions of the clock generation circuit 40 are the same as.

The detailed operation will be described below.

To perform normal operation in FIG. 1, the input value of the scan mode switching terminal 7 is set to the logical value "
1 ", the input value of the test mode switching terminal 10 is a logical value"
0 ". Then, the scan FFs 20-1 to 20-3
Is input from the data input signal terminals 3-1 to 3-3, and from the clock monitor terminal 11 which is the output of the clock generation circuit 40, the clock having the same phase as the clock signal input to the clock signal input terminal 9 is input. A signal is output from the clock monitor terminal 12 as a clock signal having a phase opposite to that of the clock signal input to the clock signal input terminal 9, and all the FFs operate as normal delayed flip-flops, and the circuit as a whole operates normally. Is performed.

Next, a procedure and an operation for carrying out the test will be described.

Here, a test is performed on the propagation path from the scan FF 20-2 to the scan 20-4.

As a first step, the input value of the scan mode switching terminal 7 is set to the logical value "0", and the input value of the test mode switching terminal 10 is set to the logical value "1". Then, the scan FF 20-1 which is the input side FF of the combinational circuit 30.
The input from the scan signal input terminals 1 to 20-3 is input from the scan signal input terminal 1, and the clock signal in phase with the clock signal input to the clock signal input terminal 9 is output from the clock monitor terminal 11 which is the output of the clock generation circuit 40. From the clock monitor terminal 12, clock phase adjustment terminals 8-1 to
A clock signal having a delay amount determined by the signal input to 8-2 is output. At this time, by setting the phase difference between the outputs of the clock monitor terminal 11 and the clock monitor terminal 12 at a low speed from the clock signal input terminal 9 so that the hold time error due to the skew of the clock does not occur during the shift operation, stable operation is achieved. The shift operation will be performed. In this state, a scan signal is input from the scan signal input terminal 1 and each scan FF
The values input to 20-1 to 20-5 are read while shifting.

As the second step, the input value of the scan mode switching terminal 7 is set to the logical value "0". Then, the scan signal is set to be output from the data signal output terminal 4 (see FIG. 2) by the operation of the 1-input / 2-output selection circuit 111 (see FIG. 2). In the third step, the input value of the scan mode switching terminal 7 is set to the logical value “0” again, the input value of the scan FF 20-2 is the value inverted with respect to the value input in the first step, and A value such that the input value of the scan FF other than the scan FF 20-2 becomes the same value as the value input in the first step is input from the scan signal input terminal 1 and is shifted by each scan FF. Each scan FF is written.

As the fourth step, the input value of the scan mode switching terminal 7 is set to the logical value "1" again. further,
The clock phase difference between the clock monitor terminal 11 and the clock monitor terminal 12 changes from the scan FF 20-2 to the scan 20.
-4 is set to a delay time corresponding to the maximum operating frequency of the propagation path, and one clock is input to the combinational circuit 3
The signal is propagated in 0. If the signal is propagated within the delay time, the correct value will be captured by the scan FF 20-4, and if it is not propagated within the time, an incorrect value will be captured.

As a fifth step, the input value of the scan mode switching terminal 7 is set to the logical value "0" again, and when the scan FFs 20-1 to 20-5 are shifted, an output signal is output from the scan signal output terminal 2. To be done.

By comparing the output signal with the expected value with the tester, it is determined whether or not the propagation path tested has failed.

By repeating the above-mentioned 5 steps, it is possible to arbitrarily set a propagation path to be tested and test the propagation path at an actual operating speed.

[0059]

Since the present invention is configured as described above, it has the following effects.

According to the first aspect of the present invention, normal data input, scan input, and
Equipped with a plurality of input scan flip-flops for holding and inverting data, the output side of the combinational circuit,
Equipped with multiple output scan flip-flops that perform normal data output, scan output, data retention and inversion, and can be combined with each input scan flip-flop. Since the configuration has a clock generation circuit that sets the delay time of the propagation path and inputs the clock signal, the propagation path can be selected from multiple paths other than the preset propagation path for testing. Can be done. Thereby, it is possible to discriminate defects in places other than the specific propagation path, for example, accidental defects such as defects of contacts and through holes, in the test.

According to another aspect of the present invention, each of the plurality of input flip-flops and the plurality of output flip-flops has a first and a second latch circuit to which clock signals of different timings are input, and a second latch circuit. Since the configuration includes the selection circuit connected to the output stage of the latch circuit and the third latch circuit for controlling the selection circuit, the same effect as that of the first aspect is achieved.

According to the third aspect of the present invention, the clock generation circuit includes the delay adjustment buffer circuit, whereby the delay time of the propagation path corresponding to the combination of the input flip-flop and the output flip-flop is arbitrarily set. Therefore, the same effect as that described in claim 1 is achieved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a test circuit of the present invention.

FIG. 2 is a circuit diagram of a scan FF in the test circuit shown in FIG.

FIG. 3 is a circuit diagram of a clock generation circuit in the test circuit shown in FIG.

4 is a waveform diagram of a clock generated by the clock generation circuit shown in FIG. 3, (a) is a waveform diagram when no delay is generated, and (b) is a waveform diagram when a delay is generated. .

FIG. 5 is a diagram showing an AC characteristic test circuit using a conventional ring oscillator.

FIG. 6 is a diagram showing another example of an AC characteristic test circuit in a conventional semiconductor integrated circuit.

FIG. 7 is a diagram showing another example of an AC characteristic test circuit in a conventional semiconductor integrated circuit.

[Explanation of symbols]

1 scan signal input terminal 2 scan signal output terminal 3-1 to 3-3 data signal input terminal 4-1 and 4-2 data signal output terminal 7 scan mode switching terminal 8-1 and 8-2 clock phase adjustment terminal 9 clock Signal input terminal 10 Test mode switching terminal 11, 12 Clock monitor terminal 20-1 to 20-5 Scan flip-flop (scan FF) 30 Combination circuit 40 Clock generation circuit 108, 109, 112 Latch circuit 110 2 Input 1 output selection circuit 111 1-input 2-output selection circuit 206 Delay adjustment buffer circuit 207 4-input 1-output selection circuit 208 Buffer circuit 209 2-input 1-output selection circuit 210 Inverter circuit

Claims (3)

[Claims] 1. A test circuit for performing an AC characteristic test by applying test data to an internal combinational circuit using scan lines, wherein normal data input, scan input, data retention and A plurality of input scan flip-flops that perform inversion are provided, and normal data output, scan output, data retention and inversion are performed on the output side of the combinational circuit, and it is possible to combine with each of the plurality of input scan flip-flops. A clock generation circuit that includes a plurality of output scan flip-flops, sets a delay time of a corresponding propagation path by a combination of the input flip-flops and the output flip-flops, and inputs a clock signal to the input flip-flops and the output flip-flops. The ingredients A test circuit characterized by being provided. 2. The test circuit according to claim 1, wherein each of the plurality of input flip-flops and the plurality of output flip-flops includes first and second latch circuits to which different clock signals are input, and A test circuit comprising: a selection circuit connected to an output stage of a second latch circuit; and a third latch circuit for controlling the selection circuit. 3. The test circuit according to claim 1, wherein the clock generation circuit includes a delay adjustment buffer circuit, and thereby corresponds to a combination of the input flip-flop and the output flip-flop. A test circuit characterized by arbitrarily setting a delay time of a propagation path.