JPH08108981A - Information display system in elevator system - Google Patents

Abstract

PURPOSE: To display many informations containing an animation at a high speed together with elevator operating information by displaying a single image or plural images by plural display panels in an elevator car or in an elevator hall. CONSTITUTION: An image signal source 1 outputs a composite video signal to a transmitting part a2, and transmits it to an image processing part 6 by a cable system. The image processing part 6 digitalizes the signal, and produces and stores display data of a display part 10. An information processing part 4 inputs a still picture from a graphic signal source 3, and produces and stores display data by digitalizing it. A transmitting part b5 transmits it to an elevator information processing part 8 by a cable system. The elevator information processing part 8 to which information from an elevator information source 7 is inputted produces stage information display data corresponding to it, and produces and stores display data by superimposing still picture data on it. A synthesizing part 9 superimposes the display data of the image processing part 6 and synthesized display data on each other, and outputs it to a display part 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention provides a user with general information such as elevator operation information such as elevator position and elevator status, and guidance information including moving images in an elevator car or hall. The present invention relates to an information display system for displaying.

[0002]

2. Description of the Related Art As a conventional device for displaying elevator operation information in an elevator car or hall for passengers using an elevator, a device described in Japanese Patent Application Laid-Open No. 2-261787 is known.

According to this device, general information such as event information in the building in which the elevator is installed and weather forecast is displayed as a still image (graphic display) using pictures and characters together with elevator operation information such as floor display. , The operation information can be displayed without impairing the visibility.

[0004]

Now, with the progress of the advanced information society in recent years, there has been a demand for displaying advanced information including natural images and moving images as general information together with elevator operation information. ing.

However, a natural image and a moving image have much more information than a still image using pictures and characters, and the apparatus disclosed in the above-mentioned Japanese Patent Laid-Open No. 2-261787 cannot cope with this. .

In the device disclosed in Japanese Patent Laid-Open No. 2-261787, only one display panel, which is a display device, is displayed, and if a large amount of information is displayed, the visibility is impaired. Therefore, a large amount of information can be displayed. could not.

Therefore, the present invention provides information in an elevator system that has a plurality of display panels in an elevator hall or an elevator car and can display a lot of information including moving images together with elevator operation information at high speed. It is intended to provide a display system.

[0008]

In order to achieve the above object, the present invention provides a video signal source such as a TV or VTR, a graphic signal source such as an image scanner, an information processing section, a transmission section a in an elevator machine room. Equipped with a transmission unit b, an elevator car has an elevator information source such as elevator operation information,
A video processing unit, an elevator information processing unit, a synthesizing unit, and a display unit are provided, and moving image data of the video signal source in the elevator machine room is transmitted to the transmission unit a by a luminance signal, a carrier color signal, horizontal and vertical synchronization signals, and a color synchronization signal. The composite video signal including the signal is transmitted to the image processing unit in the elevator car using the first transmission cable, and the display data of the graphic information of the information processing unit in the elevator machine room is transmitted as a digital signal by the transmission unit. Using the second transmission cable of b, the information is transmitted to the elevator information processing unit in the elevator car, the information of the elevator information source in the elevator car and the graphic information of the information processing unit are combined, and in the combining unit, the image processing unit The digitized video signal and the digital signal synthesized by the elevator information processing unit are synthesized and displayed on the display unit.

Further, the elevator car is provided with a storage device for storing a still image of the elevator operation information and general information transmitted to the elevator car, and the elevator information processing unit is responsive to the elevator operation information generated in the elevator car. Then, the stored elevator operation information is read out, and in the combining unit, the digitized video signal of the image processing unit and the elevator operation display information read out from the storage device in the elevator information processing unit are combined and displayed in the display unit. It is to display.

The display unit is composed of a plurality of display panels, and a plurality of display panels constitutes one image, or a plurality of display panels independently constitutes an individual image for display. Is.

[0011]

According to the information display system in the elevator system of the present invention, one image or a plurality of images are displayed in the elevator car or in the elevator hall by using a plurality of display panels. It can display a lot of information such as moving images, general information such as event information in buildings where elevators are installed, weather forecasts, etc. Also, multiple display panels are regarded as one screen, and display information is displayed. Since it can be displayed in large size, it is easy for passengers to see and a good operation display can be realized.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the information display system in the elevator system according to the present invention will be described below.

FIG. 1 shows the configuration of the information display system according to this embodiment.

In the figure, 11 is an elevator machine room, 12 is an elevator car, and 13 is an elevator hoistway.

Further, the elevator machine room 11 is provided with a display control device 14, and the display control device 14 is a television (TV) or a video tape recorder (VTR).
Such as a video signal source 1 for outputting a moving image, a transmission unit a2,
A graphic signal source 3 for outputting still image data such as an image scanner, an information processing unit 4, and a transmission unit b5 are provided.

Further, the elevator car 12 is provided with a display device 201. The display device 201 includes an image processing unit 6, an elevator information source 7 for outputting elevator operation information, and information obtained by developing the elevator operation information on an image. The elevator information processing unit 8 that outputs the still image data for presentation, the combining unit 9, and the display unit 10 are provided.

Here, the transmission section a2 and the transmission section b5 of the machine room 12 of the elevator are connected to the video processing section 6 and the elevator information processing section 8 in the elevator car 12 by cables, respectively.

Next, FIG. 2 shows an example of arrangement of the display devices in the elevator car 12, and FIG. 3 shows an example of display.

In the figure, 201 is a display device, 202 is a door, and 2
Reference numerals 03 and 204 denote operation panels, and 320, 321, and 322 denote display panels. The display unit 10 in the display device 201 is composed of a plurality of display panels.
It is assumed that the display panels are arranged and arranged as shown in FIG. Further, the display device 201 is arranged above the elevator door 202 in consideration of the visibility of passengers.
Further, the operation panel 203 displays the same information as one display panel of the display device 201 or other information such as floor information so that the passenger / operator can see the floor information to be stopped. . Display panels 320, 321,
322 and a display example of the operation panel 203 in FIG.
It shows in (b).

FIG. 3A shows an example in which three display panels independently display individual videos including moving images, and the same display panel 321 and operation panel 203 are displayed. FIG. 3B shows three display panels 320, 32.
1 is an example of displaying one video including a moving image at 322. Different display panels 320, 321, 322 and operation panel 203 are displayed.

Note that FIG. 2 is an example of a display device, and the number and arrangement of displays are not limited to this. In addition, as the display unit 10 of the display device in the same cage,
You may arrange | position a display in two or more places.

With the above-described structure, the video signal source 1 displays the event information of the building as a moving image on the display unit 10.
Supply to. The video signal source 1 also outputs a composite video signal including a luminance signal, a carrier color signal, horizontal and vertical synchronization signals, and a color synchronization signal to the transmission unit a2, and the transmission unit a2.
Transmits the input composite video signal by wire to the image processing unit 6 in the elevator car 12. Then, the video processing unit 6 inputs the transmitted composite video signal, digitizes the signal, and generates and stores digital display data corresponding to three frames of the display unit 10.

Further, the graphic signal source 3 outputs the still image data to the information processing section 4, and the information processing section 4 digitizes the inputted still image data and displays the display data corresponding to three frames of the display section 10. Generate and store. Then, the stored digitized display data is read synchronously and output to the transmission unit b5. Then, the transmission unit b5 transmits the input display data by wire to the elevator information processing unit 8 in the elevator car 12.

The elevator information source 7 inputs elevator position information and elevator information from the elevator car 12 and outputs it to the elevator information processing section 8. Elevator information source 7
Then, the elevator information processing unit 8 that has received the elevator position information, elevator information, and the like generates floor information display data corresponding to the information, and superimposes the still image data transmitted from the transmission unit b5 and the floor information display data. Display data corresponding to three frames of the display unit 10 is generated and stored. Then, the combining unit 9 compares the digitized video display data stored in the video processing unit 6 with the combined display data of the still image and the floor information stored in the elevator information processing unit 8 according to the priority. It is superimposed and output to the display unit 10. Then, the display unit 10 inputs the display data from the combining unit 9 and displays it.

The moving image output from the video signal source 1 includes, for example, building event guides and general information such as weather forecasts.

The specific configurations and operations of the display control unit 14 and the display device 201 will be described below.

Now, the video signal source 1 of the display control device 14 uses a TV or VTR video as a moving image to be displayed on the display unit 10, and its output is a luminance signal, a carrier color signal, horizontal and vertical synchronization signals, and a color. It is assumed that the composite video signal includes a sync signal. Further, assuming that the graphic signal source 3 is an image scanner, the signal flow in the display control device 14 and the display device 201 according to this embodiment is as shown in FIG. The same parts as those in FIGS. 1, 2 and 3 are designated by the same reference numerals.

In FIG. 4, 407 is a personal computer (hereinafter referred to as "PC") to which an image scanner can be connected.
411 is a frame memory, and these are included in the information processing unit 4. Also, 401 is video-R
GB conversion circuit, 402 is A / D conversion circuit, 403, 40
Frame memories 4, 405, and 406 are included in the video processing unit 6. Further, 415 is a floor information generation circuit including a microcomputer or a peripheral device thereof, 416, 417, 418, and 419 are frame memories, and 420 is a storage device, which are included in the elevator information processing unit 8. . 421, 422, 4
Reference numerals 23 and 424 are frame memories for storing the display data combined by the combining unit 9.

Here, the PC 407 inputs the digital data of the image output by the image scanner used as the graphic signal source 3, and stores it in the frame memory 411 for one frame. And the transmission part b5
The digital data stored in the frame memory 411 is sequentially transmitted to the microcomputer 415.

The video-RGB conversion circuit 401 converts the composite video signal transmitted from the TV or VTR via the transmission section a2 into RGB three primary color signals, and the converted R signal.
The GB three primary color signals are input to the A / D conversion circuit 402. The A / D conversion circuit 402 samples and digitizes at a frequency four times higher than the color carrier wave frequency of 3.58 MHz, and digitizes the frame memories 403, 404, 405, and 4.
One frame is stored in 06.

Further, the microcomputer 415 receives the registration display data of characters and symbols from the transmission section b5 and receives the storage device 42.
0, and when elevator operation information is input from the elevator information source 7 during elevator operation,
The operation display data corresponding to the information is read from the storage device 420, and further superimposed on the digital data of the still image sequentially transmitted from the transmission unit b5, and the display panels 320, 321, 322 in the display unit 10 are operated. Panel 203
The display data to be displayed on is generated one frame at a time,
The frames are sequentially stored in the frame memories 421, 422, 423, 424. Here, the storage device 420 stores operation display data representing one frame of still image data representing a plurality of frames and a partial portion required to form one frame.

The storage device 420 is a hard disk or a memory (for example, a flash memory) that retains stored contents even when the power is turned off. In addition, the display data of the characters and symbols used in the elevator operation information is stored in the storage device 420.
It may be a fixed data format to be stored at the time of installation, or when the power of the elevator is turned on, the elevator machine room 11
The display data from the storage device 42 is used as registered display data.
It may be a format for transmitting to 0.

The synthesizing unit 9 includes frame memories 403 and 40.
4, 405, 406 and 416, 417, 418, 41
The video digital display data and the composite digital display data respectively stored in 9 are sequentially read at the same time, and the display data of the video signal source 1 and the composite display data of the graphic signal source 3 and the elevator information source 7 are overlapped in accordance with the priority. In addition, the display panels 320, 321, 32 in the display unit 10
2. Display data for one frame displayed on the operation panel 203 is stored in the frame memories 421, 422, 42.
3 and 424, respectively. The display unit 10 then reads the display data from the frame memories 421, 422, 423, 424, and displays the display panels 320, 321, 32.
2. Display on the operation panel 203.

The video-RGB conversion circuit 401 is a SON.
A / D conversion circuit 402 using CXA1585Q manufactured by Y
Can be realized by using a Hitachi resolution 8-bit HA19209TP. In this embodiment, the display unit 1
If 0,260,000 colors are to be displayed, 6 bits of RGB primary color signals are required for each, so the A / D conversion circuit 4
02 can be realized by using the upper 6 bits of the 8 bits. When displaying 260,000 colors, the frame memories 403, 404, 405, 406, 411, 41 are used.
6, 417, 418, 419, 421, 422, 42
A RAM having a capacity corresponding to 260,000-color display is used as 3, 424.

Hereinafter, the display control device 14 and the display device 201 will be described.
The details of each unit will be described.

First, FIG. 5 shows the detailed structure of the transmission section a2.

In FIG. 5, 501 is a boost circuit, and 502 is a 5C2V coaxial cable line used as a first transmission cable.

In such a configuration, the boost circuit 5
01 represents the composite video signal input from the video signal source 1 in consideration of the transmission distance to the inside of the elevator car where the display unit 10 is mounted, and outputs it to the 5C2V coaxial cable line 502 to display the composite video signal. It is transmitted to the video processing unit 6 of the device 201.

Next, details of the information processing section 4 will be described.

FIG. 6 shows the internal structure of the information processing section 4. The same parts as those in FIG. 4 are designated by the same reference numerals.

Reference numeral 601 is a read signal generation circuit of the frame memory 411, 602 is a transmission circuit, and 603 is a PC 407.
Is a read start signal for permitting the start of reading the display data of the frame memory 411, 604 is parallel display data read from the frame memory 411, and 605 is a read signal. Here, between the PC 407 and the frame memory 411, the display data output from the PC 407 may be directly written to the frame memory 411 or a connection may be made as an I / O of the PC 407. For example, in the latter case, the PC 407 can temporarily take in the still image read by the image scanner 4 and write the display data for one frame of the display unit 10 into the frame memory 411 by an I / O command of the PC 407. Then, when the writing of the display data to the frame memory 411 is completed, the PC 407 outputs the read start signal 603 permitting the reading. Memory reading circuit 601
When the read start signal 603 is detected, the read signal 605 is output, and the frame memory 411 stores the still image data for one frame or the registered display data as the individual operation display data constituting one frame. Are output in parallel. Display panels 320, 321,
When one video image is formed by 322 as shown in FIG. 3B, still image data is expanded in the frame memory 411 so that the video images of the display panels 320, 321, 322 are continuous, and the transmission unit b5 The display data is sequentially transmitted to the microcomputer 415.

For example, as shown in FIG. 7, the operation in the case where the still image data is displayed so as to flow from right to left by using the three display panels 320, 321, 322 will be described.

FIG. 8 shows frame memories 416, 417,
418, and a development memory 801 in the microcomputer 415
FIG. The dotted line represents a line divided in units of words (16 bits).

First, the transmission section b5 transmits and stores the display data in the expansion memory 801 in the microcomputer 415.
Then, the microcomputer 415 shifts the display data in the expansion memory 801 to the left by one word, and the expansion memory 8
The data protruding from 01 is stored in the frame memory 418. Next, the shifted data is further shifted to the left by one word. In this way, the data is sequentially shifted leftward by one word, and the expansion memory 8
After shifting all the data in 01, the microcomputer 4
Reference numeral 15 expands the display data transmitted from the frame memory 411 via the transmission unit b5 in the expansion memory 801.
Similar processing is performed. In this case, the data in the frame memory 418 is sequentially shifted to the frame memory 417, and when all the data is filled in the frame memory 417, the data is sequentially shifted to the frame memory 416.

The operation up to displaying on the display panel 320 in the display unit 10 will be described below, but the display panels 321 and 322 in the display unit 10 and the operation panel 203 will be described.
The same configuration is also applied to the above, and the same processing is performed.

Next, details of the transmission section b5 will be described.

FIG. 9 shows a part of the internal structure of the transmission section b5. The same parts as those in FIG. 6 are designated by the same reference numerals.

Reference numeral 901 denotes a parallel-serial conversion circuit, 9
Reference numeral 02 is a transmission circuit, 903 is a twisted pair cable line as a second transmission cable, and 904 is a synchronization signal from the memory read signal generation circuit 601. Here, the twisted pair cable 903 will be described as being capable of transmitting the digital display data of the graphic signal source 3 at least in accordance with the ascending / descending speed of the elevator, for example, for one frame while going up from the first floor to the second floor. The parallel-serial conversion circuit 901 converts the digital display data 604 from a parallel signal into a serial signal and outputs the serial signal to the transmission circuit 902. The transmission circuit 902 outputs the input parallel signal to the twisted pair cable line 903. The parallel-serial conversion circuit 901 may be configured to directly perform parallel-serial conversion on the parallel display data 604 read from the frame memory 411. Alternatively, the parallel-serial conversion circuit 901 may be connected by I / O and read as a serial signal by an I / O command. It may be configured. Further, the transmission circuit 902 is 20 Mbps.
Texas Instruments SN75ALS192 capable of high-speed data transmission of [bit / sec] or higher
Can be realized by using.

Next, details of the video processing unit 6 will be described.

FIG. 10 shows the display resolution in the NTSC television system.

Reference numeral 1001 is a blanking period, 1002 is a display valid period, 1003 is a broken line, and 1004 is a solid line. In the case of the NTSC television system, the horizontal frequency is approximately 15.75 kHz, and the number of vertical scanning lines is 525, and interlaced scanning of 60 Hz in one field is performed. The frequency of the color carrier is 3.58 MHz, and in this embodiment, the video processing unit 6 digitizes the color carrier at a frequency four times and stores it in the field memory.
In this case, the resolution in the horizontal direction is 910 dots as expressed by the equation (Equation 1).

[0052]

[Equation 1]

Here, about 910 dots in the horizontal direction and 5 dots in the vertical direction.
When the blanking period 701 is extracted from the 25 lines, the resolution in the display effective period is approximately 755 dots in the horizontal direction and 480 lines in the vertical direction. In this embodiment, the display device used in the display unit 10 is a liquid crystal display device having a resolution of horizontal 640 dots and vertical 480 lines, and in particular, a Thin Film Tran which is an active element for each pixel of the display screen.
TFT liquid crystal with thin film (Thin Film)
A case of using a Transistor liquid crystal (LCD) display device will be described. As described above, in the NTSC television system, interlaced scanning of 60 Hz in one field is performed, so the number of vertical scanning lines in one field is 240, which is half the number of vertical scanning lines in one frame, 480 lines. Therefore, in this embodiment, it is necessary to increase the display data stored in the field memory to one frame of the display unit 10.

FIG. 11 is a detailed block diagram of the video processing unit 6 in consideration of the above. The same parts as those in FIG. 4 are designated by the same reference numerals.

1101 is a sync separation circuit, 1102 is an oscillation circuit, 1103 is a write memory control circuit, 1104 is a field memory, 1105 is a line memory, 1106.
Is a selector, 1107 is a write signal of the field memory 1104 (hereinafter referred to as a field memory write signal), 1108 is a write signal of the line memory 1105 (hereinafter referred to as a line memory write signal), 1109
Is a switching signal of the selector 1106, 1110 is a write signal of the frame memory 403 (hereinafter referred to as a frame memory write signal), 1111 is a field memory read signal from the synthesizing unit 9, 1112 is a line memory read signal from the synthesizing unit 9, Reference numeral 1113 is a read signal of the frame memory 403 from the combining unit 9.

In such a configuration, video-RGB
The conversion circuit 401 converts the composite video signal into RGB3 primary color signals and outputs the signals to the A / D conversion circuit 402. A
The / D conversion circuit 402 samples and digitizes the RGB3 primary color signals at a frequency four times higher than 3.58 MHz which the oscillation circuit 1102 constantly outputs. On the other hand, the sync separation circuit 1101 separates the sync signal, extracts the horizontal sync signal and the vertical sync signal, and outputs them to the write memory control circuit 1103. The write memory control circuit 1103 holds the write start position designation and the write end position designation from the horizontal sync signal in advance, and further holds the write start position designation from the vertical sync signal to start the storage in the field memory 1104. Control termination. Then, the write memory control circuit 1103 uses the field memory 1
A field memory write signal 1107 for writing to 104 is generated, and display data is written to a desired address. Then, as the display data written in the field memory 1104, one line of data is sequentially read by the field memory read signal 1111 from the synthesizing unit 9 and output to the selector 1106. At the same time, the line memory write signal 1108 from the write memory control circuit 1103 stores the data for one line in the line memory 1105. Line memory 110
The display data stored in No. 5 is sequentially read by the line memory read signal 1112 from the synthesizing unit 9, and is output to the selector 1106. The selector 1106 performs switching by the selector switching signal 1109 from the write memory control circuit 1103, and the field memory 110
4 and the data of the first line input from the line memory 1105 are alternately output to the frame memory 403. Thereafter, the same operation is performed on the second line and thereafter, and the display data of the first line to the 240th line is sequentially written to the frame memory 403 by two lines by the frame memory write signal 1110 of the write memory control circuit 1103, and the 240th line is displayed. The data is doubled to 480 lines, and the display data for one frame of the display panel in the display unit 10 is stored. FIG. 10 shows the field memory 1
10 is a schematic diagram of display data storage of 104 and the frame memory 403.

Next, the detailed operation of the write memory control circuit 1103 will be described with reference to FIGS.

FIG. 13 shows the write memory control circuit 110.
3 is a block diagram of one embodiment of No. 3 of FIG.

1301 is a horizontal write start position register, 1302 is a horizontal counter, 1303 is a comparison circuit, 1
304 is a horizontal write end position register, 1305 is a comparison circuit, 1306 is a vertical write start position register, 1
307 is a vertical counter, 1308 is a comparison circuit, 1309.
Is a write control signal generation circuit, 1310 is 3.58 MH
4 times the frequency of z (hereinafter referred to as 4fsc clock),
1311 is a horizontal sync signal, 1312 is a vertical sync signal, 1
313 is a horizontal counter output, 1314 is a horizontal write start position comparison result, 1315 is a horizontal write end position comparison result, 1316 is a vertical counter output, 1317 is a vertical write start position comparison result, 1318 is a field memory write address reset signal, and 1319 is A line memory write address reset signal, 1320 is a frame memory write address reset signal, 1321 is a write clock, and 1322 is a selector switching signal generation circuit.

FIG. 14 is an operation timing chart of the block diagram shown in FIG. The same parts as those in FIGS. 11 and 13 are designated by the same reference numerals.

Reference numeral 1401 is an address of the field memory 1104, the line memory 1106, and the frame memory 403.

Here, hereinafter, the frame memories 403, 404, 405, 406, 411, 412 shown in FIG.
413, 414, 416, 417, 418, 419, 4
21, 422, 423, 424, and the field memory 1104 are T manufactured by Texas Instruments.
A description will be made assuming that the PD4101C manufactured by NEC is used as the MS4C1050 and the line memory 1105. The TMC4C1050 has a bit width of 4 bits and a capacity of 256 kbits. Therefore, as shown in FIG. 13, when used as a field memory, the information amount of the display data is 6 bits for the RGB3 primary color signal, (64
Since there are 0 dots × 240 lines =) 154 k bits, there are two, and when used as a frame memory, the information amount of the display data is 6 bits for the RGB3 primary color signal,
Since (640 dots × 480 lines =) 307 k bits, it can be realized by using four. Also, TMC4C
The 1050 can independently perform writing and reading asynchronously. In the case of writing, the address is set to zero by the write address reset signal and the write clock is input to write the data, and then the address is automatically set to 1
In addition, it is automatically updated. The outline of the operation of the μPD41101C used in the line memory 1105 is as follows.
It is similar to TMC4C1050.

Further, the horizontal write start position register 1301 and the horizontal write end position register 130 are previously set.
4. The vertical write start position register 1306 is set with values indicating the number of pixels from the horizontal sync signal position to the effective pixel, the number of horizontal effective pixels, and the distance from the vertical sync signal position to the effective line position, respectively. In the present embodiment, the display device used in the display unit 10 has the horizontal direction 64 as described above.
TFT with a resolution of 0 dots and 480 lines in the vertical direction
A liquid crystal display device was used. Therefore, if the value X is written in the horizontal write start position register 1301,
The horizontal write end position register 1304 has E = (X +
640) is written. It is assumed that the value Y is written in the vertical write start position register 1306.
The vertical write start position register 1306 and the vertical counter 1307 determine the start position of fetching data into the field memory 1104 in the vertical direction. The vertical counter 1307 is zero-cleared by the vertical synchronizing signal 1312 and counts with the horizontal synchronizing signal. Then, when the set value of the vertical write start position register 1306 and the count value of the vertical counter 1307 become equal, the comparison circuit 1308 indicates that the vertical write start position comparison result 1 indicates that the line is a line to start capturing.
317 is notified to the write control signal generation circuit 1309. On the other hand, the horizontal counter 1302, the horizontal write start position register 1301, and the horizontal write end position register 1
Reference numeral 304 is for determining the horizontal writing range of the field memory 1104. Horizontal counter 1302
Is cleared to zero by the horizontal sync signal 1311 and 4fsc
Count by clock 1310. Horizontal counter 13
02 count value and horizontal write start position register 1301
The comparison circuit 1303 compares the set values of the above, and if the two values are equal, the comparison circuit 1303 outputs the horizontal write start position comparison result 1314 to the write control signal generation circuit 1309. The write control signal generation circuit 1309 inputs the horizontal write start position comparison result 1314 from the comparison circuit 1303, refers to the vertical write start position comparison result 1317 from the comparison result 1308, and outputs the field memory write address reset signal 1318 to output 4fsc. The synchronized write clock 1321 is sequentially output at the same frequency as the clock 1310, and the display data for one line is written to the field memory 1104. And
When the count value of the horizontal counter 1302 becomes equal to the set value of the horizontal write end position register 1304, the comparison circuit 1
305 outputs the horizontal write end position comparison result 1315 to the write control signal generation circuit 1309, and the write control signal generation circuit 1309 stops the write clock 1321. Next, the horizontal counter 1302 is cleared to zero by the horizontal synchronizing signal 1311, and the display data of the second line is written in the same manner as above. After the second line, the write control signal generation circuit 1309 is compared to the comparison circuit 1
Since there is no vertical write start position comparison result 1317 from 308, the field memory write address reset signal 1318 is not output. By repeating such an operation, display data for one field is stored in the field memory 1104. Writing to the line memory 1105 is the same as writing the display data for one line to the field memory 1104 described above. Then, after writing the display data of the first line, the line memory write address reset signal 1319 is output to the line memory 1105, the address is set to zero, and the display data of the second line is written. repeat. The writing to the frame memory 403 is similar to the case of writing the display data to the field memory 1104 described above, but the display data of the first line of the field memory 1104 is written to the first line of the frame memory 403. The display data of the first line of the line memory 1105 is written in the. The same operation is performed thereafter, and the field memory 1104 and the line memory 11
The display data of 05 is alternately written line by line, and the display data is stored for one frame of the display panel 320 in the display 10. Then, the frame memory write address reset signal 1320 is output to the frame memory 403,
The address is set to zero and the same operation is repeated from the second frame onward.

Next, details of the elevator information processing section 8 will be described.

FIG. 16 shows a part of the internal configuration of the elevator information processing section 8. The same parts as those in FIGS. 1, 4 and 9 are designated by the same reference numerals.

In the figure, 1601 is a receiving circuit, 1602 is a serial-parallel conversion circuit, and 1603 is a microcomputer 415.
Is a read start signal for permitting the start of reading the display data of the frame memory 416, and 1604 is a read signal of the frame memory 416. In this embodiment, the receiving circuit 1601 is a SN75 manufactured by Texas Instruments Incorporated.
Serial-parallel conversion circuit 16 using ALS193
02 can be realized by using MSM82C51A manufactured by Oki Electric. In the embodiment of FIG. 16, the display data is stored in the storage device 420 via the microcomputer 415, but the storage device 420 is directly stored without passing through the microcomputer 415.
The configuration may be stored in.

The receiving circuit 1601 inputs the digital display data of the still image transmitted by the twisted pair cable 903 and the registration display data to be registered in advance,
It is output to the serial-parallel conversion circuit 1602. The serial-parallel conversion circuit 1602 includes a reception circuit 1601.
The digital display data of the still image and the registration display data registered in advance are input, the serial signal is converted into a parallel signal, and the parallel signal is output to the microcomputer 415. The microcomputer 415 uses the serial-parallel conversion circuit 1
The parallel digital display data output by 602 is temporarily stored in the storage device 420, and when the elevator floor information and the operation information from the elevator information source 7 are input, the operation display data registered in advance corresponding to the information and The digital display data of the stored still image is stored in the storage device 420.
Read from, synthesize, and display panel 3 in display unit 10.
20 pieces of display data for one frame are generated and written in the frame memory 416. When the writing is completed, the reading start signal 1603 permitting reading of the frame memory 416 is output to the reading memory control circuit arranged in the synthesizing unit 9. When the read start signal 1603 is input, the read memory control circuit generates a frame memory read signal 1604 and reads the composite display data stored in the frame memory 416. Further, by having the frame memory 416 for at least two frames of the display panel 320 in the display unit 10,
By alternately writing and reading, the screen of the display panel 320 in the display unit 10 can be switched at high speed.

Next, details of the synthesizing unit 9 will be described.

FIG. 17 shows an embodiment of the internal structure of the synthesizing unit 9. The same parts as those in FIG. 16 are designated by the same reference numerals.

In the figure, 1701 and 1702 are holding circuits and 1
703 is a read memory control circuit, 1704 is a transmission circuit, 1705 is a selector, 1706 is a priority control circuit,
1707 is a holding circuit, 1708 is a frame memory 403.
Display data read from the frame memory 416, display data 1709 read from the frame memory 416, and 4f display data 1710.
sc clock, 1711 and 1712 are data latch signals, 1713 is a read clock, 1714 is a read address reset signal of the frame memories 403 and 416, 1715 is a read address reset signal of the field memory 1104, and 1716 is a line memory 1105.
Read address reset signal, 1717 is a vertical synchronizing signal, and 1718 is a horizontal synchronizing signal. In FIG. 11, the read address reset signal 1715 of the field memory 1104 and the read clock 1713 are combined into a field memory read signal 1111, and the line memory 1
The read address reset signal 1716 of 106 and the read clock 1713 are combined into a line memory read signal 1112, and the read address reset signal 1714 and read clock 1713 of the frame memory 403 are combined.
Is also described as a frame memory read signal 1113.

The read memory control circuit 1703 receives the 4fsc clock 1710 output from the transmission circuit 1704 and receives the vertical sync signal 1 corresponding to the composite video signal.
717 and a horizontal synchronization signal 1718 are generated. Further 4f
A read clock 1713 and a frame memory read address reset signal 1714 necessary to read the display data stored in the frame memories 403 and 4163, the field memory 1104 and the line memory 1105 from the sc clock 1710 and the vertical sync signal 1717 and the horizontal sync signal 1718. , Field memory read address reset signal 1715, line memory read address reset signal 1716, data latch signals 1711, 171
2 is generated. The holding circuits 1701 and 1702 temporarily hold the display data read from the frame memories 403 and 416, respectively, and output the display data to the selector 1705 and the priority control signal 1706. Priority control signal 1706
Stores the priority of the composite data of the graphic signal source 3 and the elevator information source 6 and the display data of the video signal source 6 in advance. The stored priority and the frame memory 4 output from the holding circuits 1701 and 1702
Display data 1708 read from 03, 416, 1
A selector 705 is controlled by 709 to determine which display data of the outputs of the holding circuits 1701 and 1702 is output to the holding circuit 1707. Assuming that the composite data of the graphic signal source 3 and the elevator information source 6 and the video signal source 6 have higher priority in this order, the priority control signal 1706 sees the output from the holding circuit 1702 and displays it. If there is data to be stored, the selector 1705 is switched to the holding circuit 1702 side. Here, the holding circuit 170
If there is no data to be displayed in 2, the selector 1705 is switched from the priority to the holding circuit 1701 side, and the holding circuit 1
Output to 707. Also, the priority control signal 1706 is
The display screen is divided into at least two or more display screens, the first area outputs composite data of the graphic signal source 3 and the elevator information source 6, and the second area outputs information of the video signal source 6. It is also possible to control the selector 1705 to do so. Further, it can be easily understood that the combination of priority and area division can be performed.

Next, details of the read memory control circuit 1703 will be described.

FIG. 18 shows a read memory control circuit 1703.
19 shows the internal configuration of the read memory control circuit 1 shown in FIG.
703 shows a timing chart of 703. 18 and 19, the same components are designated by the same reference numerals.

In the figure, reference numeral 1801 denotes a synchronizing signal generating circuit, 18
02 is a horizontal read start position register, 1803 is a horizontal counter, 1804 is a horizontal read end position register,
1805 and 1806 are comparison circuits, 1807 is a vertical read start position register, 1808 is a vertical counter, 180
9 is a comparison circuit, 1810 is a read control signal generation circuit,
1811 is a horizontal counter output, 1812 is a horizontal read start position comparison result, 1813 is a horizontal read end position comparison result, 1814 is a vertical counter output, and 1815 is a vertical read start position comparison result. Further, 1901 is an address of the frame memories 403 and 416.

The sync signal generation circuit 1801 receives the 4fsc clock 1710 and generates a vertical sync signal 1717 and a horizontal sync signal 1718 corresponding to the composite video signal. The horizontal read start position register 1802, the horizontal read end position register 1804, and the vertical read start position register 1807 are set in advance with the set values of the write memory control signal 1103 described in FIG. Therefore, in the present embodiment, the value X is set in the horizontal read start position register 1802 as in the horizontal write start position register 1301. Then, the value E = (X + 640) is set in the horizontal read end position register 1804 as in the horizontal write end position register 1304. Further, the vertical read start position register 1807 has the same value Y as the vertical write start position register 1306.
Set. The operation of the block diagram shown in FIG. 17 is the same as the operation of the write memory control circuit 1103 described with reference to FIG. 13, except that the sync signal generation circuit 1801 generates the vertical sync signal 1717 and the horizontal sync signal 1718. Frame memories 403, 416, field memory 110
4. The signals output to the line memory 1105 are the frame memory read address reset signal 1714, the field memory read address reset signal 1715, the line memory read address reset signal 1716, and the read clock 1713. The vertical read start position register 1807 and the vertical counter 1809 determine the vertical read position of the frame memories 403 and 416. The vertical counter 1808 is zero-cleared by the vertical synchronizing signal 1717 and is multiplied by the horizontal synchronizing signal 1718. The comparison circuit 1809 compares the preset setting value of the vertical read start position register with the output 1814 of the vertical counter, and if they match, the frame memory 403,
The vertical start position comparison result 1815 indicating that the line starts reading from 416 is output to the read control signal generation circuit 1810. On the other hand, the horizontal read start position register 1802 and the horizontal read end position register 1804
And the horizontal counter 1803 are the frame memories 403, 4
16 horizontal read ranges are determined. The horizontal counter 1803 is zero-cleared by the horizontal sync signal 1718,
It is multiplied by the 4fsc clock 1710. Horizontal counter output 1811 and horizontal read start position register 18
When the set values of 02 match, the horizontal read start position comparison result 1812 indicating that the horizontal read is started
Is output to the read control signal generation circuit 1810. The read control signal generation circuit 1810 inputs the horizontal read start position comparison result 1812 from the comparison circuit 1805, refers to the vertical start position comparison result 1815 from the comparison circuit 1809, and outputs the frame memory read address reset signal 1714. The synchronized read clock 1713 is sequentially output at the same frequency as the 4fsc clock 1710, and the display data for one line is read from the frame memories 403 and 416. Then, the horizontal counter output 18
03 and the set value of the horizontal read end position register 1804 match, the comparison circuit 1806 reads the horizontal read end position comparison result 1813 and the control signal generation circuit 181.
0, and the read control signal generation circuit 1810 stops the read clock 1713. Next, horizontal sync signal 1
The horizontal counter 1803 is cleared to zero by 718, and the display data of the second line is sequentially read from the frame memories 403 and 416 simultaneously in the same manner as above. The operation of the second and subsequent lines is the read control signal generation circuit 181.
To 0 Vertical comparison result 18 from the comparison circuit 1809
Since 15 is not output, the frame memory read address reset signal 1714 is not output. By repeating this operation, the display data for one frame is sequentially read from the frame memories 403 and 416.

Next, details of the priority control circuit 1706 will be described.

FIG. 20 shows the internal structure of the priority control circuit 1706, and FIG. 21 shows a timing chart of the priority control circuit 1706. The same parts as those in FIG. 17 are designated by the same reference numerals.

In the figure, reference numeral 2001 is an address control circuit for display data of the video signal source 1, 2002 is an address control circuit for display data of the graphic signal source 3, 2003 is a selector control circuit, and 2004 is display data latched by the holding circuit 1701. , 2005 is display data latched by the holding circuit 1702, 2006 is a control signal of the same frequency synchronized with the read clock 1713 from the read control circuit 1706, 2007 and 2008 are display data selection signals, and 2009 is a selector switching signal. .

The address control circuits 2001 and 2002 set an address in which area the display data of the video signal source 1 and the combined display data of the graphic signal source 3 and the elevator information source 8 are to be displayed. The display data selection signals 2007 and 2008 synchronized with the control signal 2006 for a set period can be output to the selector control circuit 1703. Selector control circuit 20
03 generates a selector switching signal 2009 from the display data selection signals 2007 and 2008, and a selector 1705
Is controlled to output the combined display data to the display panel 320 in the display unit 10.

Next, the display section 10 will be described.

FIG. 22 shows the internal structure of the display unit 10.
The same parts as those in FIGS. 3 and 4 are designated by the same reference numerals.

2201 is a liquid crystal controller, 2203 is a display data read signal, 2204 is a liquid crystal control signal, 2
Reference numeral 205 is a write control signal from the write memory control circuit 1103. The display data combined by the combining unit 9 is written into the frame memory 421 for one frame by the write control signal 2205 in the same display data storage method as the frame memo 403. Then, the liquid crystal controller 2201 sequentially reads the display data stored in the frame memory 421 with the display data read signal 2203, and the liquid crystal control signal 22 necessary for the TFT-LCD 320.
04 is output and converted into a display data rate and data format suitable for the TFT-LCD 320, and the TFT-LCD 320
Is displayed.

Next, an embodiment in which there are a plurality of elevators will be described with reference to FIG. The same parts as those in FIG. 1 are designated by the same reference numerals. 2301, 2302 are selectors, 2303
Is the first elevator car, 2304 is the elevator car 2303 hoistway, 2305 is the second elevator car,
2306 is the hoistway of the elevator car 2305, 2307
Is the first transmission cable of the elevator car 2303, 23
08 is the second transmission cable of the elevator car 2303,
2309 is a first transmission cable of the elevator car 2305, 2310 is a second transmission cable of the elevator car 2305, and 2311 is a selector control signal. When transmitting display data from one machine room to the display units 10 in two elevator cars, the information processing unit 4 determines to which of the elevator cars 2303 and 2305 the display data is transmitted. For example, if display data is transmitted to the elevator car 2303, the selector control signal 2
311 is output. When the selectors 2301 and 2302 receive the selector control signal 2311, the display data is sent to the first transmission cable 2307 and the second transmission cable 2307 of the elevator car 2303.
Data is transmitted to the transmission cable 2310. In the present embodiment, the case where there are two elevator cars has been described, but the present invention is not limited to this, and even if there are more elevator cars, there will be no problem in implementation if a similar system is used.

Further, in the present embodiment, the storage device 420 has been described as a hard disk or a flash memory, but there is no problem in realizing it as a battery backup using a DRAM.

In the present invention, a TFT-LC is used as a display device.
Although it has been described using D, the present invention is not limited to this.
In the liquid crystal display device, there is no problem in realizing the STN liquid crystal. In addition, there is no problem in realizing even a CRT. If a display device having a video signal input is used as the display unit 10, the display unit 10 can be realized only by the display device itself.

In the present invention, the resolution of the display unit 10 has been described as having a horizontal resolution of 640 dots and a vertical resolution of 480 lines, but the present invention is not limited to this, and the write memory control circuit 1103 and the read memory control circuit are not limited thereto. It is obvious that this can be dealt with by changing the setting value to 1703. In this case, the capacity of the frame memory increases or decreases according to the resolution.

Further, in the present invention, the signal to be transmitted is set to NTS.
Although the video signal of the C system has been described, the PAL system can also be used.

In this embodiment, the graphic signal source 3
Although the image scanner is used as the above description, the present invention is not limited to this, and may be graphic data created by a general-purpose drawing software of a PC, for example.

[0089]

As described above, according to the present invention,
Since the general information and the elevator operation display information are displayed using a plurality of display panels, more information can be displayed. Further, since each display panel is controlled independently, each display panel may display different information, or a plurality of display panels may constitute one screen and display it. Therefore, there is an effect that more information can be displayed at high speed, and more advanced information can be provided to passengers without impairing the recognition of elevator operation information.

[Brief description of drawings]

FIG. 1 is a block diagram of the present invention.

FIG. 2 is a diagram showing an arrangement example of display devices in an elevator car.

FIG. 3 is a diagram showing a display example 1 of the display device in the elevator car.

FIG. 4 is a detailed block diagram of one embodiment of the present invention.

FIG. 5 is a block diagram of an embodiment of a transmission unit a.

FIG. 6 is a block diagram of an embodiment of an information processing unit.

FIG. 7 is a diagram showing a second display example of the display device in the elevator car.

FIG. 8 is a schematic diagram of a frame memory.

FIG. 9 is a block diagram of an embodiment of a transmission unit b.

FIG. 10 is an explanatory diagram of resolution of NTSC system.

FIG. 11 is a block diagram of an embodiment of a video processing unit.

FIG. 12 is a diagram illustrating a display method on a display unit.

FIG. 13 is a block diagram of one embodiment of a write memory control circuit.

FIG. 14 is a timing chart of a write memory control circuit.

FIG. 15 is a data storage diagram of a memory.

FIG. 16 is a block diagram of an embodiment of an elevator information processing unit.

FIG. 17 is a block diagram of an embodiment of a combining unit a.

FIG. 18 is a block diagram of an embodiment of a read memory control circuit.

FIG. 19 is a timing chart of the read memory control circuit.

FIG. 20 is a block diagram of an embodiment of a priority control circuit.

FIG. 21 is a timing chart of the priority control circuit.

FIG. 22 is a block diagram of an embodiment of a display unit.

FIG. 23 is a block diagram of an embodiment when there are a plurality of elevators.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Video signal source, 2 ... Transmission part a, 3 ... Graphic signal source, 4 ... Information processing part, 5 ... Transmission part b, 6 ... Video processing part, 7 ... Elevator information source, 8 ... Elevator information processing part, 9 … Synthesis part, 10… display part, 11… machine room, 12… elevator car, 13… hoistway.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Narihiko Kasai 1099, Ozenji, Aso-ku, Kawasaki, Kanagawa, Ltd. System Development Laboratory, Hitachi, Ltd. (72) Inventor, Yoichi Watanabe 3681, Hayano, Mobara, Chiba Hitachi Device Engineering Co., Ltd. In-house (72) Inventor Kaname Iijima 1070 Ma, Katsuta City, Ibaraki Prefecture Hitachi Ltd. Mito Factory

Claims (7)

[Claims] 1. An information display system for displaying various kinds of information in an elevator car or an elevator hall, wherein a display unit for displaying an image on a screen comprises a plurality of display panels, and a first information input. And a second information input, a plurality of display panels compose one image,
2. An information display system in an elevator system, comprising means for synthesizing and displaying the display information of 1. and the second display information. 2. The information display system in an elevator system according to claim 1, wherein the plurality of display panels are independently controlled to individually display a plurality of images. 3. An information display system in an elevator system according to claim 1, wherein a plurality of display panels compose and display one moving image. 4. An information display system in an elevator system according to claim 1, wherein a plurality of display panels compose and display one still image. 5. The information display system in an elevator system according to claim 2, wherein a plurality of display panels independently form a moving image and are individually displayed on each display panel. 6. The information display system in an elevator system according to claim 2, wherein a plurality of display panels independently form a still image and are individually displayed on each display panel. 7. The information display system in an elevator system according to claim 1 or 2, wherein a plurality of display panels are connected and arranged so as not to have a joint.