JPH0799391A - Manufacture of multilayer board for electronic component mounting - Google Patents
Manufacture of multilayer board for electronic component mountingInfo
- Publication number
- JPH0799391A JPH0799391A JP5264223A JP26422393A JPH0799391A JP H0799391 A JPH0799391 A JP H0799391A JP 5264223 A JP5264223 A JP 5264223A JP 26422393 A JP26422393 A JP 26422393A JP H0799391 A JPH0799391 A JP H0799391A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- heat dissipation
- mounting
- manufacturing
- plating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は，貫通穴及び配線回路パ
ターンを有する電子部品搭載用多層基板の製造方法に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a multilayer substrate for mounting electronic parts, which has through holes and wiring circuit patterns.
【０００２】[0002]
【従来技術】従来，電子部品搭載用基板としては，図２
４に示すごとく，複数の絶縁基材９１，９２，９３を積
層した積層体９９を有すると共に，電子部品搭載部９０
の下部には放熱穴９１９を設けてなる電子部品搭載用多
層基板９がある。上記電子部品搭載用多層基板９は，上
記積層体９９を貫通する貫通穴９５と，配線回路パター
ン１と，ボンディングパッド１１とを有している。2. Description of the Related Art Conventionally, as a board for mounting electronic parts, there has been used a board shown in FIG.
As shown in FIG. 4, the electronic component mounting portion 90 has a laminated body 99 in which a plurality of insulating base materials 91, 92, 93 are laminated.
There is a multilayer substrate 9 for mounting electronic parts, which is provided with a heat dissipation hole 919 in the lower part of the. The electronic component mounting multilayer substrate 9 has a through hole 95 penetrating the laminated body 99, a wiring circuit pattern 1, and a bonding pad 11.
【０００３】上記貫通穴９５の内壁は，金属メッキ膜３
及びニッケル金メッキ膜４により被覆されている。上記
ボンディングパッド１１は，電子部品搭載部９０の周囲
に形成されており，ニッケル金メッキ膜４により被覆さ
れている。上記放熱穴９１９の内壁は，金属膜１０及び
ニッケル金メッキ膜４により被覆されている。上記積層
体９９の外表面に形成された配線回路パターン１は，金
属メッキ膜３及びニッケル金メッキ膜４により被覆され
ている。The inner wall of the through hole 95 has a metal plating film 3
And a nickel-gold plated film 4. The bonding pad 11 is formed around the electronic component mounting portion 90 and is covered with the nickel gold plating film 4. The inner wall of the heat dissipation hole 919 is covered with the metal film 10 and the nickel-gold plated film 4. The wiring circuit pattern 1 formed on the outer surface of the laminated body 99 is covered with a metal plating film 3 and a nickel gold plating film 4.
【０００４】上記絶縁基材９１〜９３は，レジスト膜２
及び接着材６により接合されている。上記電子部品搭載
部９０は，絶縁基材９２，９３に穿設された搭載用開口
部９２０，９３０により囲まれている。電子部品搭載部
９０には，電子部品８２が搭載される。該電子部品８２
は，ワイヤー８３を介して，上記ボンディングパッド１
１と電気的に接続される。上記貫通穴９５内には，リー
ドピンが挿着される。The insulating base materials 91 to 93 are formed of the resist film 2
And are bonded by an adhesive material 6. The electronic component mounting portion 90 is surrounded by mounting openings 920 and 930 formed in insulating base materials 92 and 93. An electronic component 82 is mounted on the electronic component mounting portion 90. The electronic component 82
Is bonded to the bonding pad 1 through the wire 83.
1 is electrically connected. Lead pins are inserted into the through holes 95.
【０００５】次に，従来にかかる，上記電子部品搭載用
多層基板９の製造方法について説明する。まず，図１８
に示すごとく，最上層としての絶縁基材９３の表側面
を，銅材１２により被覆する。次いで，絶縁基材９３に
搭載用開口部９３０を穿設する。次に，図１９に示すご
とく，中間層としての絶縁基材９２に，銅材からなる配
線回路パターン１及びボンディングパッド１１と，搭載
用開口部９２０とを形成する。次いで，上記ボンディン
グパッド１１の表面には無電解銅メッキ膜５を，上記配
線回路パターン１の表面にはレジスト膜２を施す。Next, a conventional method for manufacturing the electronic component mounting multilayer substrate 9 will be described. First, FIG.
As shown in FIG. 3, the upper surface of the insulating base material 93 is covered with the copper material 12. Next, a mounting opening 930 is formed in the insulating base material 93. Next, as shown in FIG. 19, the wiring circuit pattern 1 and the bonding pad 11 made of a copper material and the mounting opening 920 are formed on the insulating base material 92 as an intermediate layer. Then, the electroless copper plating film 5 is applied to the surface of the bonding pad 11, and the resist film 2 is applied to the surface of the wiring circuit pattern 1.
【０００６】次に，図２０に示すごとく，最下層として
の絶縁基材９１の裏側面を，銅材１２により被覆する。
次いで，上記絶縁基材９１に放熱穴９１９を穿設する。
次いで，上記絶縁基材９１の表側面には配線回路パター
ン１を，上記放熱穴９１９の内壁には金属膜１０を形成
する。上記配線回路パターン１及び金属膜１０は，ニッ
ケル金メッキ膜からなる。次いで，上記配線回路パター
ン１の表面を，レジスト膜２により被覆する。Next, as shown in FIG. 20, the back side surface of the insulating base material 91 as the lowermost layer is covered with the copper material 12.
Next, a heat dissipation hole 919 is formed in the insulating base material 91.
Next, the wiring circuit pattern 1 is formed on the front surface of the insulating base material 91, and the metal film 10 is formed on the inner wall of the heat dissipation hole 919. The wiring circuit pattern 1 and the metal film 10 are made of nickel-gold plated film. Next, the surface of the wiring circuit pattern 1 is covered with a resist film 2.
【０００７】次に，図２１に示すごとく，接着材６を用
いて，上記絶縁基材９１，９２，９３を積層接合し，積
層体９９を形成する。次に，図２２に示すごとく，上記
積層体９９に，貫通穴９５を穿設する。次いで，該貫通
穴９５及び放熱穴９１９の内壁を含む積層体９９の全表
面を，金属メッキ膜３により被覆する。Next, as shown in FIG. 21, the insulating base materials 91, 92 and 93 are laminated and bonded using an adhesive material 6 to form a laminated body 99. Next, as shown in FIG. 22, through holes 95 are formed in the laminated body 99. Then, the entire surface of the laminated body 99 including the through holes 95 and the inner walls of the heat dissipation holes 919 is covered with the metal plating film 3.
【０００８】次に，図２３に示すごとく，積層体９９の
外表面を被覆する銅材及び金属メッキ膜３を露光，エッ
チング処理して，配線回路パターン１を形成する。ま
た，ボンディングパッド１１及び金属膜１０を覆う金属
メッキ膜３を，エッチング処理により除去する。次い
で，上記ボンディングパッド１１及び金属膜１０の表面
に，無電解銅メッキ膜５を施す。次に，上記無電解銅メ
ッキ膜５及び金属メッキ膜３の表面を，再度ニッケル金
メッキ膜４により被覆する。これにより，上記従来の電
子部品搭載用多層基板９が得られる。Next, as shown in FIG. 23, the copper material and the metal plating film 3 for covering the outer surface of the laminate 99 are exposed and etched to form the wiring circuit pattern 1. Further, the metal plating film 3 covering the bonding pad 11 and the metal film 10 is removed by etching. Then, the electroless copper plating film 5 is applied to the surfaces of the bonding pad 11 and the metal film 10. Next, the surfaces of the electroless copper plating film 5 and the metal plating film 3 are coated again with the nickel gold plating film 4. As a result, the conventional multilayer board 9 for mounting electronic parts is obtained.
【０００９】上記電子部品搭載用多層基板９において
は，外表面に形成された配線回路パターン１，ボンディ
ングパッド１１，貫通穴９５，及び放熱穴９１９が，ニ
ッケル金メッキ膜４により被覆されているため，耐錆性
に優れている。また，複数の絶縁基材９１〜９３が積層
されているため，高密度に配線回路パターン１を形成す
ることができる。In the above-mentioned electronic component mounting multilayer substrate 9, the wiring circuit pattern 1, the bonding pad 11, the through hole 95, and the heat dissipation hole 919 formed on the outer surface are covered with the nickel gold plating film 4. Has excellent rust resistance. Moreover, since the plurality of insulating base materials 91 to 93 are laminated, the wiring circuit pattern 1 can be formed with high density.
【００１０】[0010]
【解決しようとする課題】しかしながら，上記従来の電
子部品搭載用多層基板の製造方法においては，図２２，
図２３に示すごとく，電子部品搭載部９０の周囲，ボン
ディングパッド１１，及び放熱穴９１９を覆う金属メッ
キ膜３を，エッチング処理により除去する際に，上記ボ
ンディングパッド１１及び金属膜１０の表面が，損傷を
受ける。However, in the conventional method for manufacturing a multilayer substrate for mounting electronic components described above, the method shown in FIG.
As shown in FIG. 23, when the metal plating film 3 covering the electronic component mounting portion 90, the bonding pad 11, and the heat dissipation hole 919 is removed by etching, the surfaces of the bonding pad 11 and the metal film 10 are Get damaged.
【００１１】そのため，ボンディングパッド１１と接続
している配線回路パターン１と電子部品８２との電気的
接続性が悪化する。また，金属膜１０が損傷を受けた場
合には，電子部品８２から発せられる熱を外方に効率良
く放散させることができない。本発明はかかる従来の問
題点に鑑み，電子部品搭載部の周囲，ボンディングパッ
ド，及び放熱穴に損傷を与えることがない，電子部品搭
載用多層基板の製造方法を提供しようとするものであ
る。Therefore, the electrical connectivity between the wiring circuit pattern 1 connected to the bonding pad 11 and the electronic component 82 deteriorates. Further, when the metal film 10 is damaged, the heat generated from the electronic component 82 cannot be efficiently dissipated to the outside. In view of the above conventional problems, the present invention aims to provide a method of manufacturing a multilayer substrate for mounting electronic components without damaging the periphery of the electronic component mounting portion, the bonding pad, and the heat dissipation hole.
【００１２】[0012]
【課題の解決手段】本発明は，複数の絶縁基材を積層し
てなると共に，電子部品搭載部の下部には放熱穴を設け
てなる電子部品搭載用多層基板の製造方法において，
（ａ）予め配線回路パターンと放熱穴とを形成すると共
に，上記放熱穴に金属膜を施した最下層の絶縁基材を準
備し，（ｂ）上記最下層の絶縁基材の少なくとも上側
に，更に予め配線回路パターンを形成してあると共に電
子部品搭載用の搭載用開口部を有する絶縁基材を，１枚
又は複数枚積層接合して積層体を形成し，（ｃ）上記積
層体に，該積層体を貫通する貫通穴を穿設し，（ｄ）上
記搭載用開口部及び放熱穴をそれぞれ閉塞部材により閉
塞し，（ｅ）上記貫通穴の内部に第一金属メッキ膜を形
成し，（ｆ）その後，上記搭載用開口部及び放熱穴から
上記閉塞部材を除去することを特徴とする電子部品搭載
用多層基板の製造方法にある（第１製造方法）。According to the present invention, there is provided a method of manufacturing a multilayer substrate for mounting electronic components, which comprises a plurality of insulating base materials laminated and a heat dissipation hole is provided in a lower portion of the electronic component mounting portion.
(A) A wiring circuit pattern and a heat dissipation hole are formed in advance, and a lowermost insulating base material in which the heat dissipation hole is provided with a metal film is prepared. (B) At least an upper side of the lowermost insulating base material, Further, one or more insulating base materials having a wiring circuit pattern formed thereon and having a mounting opening for mounting electronic parts are laminated and joined to form a laminated body, and (c) the laminated body, Forming a through hole penetrating the laminated body, (d) closing the mounting opening and the heat radiating hole with respective closing members, and (e) forming a first metal plating film inside the through hole, (F) After that, in the method of manufacturing a multilayer substrate for mounting electronic components, the blocking member is removed from the mounting opening and the heat dissipation hole (first manufacturing method).
【００１３】本発明において最も注目すべきことは，搭
載用開口部及び放熱穴をそれぞれ閉塞部材により閉塞し
た後にメッキ処理を行って，貫通穴内を金属メッキ膜に
より被覆していることである。What is most noticeable in the present invention is that the mounting opening and the heat dissipation hole are each closed by a closing member, and a plating process is performed to cover the inside of the through hole with a metal plating film.
【００１４】上記放熱穴には，金属膜が形成されてい
る。また，上記放熱穴には，放熱材としての放熱板を配
置してもよい。これにより，電子部品搭載用多層基板の
放熱性が更に向上する。上記放熱穴は，最下層の絶縁基
材に，１又は複数個形成される。上記放熱穴の穴径は，
０．１〜３０ｍｍであることが好ましい。０．１ｍｍ未
満では，機械的に開口部を形成するのが困難である。一
方，３０ｍｍを越える場合には，電子部品搭載用多層基
板自体の強度が低下するおそれがある。A metal film is formed in the heat dissipation hole. Further, a heat dissipation plate as a heat dissipation material may be arranged in the heat dissipation hole. As a result, the heat dissipation of the electronic component mounting multilayer substrate is further improved. One or a plurality of the heat dissipation holes are formed in the lowermost insulating base material. The hole diameter of the heat dissipation hole is
It is preferably 0.1 to 30 mm. If it is less than 0.1 mm, it is difficult to mechanically form the opening. On the other hand, when the thickness exceeds 30 mm, the strength of the electronic component mounting multilayer substrate itself may decrease.
【００１５】上記複数枚の絶縁基材は，プリプレグ等の
接着材により接合され，積層体を形成する。上記第一金
属メッキ膜は，銅，アルミ等を用いる。上記配線回路パ
ターンは，銅，アルミ等を用いる。上記絶縁基材は，ガ
ラスエポキシ基板，ガラスポリイミド基板，ガラストリ
アジン基板等を用いる。上記閉塞部材としては，例え
ば，感光性ドライフィルム等を用いる。上記貫通穴内に
は，例えばリードピンが挿着される。The plurality of insulating base materials are joined by an adhesive such as prepreg to form a laminated body. Copper, aluminum or the like is used for the first metal plating film. Copper, aluminum or the like is used for the wiring circuit pattern. As the insulating base material, a glass epoxy substrate, a glass polyimide substrate, a glass triazine substrate, or the like is used. As the closing member, for example, a photosensitive dry film or the like is used. A lead pin, for example, is inserted into the through hole.
【００１６】また，上記製造方法においては，上記閉塞
部材を除去した後，貫通穴の内部，放熱穴及び搭載用開
口部の周囲の配線回路パターンに第二金属メッキ膜を施
すことが好ましい。これにより，貫通穴の内部，放熱穴
及び配線回路パターンに耐錆性を付与することができ
る。Further, in the above manufacturing method, it is preferable that after the blocking member is removed, a second metal plating film is applied to the inside of the through hole, the heat radiation hole and the wiring circuit pattern around the mounting opening. As a result, rust resistance can be imparted to the inside of the through hole, the heat dissipation hole, and the wiring circuit pattern.
【００１７】上記第二金属メッキ膜は，例えば，電気メ
ッキ法により形成される。該電気メッキ法は，配線回路
パターン，ボンディングパッド，金属膜，及び金属メッ
キ膜からなる導電材を帯電させた状態で，積層体をメッ
キ液に浸漬し，これらの導電材の表面にのみ上記第二金
属メッキ膜を形成させる方法である。上記電気メッキ法
によれば，上記導電材以外に第二金属メッキ膜が形成さ
れることがないため，エッチング処理が不要となる。上
記第二金属メッキ膜は，ニッケルメッキ又は金メッキの
単体膜，或いはニッケルメッキ及び金メッキの複合膜等
である。The second metal plating film is formed by, for example, an electroplating method. In the electroplating method, the laminated body is immersed in a plating solution in a state where a conductive material composed of a wiring circuit pattern, a bonding pad, a metal film, and a metal plating film is charged, and only the surface of these conductive materials is subjected to the above This is a method of forming a bimetallic plating film. According to the electroplating method, the second metal plating film is not formed except for the conductive material, so that the etching process is unnecessary. The second metal plating film is a single film of nickel plating or gold plating, or a composite film of nickel plating and gold plating.
【００１８】また，他の製造方法としては，複数の絶縁
基材を積層してなると共に，電子部品搭載部の下部には
放熱穴を設けてなる電子部品搭載用多層基板の製造方法
において，（ａ）予め配線回路パターンと放熱穴とを形
成すると共に，上記放熱穴に金属膜を施した最下層の絶
縁基材を準備し，（ｂ）上記最下層の絶縁基材の少なく
とも上側に，更に予め配線回路パターンとを形成してあ
ると共に電子部品搭載用の搭載用開口部を有する絶縁基
材を１枚又は複数枚積層接合して積層体を形成し，
（ｃ）上記積層体に該積層体を貫通する貫通穴を穿設
し，（ｄ）上記放熱穴及び搭載用開口部を含めて上記積
層体の全表面に無電解金属メッキ膜を施し，（ｅ）上記
搭載用開口部及び放熱穴をそれぞれ閉塞部材により閉塞
し，（ｆ）上記貫通穴の内部に第一金属メッキ膜を形成
し，（ｇ）上記搭載用開口部及び放熱穴から上記閉塞部
材を除去し，（ｈ）その後，上記第一金属メッキ膜によ
り被覆されなかった無電解銅メッキ膜を除去することを
特徴とする電子部品搭載用多層基板の製造方法がある
（第２製造方法）。As another manufacturing method, a method for manufacturing a multilayer substrate for mounting electronic parts, which comprises a plurality of insulating base materials laminated and a heat dissipation hole provided under the electronic part mounting portion, a) A wiring circuit pattern and heat dissipation holes are formed in advance, and a metal film is formed in the heat dissipation holes to prepare a lowermost insulating base material, and (b) at least an upper side of the lowermost insulating base material. Forming a wiring circuit pattern in advance and laminating and bonding one or more insulating base materials having mounting openings for mounting electronic components to form a laminated body,
(C) A through hole is formed in the laminated body to penetrate the laminated body, and (d) An electroless metal plating film is applied to the entire surface of the laminated body including the heat dissipation hole and the mounting opening. e) The mounting opening and the heat dissipation hole are respectively closed by a closing member, (f) the first metal plating film is formed inside the through hole, and (g) the mounting opening and the heat dissipation hole are closed. There is a method of manufacturing a multilayer board for mounting electronic parts, characterized in that (h) after that, the member is removed, and then the electroless copper plating film not covered by the first metal plating film is removed (second manufacturing method). ).
【００１９】この第２製造方法によれば上記無電解銅メ
ッキ膜は，例えば，ソフトエッチング等により容易に除
去することができる。そのため，ボンディングパッド，
金属膜，及び配線回路パターンが，損傷及び汚染を受け
ない。上記ソフトエッチング処理は，例えば，硫酸と過
酸化水素水との混合液をスプレー方式により積層体全面
に噴きつけて行われる。また，その他は，前記第１製造
方法と同様である。According to the second manufacturing method, the electroless copper plated film can be easily removed by, for example, soft etching. Therefore, the bonding pad,
The metal film and the wiring circuit pattern are not damaged or contaminated. The soft etching process is performed, for example, by spraying a mixed solution of sulfuric acid and hydrogen peroxide solution onto the entire surface of the laminate by a spray method. Others are the same as the first manufacturing method.
【００２０】[0020]
【作用及び効果】本発明の第１製造方法においては，搭
載用開口部及び放熱穴をそれぞれ閉塞部材により閉塞し
た状態で，貫通穴内に第一金属メッキ膜を形成してい
る。そのため，貫通穴への第一金属メッキ膜形成時に，
この第一金属メッキ膜を必要としない搭載用開口部及び
放熱穴には，第一金属メッキ膜が形成されない。According to the first manufacturing method of the present invention, the first metal plating film is formed in the through hole with the mounting opening and the heat dissipation hole being closed by the closing member. Therefore, when forming the first metal plating film on the through hole,
The first metal plating film is not formed in the mounting opening and the heat dissipation hole that do not require the first metal plating film.
【００２１】また，上記搭載用開口部及び放熱穴が上記
閉塞部材により閉塞される際に，電子部品搭載部の周囲
も閉塞される。そのため，電子部品搭載部内にはメッキ
液が浸入せず，電子部品搭載部の周囲には金属メッキ膜
が形成されない。When the mounting opening and the heat dissipation hole are closed by the closing member, the periphery of the electronic component mounting portion is also closed. Therefore, the plating liquid does not penetrate into the electronic component mounting portion, and the metal plating film is not formed around the electronic component mounting portion.
【００２２】それ故，貫通穴へ第一金属メッキ膜を形成
した後に，電子部品搭載部の周囲，搭載用開口部，及び
放熱穴をエッチングする必要がなく，これらに損傷及び
汚染を与えない。また，エッチング処理を行う必要がな
いため，作業効率が向上する。また，本発明の製造方法
によれば，一般的なプリント基板製造ラインを用いて，
電子部品搭載用多層基板を製造することができる。な
お，上記放熱穴は，電子部品と基板裏側面との間の回路
の導電孔として用いることもできる。Therefore, it is not necessary to etch the periphery of the electronic component mounting portion, the mounting opening, and the heat dissipation hole after forming the first metal plating film in the through hole, and these are not damaged or contaminated. Further, since it is not necessary to perform etching processing, work efficiency is improved. Further, according to the manufacturing method of the present invention, using a general printed circuit board manufacturing line,
A multilayer board for mounting electronic components can be manufactured. The heat dissipation hole can also be used as a conductive hole of a circuit between the electronic component and the back surface of the substrate.
【００２３】また，第２製造方法においては，積層体に
貫通穴を穿設した後に，積層体の全表面及び放熱穴並び
に搭載用開口部に無電解金属メッキを施し，その後にマ
スクフィルム等の閉塞部材を用いている。そのため，上
記閉塞部材は，無電解金属メッキの影響を受けず，様々
な材質，形状，厚みのものを用いることができる。その
他，上記第１製造方法と同様の効果を得ることができ
る。本発明によれば，電子部品搭載部の周囲，ボンディ
ングパッド，及び放熱穴に損傷を与えることがない，電
子部品搭載用多層基板の製造方法を提供することができ
る。In the second manufacturing method, after the through holes are formed in the laminated body, electroless metal plating is applied to the entire surface of the laminated body, the heat dissipation holes and the mounting openings, and then a mask film or the like is formed. A closing member is used. Therefore, the closing member can be made of various materials, shapes and thicknesses without being affected by the electroless metal plating. In addition, the same effect as the first manufacturing method can be obtained. According to the present invention, it is possible to provide a method for manufacturing a multilayer substrate for mounting electronic components without damaging the periphery of the electronic component mounting portion, the bonding pad, and the heat dissipation hole.
【００２４】[0024]
実施例１ 本発明にかかる電子部品搭載用多層基板の製造方法につ
いて，図１〜図１１を用いて説明する。本例の製造方法
により製造される電子部品搭載用多層基板９は，図１に
示すごとく，３枚の絶縁基材９１，９２，９３を積層し
た積層体９９を有すると共に，電子部品搭載部９０の下
部には放熱穴９１１を設けてなる。上記電子部品搭載用
多層基板９は，上記積層体９９を貫通する貫通穴９５
と，配線回路パターン１と，ボンディングパッド１１と
を有している。Example 1 A method for manufacturing a multilayer substrate for mounting electronic components according to the present invention will be described with reference to FIGS. As shown in FIG. 1, an electronic component mounting multilayer substrate 9 manufactured by the manufacturing method of this example has a laminated body 99 in which three insulating base materials 91, 92, 93 are laminated, and an electronic component mounting portion 90. A heat radiation hole 911 is provided in the lower part of the. The electronic component mounting multilayer substrate 9 has through holes 95 penetrating the laminate 99.
It has a wiring circuit pattern 1 and a bonding pad 11.
【００２５】上記貫通穴９５の内壁は，第一金属メッキ
膜３及び第二金属メッキ膜４により被覆されている。第
一金属メッキ膜３としては銅を用いる。第二金属メッキ
膜４としては，ニッケルメッキ又は金メッキの単体膜，
或いは両メッキからなる複合膜等がある。上記ボンディ
ングパッド１１は，電子部品搭載部９０の周囲に形成さ
れており，第二金属メッキ膜４により被覆されている。The inner wall of the through hole 95 is covered with the first metal plating film 3 and the second metal plating film 4. Copper is used as the first metal plating film 3. As the second metal plating film 4, a single film of nickel plating or gold plating,
Alternatively, there is a composite film composed of both platings. The bonding pad 11 is formed around the electronic component mounting portion 90 and is covered with the second metal plating film 4.
【００２６】上記放熱穴９１１の内壁は，金属膜１０及
び第二金属メッキ膜４により被覆されている。上記放熱
穴９１１は，図１１に示すごとく，電子部品搭載部９０
の裏側面に４個形成されている。The inner wall of the heat dissipation hole 911 is covered with the metal film 10 and the second metal plating film 4. As shown in FIG. 11, the heat dissipation hole 911 is provided in the electronic component mounting portion 90.
Four are formed on the back side of the.
【００２７】また，図１に示すごとく，上記積層体９９
の外表面に形成された配線回路パターン１は，第二金属
メッキ膜４により被覆されている。上記絶縁基材９１〜
９３は，レジスト膜２及び接着材６により接合されてい
る。上記電子部品搭載部９０は，上記搭載用開口部９２
０，９３０により囲まれている。電子部品搭載部９０に
は，絶縁基材９１の表側面に形成された搭載用パッド８
４の上に，電子部品８２が搭載される。該電子部品８２
は，ワイヤー８３により，電子部品搭載部９０の周囲に
形成されたボンディングパッド１１と電気的に接続され
る。Further, as shown in FIG.
The wiring circuit pattern 1 formed on the outer surface of is covered with the second metal plating film 4. The insulating base material 91 to
93 is joined by the resist film 2 and the adhesive material 6. The electronic component mounting portion 90 has the mounting opening 92.
It is surrounded by 0,930. The electronic component mounting portion 90 includes a mounting pad 8 formed on the front surface of the insulating base material 91.
An electronic component 82 is mounted on the board 4. The electronic component 82
Is electrically connected to the bonding pad 11 formed around the electronic component mounting portion 90 by the wire 83.
【００２８】次に，上記電子部品搭載用多層基板９の製
造方法について説明する。まず，図２に示すごとく，最
上層としての絶縁基材９３の表側面に，銅からなる配線
回路パターン１を形成する。次いで，絶縁基材９３に搭
載用開口部９３０を穿設する。次に，図３に示すごと
く，中間層としての絶縁基材９２に，銅からなる配線回
路パターン１及びボンディングパッド１１と，搭載用開
口部９２０とを形成する。次いで，上記配線回路パター
ン１の表面に，レジスト膜２を施す。Next, a method of manufacturing the above-mentioned electronic component mounting multilayer substrate 9 will be described. First, as shown in FIG. 2, the wiring circuit pattern 1 made of copper is formed on the front surface of the insulating base material 93 as the uppermost layer. Next, a mounting opening 930 is formed in the insulating base material 93. Next, as shown in FIG. 3, the wiring circuit pattern 1 and the bonding pad 11 made of copper and the mounting opening 920 are formed on the insulating base material 92 as an intermediate layer. Then, a resist film 2 is applied to the surface of the wiring circuit pattern 1.
【００２９】次に，図４に示すごとく，最下層としての
絶縁基材９１に，銅からなる配線回路パターン１を形成
する。次いで，上記絶縁基材９１に放熱穴９１１を穿設
する。次いで，上記放熱穴９１１の内壁を，金属膜１０
により被覆する。次いで，上記絶縁基材９１の表側面に
形成された配線回路パターン１の表面を，レジスト膜２
により被覆する。Next, as shown in FIG. 4, the wiring circuit pattern 1 made of copper is formed on the insulating base material 91 as the lowermost layer. Next, a heat dissipation hole 911 is formed in the insulating base material 91. Then, the inner wall of the heat dissipation hole 911 is covered with the metal film 10.
To coat. Next, the surface of the wiring circuit pattern 1 formed on the front surface of the insulating base material 91 is covered with the resist film 2
To coat.
【００３０】次に，図５に示すごとく，プリプレグ等の
接着材６を用いて，上記絶縁基材９１，９２，９３を積
層接合し，積層体９９を形成する。次に，図６に示すご
とく，上記積層体９９に，該積層体９９を貫通する貫通
穴９５を穿設する。次に，図７に示すごとく，上記積層
体９９の表側面及び裏側面に，フィルム状の閉塞部材７
１，７２を載置する。該閉塞部材７１，７２には，積層
体９９の貫通穴９５と対向する位置に，予め穴部７１
５，７２５が穿設されている。Next, as shown in FIG. 5, the insulating base materials 91, 92, 93 are laminated and bonded using an adhesive 6 such as a prepreg to form a laminated body 99. Next, as shown in FIG. 6, a through hole 95 penetrating the laminated body 99 is formed in the laminated body 99. Next, as shown in FIG. 7, a film-shaped closing member 7 is formed on the front and back surfaces of the laminate 99.
Place 1,72. The closing members 71 and 72 are provided with holes 71 in advance at positions facing the through holes 95 of the laminated body 99.
5,725 are drilled.
【００３１】次に，図８に示すごとく，上記積層体９９
をメッキ液中に浸漬し，上記貫通穴９５の内壁を第一金
属メッキ膜３により被覆する。次に，図９に示すごと
く，上記閉塞部材７１，７２を積層体９９から除去す
る。Next, as shown in FIG.
Is immersed in a plating solution, and the inner wall of the through hole 95 is covered with the first metal plating film 3. Next, as shown in FIG. 9, the closing members 71 and 72 are removed from the laminated body 99.
【００３２】次に，図１０に示すごとく，外方に露出し
ている配線回路パターン１，ボンディングパッド１１，
第一金属メッキ膜３，及び金属膜１０の表面を，第二金
属メッキ膜４により被覆する。該第二金属メッキ膜４
は，ニッケルメッキまたは金メッキの単体膜，或いはニ
ッケルメッキ及び金メッキの複合膜であり，電気メッキ
法により形成される。該電気メッキ法は，配線回路パタ
ーン１，ボンディングパッド１１，金属膜１０，及び第
一金属メッキ膜３からなる導電材を帯電させた状態で，
積層体９９をメッキ液に浸漬し，上記導電材の表面にの
み上記第二金属メッキ膜を形成させる方法である。これ
により，図１に示す上記電子部品搭載用多層基板９が得
られる。Next, as shown in FIG. 10, the exposed wiring circuit pattern 1, the bonding pad 11,
The surfaces of the first metal plating film 3 and the metal film 10 are covered with the second metal plating film 4. The second metal plating film 4
Is a single film of nickel plating or gold plating, or a composite film of nickel plating and gold plating, and is formed by electroplating. In the electroplating method, a conductive material composed of the wiring circuit pattern 1, the bonding pad 11, the metal film 10 and the first metal plating film 3 is charged,
This is a method in which the laminated body 99 is immersed in a plating solution to form the second metal plating film only on the surface of the conductive material. As a result, the above-mentioned electronic component mounting multilayer substrate 9 shown in FIG. 1 is obtained.
【００３３】次に，本例の作用効果について説明する。
本例においては，図８に示すごとく，搭載用開口部９２
０，９３０及び放熱穴９１１を閉塞部材７１，７２によ
り閉塞した状態で，貫通穴９５内に第一金属メッキ膜３
を形成している。そのため，上記搭載用開口部及び放熱
穴には，金属メッキ膜が形成されない。Next, the function and effect of this example will be described.
In this example, as shown in FIG.
0, 930 and the heat dissipation hole 911 are closed by the closing members 71, 72, the first metal plating film 3 is formed in the through hole 95.
Is formed. Therefore, no metal plating film is formed on the mounting opening and the heat dissipation hole.
【００３４】また，上記閉塞部材７１，７２は，上記搭
載用開口部及び放熱穴を閉塞すると同時に，これら開口
部の中に位置する電子部品搭載部の周囲をも閉塞する。
そのため，電子部品搭載部９０の周囲には第一金属メッ
キ膜が形成されない。従って，エッチング処理の必要が
なく，電子部品搭載部９０の周囲，搭載用開口部９２
０，９３０，及び放熱穴９１１は，損傷及び汚染を受け
ない。また，エッチング処理を行う必要がないため，作
業効率が向上する。Further, the closing members 71 and 72 close the mounting opening and the heat dissipation hole, and at the same time, close the periphery of the electronic component mounting portion located in these openings.
Therefore, the first metal plating film is not formed around the electronic component mounting portion 90. Therefore, there is no need for etching processing, and the periphery of the electronic component mounting portion 90 and the mounting opening portion 92 are
The 0, 930 and the heat dissipation holes 911 are not damaged or contaminated. Further, since it is not necessary to perform etching processing, work efficiency is improved.
【００３５】また，上記閉塞部材７１，７２を除去した
後には，貫通穴９５の内壁，放熱穴９１１，及びボンデ
ィングパッド１１に，第二金属メッキ膜４を施してい
る。そのため，貫通穴９５の内部，搭載用開口部９２
０，９３０及びボンディングパッド１１に，耐錆性を付
与することができる。After removing the closing members 71 and 72, the second metal plating film 4 is applied to the inner wall of the through hole 95, the heat dissipation hole 911, and the bonding pad 11. Therefore, the inside of the through hole 95, the mounting opening 92
It is possible to impart rust resistance to the 0, 930 and the bonding pad 11.
【００３６】実施例２ 本例の電子部品搭載用多層基板の製造方法においては，
図１２に示すごとく，貫通穴９５内に，無電解銅メッキ
膜５を形成した後に第一金属メッキ膜３を施している。
以下，上記電子部品搭載用多層基板の製造方法につい
て，図１３〜図１５を用いて説明する。まず，前記実施
例１と同様に３枚の絶縁基材９１〜９３を積層接合し，
積層体９９を得た後，該積層体９９を貫通する貫通穴９
５を穿設する（図６参照）。次に，図１３に示すごと
く，放熱穴９１１及び搭載用開口部９２０，９３０を含
めて，上記積層体９９の全表面に無電解金属メッキ膜５
を施す。Example 2 In the method of manufacturing a multilayer substrate for mounting electronic components of this example,
As shown in FIG. 12, the electroless copper plating film 5 is formed in the through hole 95 and then the first metal plating film 3 is applied.
Hereinafter, a method for manufacturing the above-mentioned electronic component mounting multilayer substrate will be described with reference to FIGS. First, three insulating base materials 91 to 93 are laminated and joined in the same manner as in the first embodiment,
After obtaining the laminated body 99, the through hole 9 penetrating the laminated body 99
5 is drilled (see FIG. 6). Next, as shown in FIG. 13, the electroless metal plating film 5 is formed on the entire surface of the laminated body 99 including the heat dissipation holes 911 and the mounting openings 920 and 930.
Give.
【００３７】次に，図１４に示すごとく，上記搭載用開
口部９２０，９３０及び放熱穴９１１をそれぞれ閉塞部
材７１，７２により閉塞する。該閉塞部材７１，７２に
は，上記積層体９９の貫通穴９５に対向する位置に，予
め穴部７１５，７２５が穿設されている。次いで，上記
積層体９９をメッキ液中に浸漬し，貫通穴９５内の無電
解銅メッキ膜５を第一金属メッキ膜３により被覆する。Next, as shown in FIG. 14, the mounting openings 920 and 930 and the heat radiation hole 911 are closed by the closing members 71 and 72, respectively. Holes 715 and 725 are previously formed in the closing members 71 and 72 at positions facing the through holes 95 of the laminated body 99. Next, the laminate 99 is dipped in a plating solution to cover the electroless copper plating film 5 in the through hole 95 with the first metal plating film 3.
【００３８】次に，図１５に示すごとく，上記閉塞部材
７１，７２を積層体９９から除去する。次いで，上記第
一金属メッキ膜３により覆われていない無電解銅メッキ
膜５を除去する。次に，外方に露出している配線回路パ
ターン１，ボンディングパッド１１，第一金属メッキ膜
３，及び金属膜１０の表面を，第二金属メッキ膜４によ
り被覆する。該第二金属メッキ膜４は，前記実施例１と
同様の電気メッキ法により形成する。これにより，図１
２に示す上記電子部品搭載用多層基板９が得られる。Next, as shown in FIG. 15, the closing members 71 and 72 are removed from the laminated body 99. Then, the electroless copper plating film 5 not covered with the first metal plating film 3 is removed. Next, the exposed surface of the wiring circuit pattern 1, the bonding pad 11, the first metal plating film 3, and the metal film 10 is covered with the second metal plating film 4. The second metal plating film 4 is formed by the same electroplating method as in the first embodiment. As a result,
The multilayer substrate 9 for mounting electronic components shown in 2 is obtained.
【００３９】その他は，前記実施例１と同様である。本
例においては，貫通穴９５内に無電解銅メッキ膜５を施
した後に，第一金属メッキ膜３を形成している。そのた
め，上記閉塞部材として様々な性質，形状，厚みのもの
を用いることができる。また，本発明の製造方法によれ
ば，一般的なプリント基板製造ラインを用いて，電子部
品搭載用多層基板を製造することができる。その他は，
前記実施例１と同様の効果を得ることができる。Others are the same as in the first embodiment. In this example, the first metal plating film 3 is formed after the electroless copper plating film 5 is formed in the through hole 95. Therefore, various materials, shapes, and thicknesses can be used as the closing member. Further, according to the manufacturing method of the present invention, it is possible to manufacture a multilayer board for mounting electronic components using a general printed board manufacturing line. Others,
The same effect as that of the first embodiment can be obtained.
【００４０】実施例３ 本例の電子部品搭載用多層基板においては，図１６，図
１７に示すごとく，電子部品搭載部９０の下方に，前記
実施例１よりも多数の放熱穴９１２を有している。ま
た，図１６に示すごとく，該放熱穴９１２の裏側面に
は，放熱材としての放熱板８１が接合されている。Embodiment 3 As shown in FIGS. 16 and 17, the multilayer board for mounting electronic components of this embodiment has a larger number of heat radiation holes 912 below the electronic component mounting portion 90 as compared with Embodiment 1. ing. Further, as shown in FIG. 16, a heat dissipation plate 81 as a heat dissipation material is joined to the back side surface of the heat dissipation hole 912.
【００４１】その他は，前記実施例１と同様である。本
例の電子部品搭載用多層基板は，多数の放熱穴９１２と
放熱板８１とを設けている。そのため，上記実施例１の
電子部品搭載用多層基板よりも放熱性に優れている。そ
の他は，前記実施例１と同様の効果を得ることができ
る。Others are the same as in the first embodiment. The multilayer board for mounting electronic components of this example is provided with a large number of heat dissipation holes 912 and heat dissipation plates 81. Therefore, it is more excellent in heat dissipation than the electronic component mounting multilayer substrate of the first embodiment. Other than that, the same effects as those of the first embodiment can be obtained.
【図１】実施例１の電子部品搭載用多層基板の断面図。FIG. 1 is a cross-sectional view of a multilayer substrate for mounting electronic components according to a first embodiment.
【図２】実施例１における，積層前の，最上層としての
絶縁基材の断面図。FIG. 2 is a cross-sectional view of an insulating base material as the uppermost layer before stacking in Example 1.
【図３】実施例１における，積層前の，中間層としての
絶縁基材の断面図。FIG. 3 is a cross-sectional view of an insulating base material as an intermediate layer before stacking in Example 1.
【図４】実施例１における，積層前の，最下層としての
絶縁基材の断面図。FIG. 4 is a cross-sectional view of an insulating base material as a lowermost layer before stacking in Example 1.
【図５】実施例１の積層体の断面図。5 is a cross-sectional view of the laminated body of Example 1. FIG.
【図６】実施例１における，貫通穴を穿設した積層体の
断面図。FIG. 6 is a cross-sectional view of a laminated body in which a through hole is formed in Example 1.
【図７】実施例１における，閉塞部材が載置された積層
体の断面図。FIG. 7 is a cross-sectional view of a laminated body on which a closing member is placed according to the first embodiment.
【図８】実施例１における，貫通穴内に第一金属メッキ
膜が施された積層体の断面図。FIG. 8 is a cross-sectional view of a laminated body in which a first metal plating film is applied in the through holes in the first embodiment.
【図９】実施例１における，閉塞部材が除去された積層
体の断面図。FIG. 9 is a cross-sectional view of the laminated body in Example 1 in which the blocking member is removed.
【図１０】実施例１における，第二金属メッキ膜が施さ
れた積層体の断面図。FIG. 10 is a cross-sectional view of a laminated body provided with a second metal plating film in Example 1.
【図１１】実施例１における，放熱穴の穿設位置を示す
説明図。FIG. 11 is an explanatory diagram showing the positions where the heat dissipation holes are formed in the first embodiment.
【図１２】実施例２の電子部品搭載用多層基板の断面
図。FIG. 12 is a cross-sectional view of a multilayer substrate for mounting electronic components according to a second embodiment.
【図１３】実施例２における，無電解銅メッキ膜が施さ
れた積層体の断面図。FIG. 13 is a cross-sectional view of a laminated body provided with an electroless copper plating film in Example 2.
【図１４】実施例２における，閉塞部材が載置され，貫
通穴内に金属メッキ膜が施された積層体の断面図。FIG. 14 is a cross-sectional view of a laminated body in which a blocking member is placed and a metal plating film is provided in a through hole according to the second embodiment.
【図１５】実施例２における，閉塞部材が除去された積
層体の断面図。FIG. 15 is a cross-sectional view of the laminated body in Example 2 in which the closing member is removed.
【図１６】実施例３の電子部品搭載用多層基板の要部断
面図。FIG. 16 is a cross-sectional view of essential parts of a multilayer substrate for mounting electronic components according to a third embodiment.
【図１７】実施例３における，放熱穴の穿設位置を示す
説明図。FIG. 17 is an explanatory diagram showing the positions where the heat dissipation holes are formed in the third embodiment.
【図１８】従来例における，積層前の，最上層としての
絶縁基材の断面図。FIG. 18 is a cross-sectional view of an insulating base material as the uppermost layer before stacking in a conventional example.
【図１９】従来例における，積層前の，中間層としての
絶縁基材の断面図。FIG. 19 is a cross-sectional view of an insulating base material as an intermediate layer before stacking in a conventional example.
【図２０】従来例における，積層前の，最下層としての
絶縁基材の断面図。FIG. 20 is a cross-sectional view of an insulating base material as a lowermost layer before stacking in a conventional example.
【図２１】従来例の積層体の断面図。FIG. 21 is a sectional view of a conventional laminated body.
【図２２】従来例における，貫通穴を穿設し，全表面に
第一金属メッキ膜が施された積層体の断面図。FIG. 22 is a cross-sectional view of a laminate in which a through hole is formed and a first metal plating film is applied to the entire surface in a conventional example.
【図２３】従来例における，不要な部分の第一金属メッ
キ膜が除去された積層体の断面図。FIG. 23 is a cross-sectional view of a laminated body in which an unnecessary portion of the first metal plating film is removed in the conventional example.
【図２４】従来例の電子部品搭載用多層基板の断面図。FIG. 24 is a cross-sectional view of a conventional multilayer electronic component mounting board.
１．．．配線回路パターン， １０．．．金属膜， １１．．．ボンディングパッド， ３．．．第一金属メッキ膜， ４．．．第二金属メッキ膜， ５．．．無電解銅メッキ膜， ７１，７２．．．閉塞部材， ８１．．．放熱板， ８２．．．電子部品， ９．．．電子部品搭載用多層基板， ９０．．．電子部品搭載部， ９１，９２，９３．．．絶縁基材， ９１１，９１２．．．放熱穴， ９２０，９３０．．．搭載用開口部， ９５．．．貫通穴， ９９．．．積層体， 1. ． ． Wiring circuit pattern, 10. ． ． Metal film, 11. ． ． Bonding pad, 3. ． ． First metal plating film, 4. ． ． Second metal plating film, 5. ． ． Electroless copper plating film, 71, 72. ． ． Closure member, 81. ． ． Heat sink, 82. ． ． Electronic components, 9. ． ． Multi-layer substrate for mounting electronic components, 90. ． ． Electronic component mounting part, 91, 92, 93. ． ． Insulating base material, 911, 912. ． ． Heat dissipation hole, 920, 930. ． ． Mounting opening, 95. ． ． Through hole, 99. ． ． Laminate,
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０５Ｋ 3/24 Ａ 7511−4Ｅ 3/42 Ｂ 7511−4Ｅ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI Technical display location H05K 3/24 A 7511-4E 3/42 B 7511-4E
Claims (14)
電子部品搭載部の下部には放熱穴を設けてなる電子部品
搭載用多層基板の製造方法において，（ａ）予め配線回
路パターンと放熱穴とを形成すると共に，上記放熱穴に
金属膜を施した最下層の絶縁基材を準備し，（ｂ）上記
最下層の絶縁基材の少なくとも上側に，更に予め配線回
路パターンを形成してあると共に電子部品搭載用の搭載
用開口部を有する絶縁基材を，１枚又は複数枚積層接合
して積層体を形成し，（ｃ）上記積層体に，該積層体を
貫通する貫通穴を穿設し，（ｄ）上記搭載用開口部及び
放熱穴をそれぞれ閉塞部材により閉塞し，（ｅ）上記貫
通穴の内部に第一金属メッキ膜を形成し，（ｆ）その
後，上記搭載用開口部及び放熱穴から上記閉塞部材を除
去することを特徴とする電子部品搭載用多層基板の製造
方法。1. A laminate of a plurality of insulating base materials,
In a method of manufacturing a multilayer substrate for mounting electronic components, in which a thermal radiation hole is provided below an electronic component mounting portion, (a) a wiring circuit pattern and a thermal radiation hole are formed in advance, and a metal film is applied to the thermal radiation hole. An insulating base material for the lowermost layer is prepared, and (b) an insulating base material having a wiring circuit pattern previously formed on at least an upper side of the insulating base material for the lowermost layer and having a mounting opening for mounting an electronic component. To form a laminated body by laminating one or a plurality of laminated bodies, (c) a through hole penetrating the laminated body, and (d) the mounting opening and the heat dissipation hole. Each of them is closed by a closing member, (e) a first metal plating film is formed inside the through hole, and (f) after that, the closing member is removed from the mounting opening and the heat dissipation hole. Manufacturing method of multilayer board for mounting electronic parts.
した後，上記貫通穴及び放熱穴の内部，並びに外方に露
出した配線回路パターンの表面に，第二金属メッキ膜を
施すことを特徴とする電子部品搭載用多層基板の製造方
法。2. The second metal plating film according to claim 1, wherein after the blocking member is removed, a second metal plating film is applied to the inside of the through hole and the heat dissipation hole and the surface of the wiring circuit pattern exposed to the outside. And a method for manufacturing a multilayer substrate for mounting electronic components.
膜は，ニッケルメッキ又は金メッキの単体膜，或いはニ
ッケルメッキ及び金メッキの複合膜であることを特徴と
する電子部品搭載用多層基板の製造方法。3. The method of manufacturing a multilayer substrate for mounting electronic components according to claim 2, wherein the second metal plating film is a single film of nickel plating or gold plating, or a composite film of nickel plating and gold plating. .
下層の絶縁基材は複数個の放熱穴を有することを特徴と
する電子部品搭載用多層基板の製造方法。4. The method for manufacturing an electronic component mounting multilayer substrate according to claim 1, wherein the insulating base material of the lowermost layer has a plurality of heat dissipation holes.
記放熱穴の穴径は，０．１〜３０ｍｍであることを特徴
とする電子部品搭載用多層基板の製造方法。5. The method of manufacturing a multilayer substrate for mounting electronic components according to claim 1, wherein the heat dissipation hole has a hole diameter of 0.1 to 30 mm.
記放熱穴には，放熱板が配置されていることを特徴とす
る電子部品搭載用多層基板の製造方法。6. The method for manufacturing a multilayer substrate for mounting electronic parts according to claim 1, wherein a heat dissipation plate is arranged in the heat dissipation hole.
記第一金属メッキ膜は，銅であることを特徴とする電子
部品搭載用多層基板の製造方法。7. The method for manufacturing a multi-layer substrate for mounting electronic components according to claim 1, wherein the first metal plating film is copper.
電子部品搭載部の下部には放熱穴を設けてなる電子部品
搭載用多層基板の製造方法において，（ａ）予め配線回
路パターンと放熱穴とを形成すると共に，上記放熱穴に
金属膜を施した最下層の絶縁基材を準備し，（ｂ）上記
最下層の絶縁基材の少なくとも上側に，更に予め配線回
路パターンを形成してあると共に電子部品搭載用の搭載
用開口部を有する絶縁基材を１枚又は複数枚積層接合し
て積層体を形成し，（ｃ）上記積層体に該積層体を貫通
する貫通穴を穿設し，（ｄ）上記放熱穴及び搭載用開口
部を含めて上記積層体の全表面に無電解金属メッキ膜を
施し，（ｅ）上記搭載用開口部及び放熱穴をそれぞれ閉
塞部材により閉塞し，（ｆ）上記貫通穴の内部に第一金
属メッキ膜を形成し，（ｇ）上記搭載用開口部及び放熱
穴から上記閉塞部材を除去し，（ｈ）その後，上記第一
金属メッキ膜により被覆されなかった無電解銅メッキ膜
を除去することを特徴とする電子部品搭載用多層基板の
製造方法。8. A laminate of a plurality of insulating base materials,
In a method of manufacturing a multilayer substrate for mounting electronic components, in which a thermal radiation hole is provided below an electronic component mounting portion, (a) a wiring circuit pattern and a thermal radiation hole are formed in advance, and a metal film is applied to the thermal radiation hole. An insulating base material for the lowermost layer is prepared, and (b) an insulating base material having a wiring circuit pattern previously formed on at least an upper side of the insulating base material for the lowermost layer and having a mounting opening for mounting an electronic component. To form a laminated body by laminating one or a plurality of the above, and (c) forming a through hole through the laminated body in the laminated body, and (d) including the heat dissipation hole and the mounting opening. An electroless metal plating film is applied to the entire surface of the laminate, (e) the mounting opening and the heat dissipation hole are each closed by a closing member, and (f) a first metal plating film is formed inside the through hole. (G) From the mounting opening and the heat dissipation hole to the closed part Removed, (h) Thereafter, the electronic component manufacturing method of mounting the multilayer substrate, and removing the electroless copper plating film not covered by said first metal plating film.
した後，上記貫通穴及び放熱穴の内部，並びに外方に露
出した配線回路パターンの表面に，第二金属メッキ膜を
施すことを特徴とする電子部品搭載用多層基板の製造方
法。9. The method according to claim 8, wherein after the blocking member is removed, a second metal plating film is applied to the inside of the through hole and the heat dissipation hole and the surface of the wiring circuit pattern exposed to the outside. And a method for manufacturing a multilayer substrate for mounting electronic components.
キ膜は，ニッケルメッキ又は金メッキの単体膜，或いは
ニッケルメッキ及び金メッキの複合膜であることを特徴
とする電子部品搭載用多層基板の製造方法。10. The method of manufacturing a multilayer substrate for mounting electronic parts according to claim 9, wherein the second metal plating film is a single film of nickel plating or gold plating, or a composite film of nickel plating and gold plating. .
記最下層の絶縁基材は複数個の放熱穴を有することを特
徴とする電子部品搭載用多層基板の製造方法。11. The method for manufacturing an electronic component mounting multilayer substrate according to claim 8, 9 or 10, wherein the lowermost insulating base material has a plurality of heat dissipation holes.
て，上記放熱穴の穴径は，０．１〜３０ｍｍであること
を特徴とする電子部品搭載用多層基板の製造方法。12. The method for manufacturing a multilayer substrate for mounting electronic components according to claim 8, wherein the heat dissipation hole has a hole diameter of 0.1 to 30 mm.
て，上記放熱穴には，放熱板が配置されていることを特
徴とする電子部品搭載用多層基板の製造方法。13. The method of manufacturing a multilayer substrate for mounting electronic parts according to claim 8, wherein a heat dissipation plate is arranged in the heat dissipation hole.
て，上記金属メッキ膜は，銅であることを特徴とする電
子部品搭載用多層基板の製造方法。14. The method of manufacturing a multilayer substrate for mounting electronic components according to claim 8, wherein the metal plating film is copper.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26422393A JP3598525B2 (en) | 1993-09-27 | 1993-09-27 | Method of manufacturing multilayer board for mounting electronic components |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26422393A JP3598525B2 (en) | 1993-09-27 | 1993-09-27 | Method of manufacturing multilayer board for mounting electronic components |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0799391A true JPH0799391A (en) | 1995-04-11 |
| JP3598525B2 JP3598525B2 (en) | 2004-12-08 |
Family
ID=17400212
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26422393A Expired - Fee Related JP3598525B2 (en) | 1993-09-27 | 1993-09-27 | Method of manufacturing multilayer board for mounting electronic components |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3598525B2 (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6005289A (en) * | 1996-03-28 | 1999-12-21 | Mitsubishi Denki Kabushiki Kaisha | Package for semiconductor device laminated printed circuit boards |
| WO2010035866A1 (en) * | 2008-09-29 | 2010-04-01 | 日立化成工業株式会社 | Package substrate for mounting semiconductor element and method for manufacturing the package substrate |
| CN101937855A (en) * | 2010-08-10 | 2011-01-05 | 日月光半导体制造股份有限公司 | Manufacture method for buried capsulation structure of component and capsulation structure thereof |
| US8284561B2 (en) | 2010-08-05 | 2012-10-09 | Advanced Semiconductor Engineering, Inc. | Embedded component package structure |
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1993
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6005289A (en) * | 1996-03-28 | 1999-12-21 | Mitsubishi Denki Kabushiki Kaisha | Package for semiconductor device laminated printed circuit boards |
| US6256875B1 (en) | 1996-03-28 | 2001-07-10 | Mitsubishi Denki Kabushiki Kaisha | Method for manufacturing semiconductor device |
| US8633393B2 (en) | 2007-12-14 | 2014-01-21 | Huawei Technologies Co., Ltd. | Printed circuit board, manufacturing method thereof and radio-frequency device |
| WO2010035866A1 (en) * | 2008-09-29 | 2010-04-01 | 日立化成工業株式会社 | Package substrate for mounting semiconductor element and method for manufacturing the package substrate |
| KR101143042B1 (en) * | 2008-09-29 | 2012-05-08 | 히다치 가세고교 가부시끼가이샤 | Package substrate for mounting semiconductor element and method for manufacturing the package substrate |
| US8284561B2 (en) | 2010-08-05 | 2012-10-09 | Advanced Semiconductor Engineering, Inc. | Embedded component package structure |
| CN101937855A (en) * | 2010-08-10 | 2011-01-05 | 日月光半导体制造股份有限公司 | Manufacture method for buried capsulation structure of component and capsulation structure thereof |
| JP2015012281A (en) * | 2013-07-02 | 2015-01-19 | 富士通株式会社 | Laminated substrate |
| JP2021507485A (en) * | 2017-12-25 | 2021-02-22 | 華域視覚科技（上海）有限公司Ｈａｓｃｏ Ｖｉｓｉｏｎ Ｔｅｃｈｎｏｌｏｇｙ Ｃｏ．， Ｌｔｄ． | Vehicle Light Reflective LED Module System and Vehicle Light Assembly |
| CN112492777A (en) * | 2019-09-12 | 2021-03-12 | 宏启胜精密电子(秦皇岛)有限公司 | Circuit board and manufacturing method thereof |
| CN112492777B (en) * | 2019-09-12 | 2022-05-27 | 宏启胜精密电子(秦皇岛)有限公司 | Circuit board and manufacturing method thereof |
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| Publication number | Publication date |
|---|---|
| JP3598525B2 (en) | 2004-12-08 |
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