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JPH0799521A - Burst signal detection circuit - Google Patents

Burst signal detection circuit

Info

Publication number
JPH0799521A
JPH0799521A JP26313193A JP26313193A JPH0799521A JP H0799521 A JPH0799521 A JP H0799521A JP 26313193 A JP26313193 A JP 26313193A JP 26313193 A JP26313193 A JP 26313193A JP H0799521 A JPH0799521 A JP H0799521A
Authority
JP
Japan
Prior art keywords
circuit
signal
burst
detection
inputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP26313193A
Other languages
Japanese (ja)
Other versions
JP3223402B2 (en
Inventor
Yoichi Matsumoto
洋一 松本
Shuji Kubota
周治 久保田
Shuzo Kato
修三 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP26313193A priority Critical patent/JP3223402B2/en
Publication of JPH0799521A publication Critical patent/JPH0799521A/en
Application granted granted Critical
Publication of JP3223402B2 publication Critical patent/JP3223402B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE:To reduce mis-detection by simply forming the burst detection circuit employing a digital circuit by using phase information so as to detect a burst signal. CONSTITUTION:A base band signal separated into I and Q channels at an orthogonal detection circuit is inputted to a ROM into which phase information is written, and a reception modulation wave phase signal from the ROM is inputted to difference circuits 10-1, 10-2. Then outputs are inputted to an adder circuit 40 and a delay circuit 30, their outputs are added and the sum is given to an absolute value circuit 50, the absolute value obtained therefrom is inputted to an accumulation circuit 60, in which the accumulation value over a predetermined time is fed to a comparator circuit 70. When the value given to the comparator circuit 70 is less than a set allowable limit or below, the circuit 70 outputs a burst detection signal. A burst is detected by using phase information in this way, then no adjustment, low power consumption and miniaturization are more facilitated in comparison with the detection of a burst signal by an analog circuit and mis-detection due to a mixed signal such as interference noise is reduced.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、ディジタル無線通信に
おけるバースト信号検出回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a burst signal detection circuit in digital radio communication.

【0002】[0002]

【従来の技術】図4は、従来のバースト信号検出回路を
示す図である。従来のバースト信号の検出は、一般的
に、バンドパスフィルタ等により所望の周波数帯域以外
の雑音が取り除かれた受信波中間周波数(IF)信号を
入力とする受信電界強度検出器(Recieved S
ignal Strength Indicator:
RSSI)80を用いて行われる。前記受信電界強度検
出器80は入力信号の電界強度をアナログ信号として出
力する。前記受信電界強度検出器出力を入力とする比較
回路90ではその大きさがあるスレッショルドと比較さ
れ、その値よりも大きい場合バースト信号を検出したも
のとしてバースト検出信号を出力する。
2. Description of the Related Art FIG. 4 is a diagram showing a conventional burst signal detection circuit. The conventional detection of a burst signal is generally performed by a reception electric field strength detector (Received S) which receives a reception wave intermediate frequency (IF) signal from which noise other than a desired frequency band is removed by a bandpass filter or the like.
Signal Strength Indicator:
RSSI) 80. The received electric field strength detector 80 outputs the electric field strength of the input signal as an analog signal. A comparison circuit 90, which receives the output of the received electric field intensity detector, compares the magnitude with a certain threshold value, and outputs a burst detection signal assuming that a burst signal is detected when the magnitude is larger than the threshold value.

【0003】[0003]

【発明が解決しようとする課題】従来技術で用いられる
受信電界強度検出器はアナログ素子であり、その他の比
較回路等もアナログ回路あるいはアナログディジタル変
換回路を用いた回路構成となり、小型化、無調整化の点
で不利である。さらに、従来の受信電界強度検出器を用
いた方法は、受信変調波の振幅情報を用いてバースト信
号を検出するため、干渉雑音等の混入信号を誤って検出
する場合がある。さらに、移動体通信用受信機でよく用
いられるリミタ等の振幅情報を欠落させる素子を通過し
た後にこの方法を用いることはできない。
The received electric field strength detector used in the prior art is an analog element, and other comparison circuits and the like also have a circuit configuration using an analog circuit or an analog-digital conversion circuit, which is downsized and has no adjustment. It is disadvantageous in terms of conversion. Further, since the conventional method using the received electric field intensity detector detects the burst signal using the amplitude information of the received modulated wave, a mixed signal such as interference noise may be erroneously detected. Furthermore, this method cannot be used after passing through an element such as a limiter that is often used in a mobile communication receiver and that lacks amplitude information.

【0004】本発明は、受信変調波の位相情報を用いて
バースト信号を検出するバースト信号検出回路を提供す
ることを目的とする。
It is an object of the present invention to provide a burst signal detection circuit which detects a burst signal by using phase information of a received modulated wave.

【0005】[0005]

【課題を解決するための手段】前記目的を達成するため
の本発明の特徴は、特定パターンをふくむ位相変調信号
を入力とし、その1シンボル時間遅延した信号との差分
をK回(Kは1以上の自然数)行なうK回差分回路と、
その出力を1シンボル時間遅延させる遅延回路の出力
と、前記K回差分回路の出力とを加算する加算回路と、
該加算回路の出力の絶対値をとる絶対値回路と、その出
力を一定時間累積加算する累積加算回路と、該累積加算
回路の出力が、所定の許容値より小さいときにバースト
信号検出信号を出力する比較回路とを有するバースト信
号検出回路にある。
A feature of the present invention for achieving the above object is that a phase-modulated signal including a specific pattern is input, and the difference from the signal delayed by one symbol time is K times (K is 1). K number of difference circuits to perform the above natural number)
An adder circuit for adding the output of the delay circuit for delaying the output by one symbol time and the output of the K-time difference circuit;
An absolute value circuit that takes the absolute value of the output of the adder circuit, a cumulative adder circuit that cumulatively adds the output for a fixed time, and a burst signal detection signal when the output of the cumulative adder circuit is smaller than a predetermined allowable value. And a burst signal detection circuit having a comparison circuit for

【0006】[0006]

【作用】本発明は、従来のように振幅情報を用いるので
はなく位相情報を用いてバースト検出を行う。そのた
め、移動体通信用受信機でよく用いられるリミタ等の振
幅情報を欠落させる素子を通過した後の信号に対しても
本発明は適用でき、バースト検出回路がベースバンド帯
におけるディジタル回路により簡易に実現可能となる。
また、振幅情報を用いないので、干渉雑音等の混入信号
を誤って検出する確率は少なくなる。
According to the present invention, burst detection is performed using phase information instead of using amplitude information as in the prior art. Therefore, the present invention can be applied to a signal that has passed through an element such as a limiter that is often used in a mobile communication receiver and that lacks amplitude information, and the burst detection circuit can be easily provided by a digital circuit in the baseband. It becomes feasible.
Moreover, since amplitude information is not used, the probability of erroneously detecting a mixed signal such as interference noise is reduced.

【0007】[0007]

【実施例】図1は、本発明実施例を示す図である。本発
明は受信波位相信号のK回差分信号が例えばサイン関数
のように周期信号となる場合に適用できる。ここでは、
バーストフォーマットとして図2に示したものを用い、
また、変調方式としてπ/4−シフトQPSK変調方式
が用いられた場合を例にとり説明する。
FIG. 1 is a diagram showing an embodiment of the present invention. The present invention can be applied to the case where the K times difference signal of the received wave phase signal becomes a periodic signal like a sine function. here,
Using the burst format shown in FIG. 2,
Further, a case where a π / 4-shift QPSK modulation method is used as a modulation method will be described as an example.

【0008】本発明のバースト信号検出回路には受信変
調波位相信号が入力される。受信変調波位相信号は、例
えば、直交検波回路によりIチャネルおよびQチャネル
に分離されたベースバンド信号を位相情報(arcta
n(I/Q))が書き込まれたROMに入力することに
より容易に得られる。前記受信変調波位相信号はK回差
分回路(ここではK=2)に入力される。本実施例にお
いて図2に示したバーストフォーマットのプリアンブル
部における受信変調波位相信号が2回差分されて得られ
る信号を図3に示す。差分回数Kは、送信プリアンブル
パターンおよび変調方式を考慮し、図3に示すようK回
差分信号が周期信号となるように選ばれる。例えば、プ
リアンブルが「1001」のパターンをふくみ(π/
4)QPSK変調の場合はK=2が適当である。多くの
場合Kの値は2又は3以下となる。
A received modulated wave phase signal is input to the burst signal detection circuit of the present invention. The received modulation wave phase signal is obtained by, for example, phase information (arcta) of a baseband signal separated into I channel and Q channel by a quadrature detection circuit.
It can be easily obtained by inputting to the ROM in which n (I / Q)) is written. The received modulated wave phase signal is input to a K times difference circuit (K = 2 in this case). FIG. 3 shows a signal obtained by subtracting the received modulated wave phase signal twice in the preamble portion of the burst format shown in FIG. 2 in the present embodiment. The difference number K is selected in consideration of the transmission preamble pattern and the modulation method so that the K-time difference signal becomes a periodic signal as shown in FIG. For example, including a pattern with a preamble of "1001" (π /
4) In the case of QPSK modulation, K = 2 is suitable. In many cases, the value of K will be 2 or 3 or less.

【0009】つぎに、前記2回差分回路出力は加算回路
40に入力されるとともに、一方で遅延回路(1シンボ
ル時間遅延)30に入力される。加算回路40では、前
記2回差分回路出力と前記遅延回路の出力を加算し(図
3からもわかるように、前記加算回路出力値は雑音の無
い場合ゼロとなる)絶対値回路50へ入力される。絶対
値回路50では前記加算値の絶対値がとられ累積加算回
路60に入力される。前記累積加算回路60では、ある
一定時間にわたる累積加算値が求められる。前記累積加
算回路出力は比較回路70に入力されてそれが設定され
た許容値以下であればバースト検出信号を出力する。
Next, the output of the two-time difference circuit is input to the adder circuit 40 and, at the same time, is input to the delay circuit (1 symbol time delay) 30. In the adder circuit 40, the output of the two-time difference circuit and the output of the delay circuit are added (as can be seen from FIG. 3, the output value of the adder circuit is zero when there is no noise) and is input to the absolute value circuit 50. It The absolute value circuit 50 takes the absolute value of the added value and inputs it to the cumulative addition circuit 60. The cumulative addition circuit 60 obtains a cumulative addition value over a certain fixed time. The output of the cumulative addition circuit is input to the comparison circuit 70, and if it is equal to or less than the set allowable value, a burst detection signal is output.

【0010】[0010]

【発明の効果】本発明は、従来のように振幅情報を用い
るのではなく位相情報を用いてバースト検出を行う。そ
のため、移動体通信用受信機でよく用いられるリミタ等
の振幅情報を欠落させる素子を通過した後の信号に対し
ても本発明は適用でき、バースト検出回路がベースバン
ド等におけるディジタル回路により簡易に実現可能とな
る。そのため、従来のアナログ回路を用いたバースト信
号検出器に比べ、無調整化、低消費電力化、および小型
化の点で有利である。また、干渉雑音等の混入信号を誤
って検出する確率が減少する。
According to the present invention, burst detection is performed using phase information instead of using amplitude information as in the prior art. Therefore, the present invention can be applied to a signal that has passed through an element such as a limiter that is often used in a mobile communication receiver and that lacks amplitude information, and the burst detection circuit can be easily provided by a digital circuit in a baseband or the like. It becomes feasible. Therefore, as compared with the conventional burst signal detector using the analog circuit, it is advantageous in terms of no adjustment, low power consumption, and miniaturization. Also, the probability of erroneously detecting a mixed signal such as interference noise is reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示す図。FIG. 1 is a diagram showing an embodiment of the present invention.

【図2】バーストフォーマット例を示す図。FIG. 2 is a diagram showing an example of a burst format.

【図3】2回差分信号を示す図。FIG. 3 is a diagram showing a two-time difference signal.

【図4】従来例の示す図。FIG. 4 is a diagram showing a conventional example.

【符号の説明】[Explanation of symbols]

10−1,10−2 差分回路 20 減算回路 30 遅延回路(1シンボル時間) 40 加算回路 50 絶対値回路 60 累積加算回路 70,90 比較回路 80 受信電界強度検出器 10-1, 10-2 Difference circuit 20 Subtraction circuit 30 Delay circuit (1 symbol time) 40 Addition circuit 50 Absolute value circuit 60 Cumulative addition circuit 70, 90 Comparison circuit 80 Received field strength detector

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 特定パターンをふくむ位相変調信号を入
力とし、その1シンボル時間遅延した信号との差分をK
回(Kは1以上の自然数)行なうK回差分回路と、 その出力を1シンボル時間遅延させる遅延回路の出力
と、前記K回差分回路の出力とを加算する加算回路と、 該加算回路の出力の絶対値をとる絶対値回路と、 その出力を一定時間累積加算する累積加算回路と、 該累積加算回路の出力が、所定の許容値より小さいとき
にバースト信号検出信号を出力する比較回路とを有する
ことを特徴とする、バースト信号検出回路。
1. A phase-modulated signal including a specific pattern is input, and the difference from the signal delayed by one symbol time is K.
Number of times (K is a natural number of 1 or more), an adder circuit that adds the output of the delay circuit that delays the output by one symbol time, and the output of the K-time difference circuit, and the output of the adder circuit An absolute value circuit that takes an absolute value of, a cumulative addition circuit that cumulatively adds the outputs for a certain period of time, and a comparison circuit that outputs a burst signal detection signal when the output of the cumulative addition circuit is smaller than a predetermined allowable value. A burst signal detection circuit having.
JP26313193A 1993-09-28 1993-09-28 Burst signal detection circuit Expired - Lifetime JP3223402B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26313193A JP3223402B2 (en) 1993-09-28 1993-09-28 Burst signal detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26313193A JP3223402B2 (en) 1993-09-28 1993-09-28 Burst signal detection circuit

Publications (2)

Publication Number Publication Date
JPH0799521A true JPH0799521A (en) 1995-04-11
JP3223402B2 JP3223402B2 (en) 2001-10-29

Family

ID=17385251

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26313193A Expired - Lifetime JP3223402B2 (en) 1993-09-28 1993-09-28 Burst signal detection circuit

Country Status (1)

Country Link
JP (1) JP3223402B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106353591A (en) * 2016-10-21 2017-01-25 成都前锋电子仪器有限责任公司 Average burst power measurement circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106353591A (en) * 2016-10-21 2017-01-25 成都前锋电子仪器有限责任公司 Average burst power measurement circuit
CN106353591B (en) * 2016-10-21 2023-05-16 成都前锋电子仪器有限责任公司 Average burst power measuring circuit

Also Published As

Publication number Publication date
JP3223402B2 (en) 2001-10-29

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