JPH0799515A - Fsk detection circuit - Google Patents

Abstract

PURPOSE:To devise a detection circuit to be proper to circuit integration by decreasing jitter of a detection output in the zero IF detection system FSK detection circuit so as to reduce a limited lower limit of an FSK modulation figure to be nearly a half or below and also its circuit scale. CONSTITUTION:Orthogonal base band signals I, Q are binary-shaped at comparators 1, 2 respectively, one output is inputted to a digital differentiation device 3 as its timing input B, and 90 deg. phase shift processing is applied to a processing input A from other comparator according to both leading and trailing timings. An EX-OR gate 4 obtains exclusive OR between its output D and the timing input B, its output is given to an LPF 5, in which a harmonic component and a noise component are eliminated from the signal and a detection output is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulation circuit used in a radio receiver, and more particularly to a quadrature baseband signal I which receives an FSK-modulated carrier signal and uses the same local oscillation frequency as the carrier frequency. (In-phase component) and Q
The present invention relates to an improvement of an FSK detection circuit in a so-called zero IF detection system, which performs FSK detection after obtaining (quadrature component).

[0002]

FSK of quadrature detection waveform (zero IF detection method)
FIG. 1 shows a configuration example of a conventionally known detector circuit. In FIG. 1, 101 and 102 are comparators for binary-shaping the quadrature baseband signals I and Q, 1
03 indicates the outputs of the comparators 101 and 102 respectively by D
It is a D-type flip-flop that takes in the input and the CK (clock) input, determines the phase of both, and obtains the determination output DET. FIG. 2 is a time chart showing an operation example of each signal of FIG. In the figure, the uppermost row is transmission data, the second and third rows are examples of I and Q waveforms, respectively.
It is to be noted that one of the examples in which both I and Q are shown by a solid line and another example shown by a broken line having a phase relationship of 180 ° with respect to this are 2
The street is shown. In any of the examples, the Lissajous figure drawn by I and Q corresponds to the characteristics "H" and "L" of the transmission data, and the circles rotate left and right respectively. This is because the rotation direction of the modulation vector is switched depending on the polarity of the frequency shift ΔF _{dev in} FSK. The fourth and fifth stages of FIG. 2 are shown in FIG. 1 for the waveform examples shown by the solid and broken lines of I and Q above.
The respective operation examples of the determination output DET are shown.

As shown in the figure, the DET is an example of the former (I,
In the Q solid line display, the rising zero-cross point of the Q solid line (●
The waveform is obtained by sampling (⊚) the polarity of the solid line of I (∘). On the other hand, in the latter example (I, Q broken line display), the polarity of the broken line of I (square mark) at the rising zero crossing point of the broken line of Q (square mark) is sampled (◇ mark).
The waveform becomes In both cases, the transmission data "H",
The detection output correctly corresponds to the polarity change of "L", but when the former and the latter are carefully compared, it is found that the judgment delay amounts τ ₁ , τ ₂ and τ ₃ , τ ₄ are greatly different. This means that the judgment delay amounts are I and Q.
It is shown that the extraction process greatly changes depending on the phase of the local oscillator on the receiving side, and this variation increases as the rotation speed of the modulation vector in one symbol section decreases.

[0004]

From the above, in the conventional configuration shown in FIG. 1, the modulation index of FSK is

[Equation 1] There is a drawback that the jitter of the judgment output becomes large as the number becomes smaller and the detection characteristic is significantly deteriorated. This drawback becomes fatal in the case of high-speed transmission in which the modulation rate R increases, because m is set small due to the limitation of the occupied bandwidth of the channel.

The object of the present invention is to set the lower limit of the applicable FSK modulation index, which was limited in the conventional circuit, to about 1.
It is to provide a FSK detection circuit that is suitable for integration into an IC, because the size of the added part is small in order to realize a large reduction of 1/2.

[0006]

The first means of the FSK detection circuit of the present invention is a quadrature baseband signal I (in-phase component).
And the first and second comparators for binarizing Q (quadrature component), and the output of one of the comparators is used as the timing input, and the output of the other comparator is used as the processing input, and the timing input A digital differentiator that performs a 90 ° phase shift process on the processing input according to both rising and falling timings, and an exclusive OR that outputs an exclusive OR of the output of the digital differentiator and the timing input It is characterized in that it is composed of a gate and a low-pass filter which obtains a detection output by removing a harmonic component and a noise component of the output of the exclusive OR gate.

The second means of the FSK detection circuit of the present invention is
First and second comparators for binary-shaping the quadrature baseband signals I (in-phase component) and Q (quadrature component) respectively, and the outputs of the second and first comparators as timing inputs, and the first and second comparators The output of the second comparator is used as a processing input, and 90 ° phase shift processing is performed on each processing input according to both the rising and falling timings of each timing input.
Digital differentiator, first and second inputs of the output of the second comparator, the output of the first digital differentiator, and the output of the first comparator and the output of the second digital differentiator, respectively. Exclusive OR gate, an adder for obtaining a level difference between the outputs of the two exclusive OR gates, and a low-pass filter for obtaining a detection output by removing harmonic components and noise components from the output of the adder. It is characterized by being configured with a wave vessel.

[0008]

【Example】

[Structure] First, a first embodiment will be described. FIG. 3 is a diagram showing a configuration example showing the first embodiment of the present invention. In the figure,
1 and 2 are orthogonal baseband signals I and Q, respectively.
Is a comparator for binary-shaping. Reference numeral 3 denotes a digital differentiator which uses the output of the comparator 2 as the timing input B and the output of the comparator 1 as the processing input A, and shifts the phase of the processing input A by 90 ° in accordance with both the rising and falling timings of the timing input B. It has the function of performing processing.
Reference numeral 4 denotes an exclusive OR (EX-OR) gate which outputs an exclusive OR E of the outputs of the comparator 2 and the digital differentiator 3, and 5 denotes a harmonic component and a noise component of the output E of the EX-OR gate 4. It is a low pass filter (LPF) to be removed.

FIG. 4 is a diagram showing an example of the configuration of the digital differentiator 3 shown in FIG. In the figure, 6 is a delay circuit for delaying the timing input B for a certain time, and it is possible to use not only digital delay means such as multistage cascade gates and shift registers but also analog delay means such as capacitors and resistors. It can be easily realized. Reference numeral 7 is an EX-OR gate for outputting the exclusive OR of the delay output and the timing input B, and 8 is a D-type flip-flop for sampling the processing input A at the timing of the output of the EX-OR gate 7. With the above configuration, when the processing input A and the timing input B input to the digital differentiator 3 are both sine wave binary shaped signals and have a phase difference of 90 ° from each other, the processing input A Since the output is obtained by synchronizing the changing point with both the rising and falling changing points of the timing input B, the change of the processing input A is 9
It can be seen that the phase is shifted by 0 ° and a process equivalent to a kind of differential operation is realized.

[Operation] First of the present invention shown in FIGS. 3 and 4
Based on the configuration example of the embodiment of FIG.
Will be described in detail by. FIG. 5 is a time chart showing an operation example of each signal of FIG. 3, and is the same as FIG. 2 from the uppermost stage to the third stage in the figure. (However, the illustration of the broken line in FIG. 2 is excluded.) At the fourth stage, the fifth stage, and the bottom stage, the output D of the digital differentiator 3, the output E of the EX-OR gate 4, and the detection, respectively. An operation example of output is shown. As shown in the figure, the polarity of I (marked with ◯) is sampled at the change points of Q rising and falling (marked with ●), and on D (◎).
Appears). On the other hand, the exclusive OR of the above-mentioned D and the binary shaped waveform of I is the output E of the EX-OR gate 4,
E has the illustrated waveform. Therefore, a waveform obtained by low-pass filtering E is obtained in the detection output, and it is understood that the detection operation corresponding to the transmission data is performed. However, in this example, the polarity of the transmission data and that of the detection output are inverted. Here, when E in FIG. 5 is compared with DET (indicated by I, Q solid lines) in FIG. 2 in more detail, it is clear that the determination delay amount of detection is equivalent.

Next, in FIG. 5, when both I and Q are inverted by 180 ° (indicated by broken lines I and Q in FIG. 2), the determination in the configuration of the first embodiment of the present invention is performed. Consider the amount of delay. In this case, first, the polarities of I and Q in FIG. 5 are all inverted. However, since there is no change in the positions of both the rising and falling changing points (marked by ●) of Q, the timing of the change of D does not change at all, and its polarity is simply reversed according to the reversal of the polarity of I. is there. Therefore, EX-OR
In Gate 4, the two inputs (binary shaped value of D and I) are
At the same time, since it is the inversion of the example of FIG. 5, the output E does not change at all and maintains the waveform shown in E of FIG. 5 according to the following equation, which is a characteristic of the exclusive OR.

[0012]

[Equation 2]

From the above, the DET shown at the bottom of FIG.
(I, Q dashed line display) large judgment delay amount τ ₃ ,
τ ₄ does not occur in the configuration of the first embodiment of the present invention, and the variation in the determination delay amount is suppressed by the averaging by the low pass filter 5. This is because the configuration of the first embodiment of the present invention uses both the rising and falling transition timings of Q (or I), which is equivalent to twice the determination sampling rate as the conventional configuration. It is a nod to the achievement of.

[Structure] Next, a second embodiment of the present invention will be described. FIG. 6 is a diagram showing a configuration example of the second embodiment of the present invention. In the figure, 1 and 2 are comparators for binary-shaping the quadrature baseband signals I and Q, respectively. 1
Reference numerals 3 and 14 denote digital differentiators each of which uses the outputs of the comparators 2 and 1 as the timing input B and the outputs of the comparators 1 and 2 as the processing input A, both of which are timings of rising and falling of the timing input B. According to the above, the processing input A has a function of performing a 90 ° phase shift processing. Reference numerals 15 and 16 denote exclusive ORs (E _I and E _Q) for obtaining the exclusive ORs E _I and E _Q of the output of the comparator 2 and the output D _I of the digital differentiator 13, and the output of the comparator 1 and the output D _Q of the digital differentiator 14, respectively. EX-O
R) gate, 17 is an adder for obtaining the level difference between E _I and E _Q , and 18 is a low-pass filter (LPF) for removing harmonic components and noise components from the output of the adder 17.

FIG. 7 shows an example of the configuration of the digital differentiator 13 shown in FIG. In the figure, reference numeral 19 is a delay circuit for delaying the timing input B for a certain period of time by a digital delay means such as a multistage cascade gate or a shift register, or by an analog delay means such as a capacitor or a resistor. It can be easily realized. Reference numeral 20 is an EX-OR gate that outputs the exclusive OR of the delay output and the timing input B, and 21 is a D-type flip-flop that samples the processing input A at the timing of the output of the EX-OR gate 20. With the above configuration, when the processing input A and the timing input B input to the digital differentiator 13 are both sine wave binary shaped signals and have a phase difference of 90 ° from each other, the processing input A Since the output is obtained by synchronizing the changing point with both the rising and falling changing points of the timing input B, the change of A is phase-shifted by 90 ° and a process equivalent to a kind of differential operation is realized. I understand.

[Operation] FS of the present invention shown in FIGS. 6 and 7
Based on the configuration example of the second embodiment of the K detection circuit, its detection operation and effect will be described in detail with reference to FIG. FIG. 8 is a time chart showing an operation example of each signal in FIG. 6, and is the same as FIG. 2 from the uppermost stage to the third stage in the figure (however, the broken line in FIG. 2 is not illustrated). . The fourth and subsequent stages of the figure show respective operation examples of D _I , E _I , Q _Q , E _Q shown in FIG. 6, the output of the adder 7 (E _Q −E _I ) and the detection output. As shown in the figure, the polarity (○) of I is sampled at the rising and falling timings of Q (●) and D _I
It appears on the top (marked with ⊚), and similarly, the polarity of Q (marked with ◯) is sampled at the timing of rising and falling of I (marked with ●) and appears on D _Q. Each of the above signals D _I , D _Q and I,
From the binary shaping signal of Q, E _I and E _Q have the illustrated waveforms. When you draw the output E _Q -E _I adder 17 from these waveforms, ternary waveform shown is obtained. Detection output (lowermost stage) obtained by removing the harmonic components due to the EX-OR gates 15 and 16 remaining in this waveform by the low-pass filter 18.
It can be seen that the detection operation corresponding to the transmission data appears in. In addition, 1-symbol length "H" of the transmission data
“L” section of E _I and “H” section of E _Q corresponding to the section
When the section is examined, the former is longer than one symbol length, and the latter is shorter. Therefore, the adder 17 and the low-pass filter 18 are
From this, it can be seen that the effect of averaging the determination delay amount is obtained.

Next, in FIG. 8, when both I and Q are inverted by 180 ° (indicated by broken lines I and Q in FIG. 2), the determination in the configuration of the second embodiment of the present invention is performed. Consider the amount of delay. In this case, first, the polarities of I and 1 in FIG. 8 are all inverted. However, since there is no change in the positions of both the rising and falling changing points (marked with ●) of I and Q,
The timing of changes in D _I and D _Q does not change at all.
Its polarity is only reversed as the polarity of I and Q is reversed. Therefore, in the EX-OR gates 15 and 16, each of the two inputs becomes the inversion of the example of FIG. 8 at the same time, so that the outputs E _I and E _Q do not change at all due to the following equation which is the characteristic of the exclusive OR. , The waveforms shown by E _I and E _Q in FIG. 8 are maintained.

[0018]

[Equation 3]

From the above, the conventional D shown at the bottom of FIG.
Large determination delay τ seen in ET (I, Q broken line display)
Not only ₃ and τ ₄ do not occur in the configuration of the second embodiment of the present invention, but also variations in the decision delay amount are suppressed by averaging by the adder 17 and the low-pass filter 18. This is because the configuration of the second embodiment of the present invention uses both the rising and falling transition timings of both Q and I signals, and is equivalent to a decision sampling rate four times that of the conventional configuration. It is a nod to the achievement of.

[0020]

As described above in detail, according to the present invention, it is possible to compress the jitter amount of the detection waveform found in the conventional FSK detector of the quadrature detection waveform to 1/2 or less and 1/4 or less. , The FSK modulation index lower limit can be greatly reduced to 1/2 or less, and it is possible to support a higher data transmission rate than conventional circuits, and not only for heterodyne receivers but also for linear conversion type receivers. Can also be applied and has high versatility in application. Further, in realizing the present invention, the circuit portion added to the conventional one is small in scale, and
Since it is suitable for carbonization, it is extremely advantageous for downsizing and economy.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a conventional circuit configuration example.

FIG. 2 is an operation time chart of a conventional circuit.

FIG. 3 is a configuration diagram showing a first embodiment of the present invention.

FIG. 4 is a partial configuration diagram of the first embodiment of the present invention.

FIG. 5 is a first operation time chart of the present invention.

FIG. 6 is a configuration diagram showing a second embodiment of the present invention.

FIG. 7 is a partial configuration example diagram of a second embodiment of the present invention.

FIG. 8 is a second operation time chart of the present invention.

[Explanation of symbols]

 1, 2 Comparator 3 Digital differentiator 4 EX-OR gate 5 LPF 6 Delay circuit 7 EX-OR gate 8 D type flip-flop 13, 14 Digital differentiator 15, 16, 20 EX-OR gate 17 Adder 18 LPF 19 Delay Circuit 21 D type flip-flop

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroki Suzuki 2-13-13 Toranomon, Minato-ku, Tokyo International Electric Co., Ltd. (72) Toru Sasayama 2-3-13 Toranomon, Minato-ku, Tokyo International Electric Co., Ltd.

Claims (2)

[Claims] 1. A first and a second comparator for binary-shaping the quadrature baseband signals I (in-phase component) and Q (quadrature component), respectively, and an output of one of the comparators is used as a timing input, and the other of the comparators is used. The output of the comparator is used as a processing input, and a digital differentiator for performing 90 ° phase shift processing on the processing input according to both the rising and falling timings of the timing input, and the output of the digital differentiator and the timing. It is composed of an exclusive OR gate that outputs an exclusive OR with the input, and a low-pass filter that obtains a detection output by removing harmonic components and noise components of the output of the exclusive OR gate. An FSK detection circuit characterized by the above. 2. A first and a second comparator for binary-shaping the quadrature baseband signals I (in-phase component) and Q (quadrature component) respectively, and outputs of the second and first comparators as timing inputs, The outputs of the first and second comparators are used as processing inputs, and the rising edges of the respective timing inputs,
First and second digital differentiators for applying 90 ° phase shift processing to the respective processing inputs according to both timings of the falling edges, outputs of the second comparator and outputs of the first digital differentiator , And the first and second exclusive OR gates to which the output of the first comparator and the output of the second digital differentiator are respectively input, and the level difference between the outputs of the two exclusive OR gates. An FSK detection circuit comprising an adder for obtaining and a low-pass filter for removing a harmonic component and a noise component from an output of the adder to obtain a detection output.