JPH0795747B2 - Data transmission equipment - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a data transmission device that performs loop switching in a loop data transmission system.

2. Description of the Related Art In a loop data transmission system, two transmission lines for transmitting signals in opposite directions may be installed in consideration of a failure of the transmission line. Generally, only one transmission line is used, and the other transmission line is used in response to a failure of the transmission line in use. Conventionally, this kind of loop switching is called "master control station", "center station", etc. In response to the identification of a clock signal break, a special command is sent to the master station through the standby system, and the master station is wired separately. It has been performed under the control of a special control device such as switching of each station by the line. In such a system, the occurrence of a failure in the special control device may develop into a fatal failure, and there is a drawback that extra special lines are provided.

In another method, when the master control station detects an abnormality in the loop-shaped transmission line, the master control station transfers frames sequentially from itself to recover. However, if the master control station goes down, there is a drawback that it is completely useless.

An object of the present invention is to automatically reconfigure a loop when a failure occurs in a transmission path of an active system or a failure occurs in both transmission paths of an active system and a standby system between certain data transmission devices. It is to provide a data transmission device capable of detecting in which section of a loop-shaped transmission path a failure has occurred.

The apparatus of the present invention is a data transmission system including a pair of loop-shaped transmission lines having an active system and a standby system, and a plurality of data transmission devices connected to the transmission lines. Identification detection means for performing at least one of identification of a signal disconnection from a transmission line and detection of a specific pattern indicating that the signal disconnection has been detected, and the signal disconnection and the above-mentioned in the operation loop transmission line. In response to at least one of reception of a specific pattern, switching means for transmitting the specific pattern to the operating loop transmission line and switching both input and output to the standby system, and invalidating the signal of the standby loop transmission line And a connection means for switching the input side to the operating loop transmission line and switching the output side to the standby loop transmission line for connection in a loopback state. Sending means for sending the specific pattern to the output side in response to the invalidity of the signal on the input side after the loopback state, and storing the detection made in response to the detection of the signal disconnection on the operational loop transmission line And means for keeping.

BEST MODE FOR CARRYING OUT THE INVENTION Next, an embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, the system in which the present invention is operated includes transmission devices 1 to 4, first loop transmission lines 11 to 14, and second transmission lines.
The loop transmission lines 21 to 24 are included. The transmission lines of the first loop systems 11 to 14 are used while the normal system is operating normally, and the transmission lines of the second loop systems 21 to 24 are in the bypass state.

With reference to FIG. 2, one embodiment of the present invention includes a first photoelectric conversion circuit 30, a second photoelectric conversion circuit 31, clock lines 51 and 61 for transmitting a clock signal after photoelectric conversion, and photoelectric conversion. Data lines 52 and 62 for transmitting the converted data, a transmission line control circuit 32, clock lines 54 and 64 for transmitting a clock signal to be sent to the loop transmission lines 11 and 21, and the loop transmission lines 11 and 21. Data lines 55 and 65 for transmitting data to be sent to the control signals, control signal lines 56 and 66 for transmitting control signals for individually controlling the first and second photoelectric conversion circuits 30 and 31, respectively, and a microprogram. Controlling processor 33, storage unit 34, data path 8
1, signal line group 82 for transmitting control signals for controlling interrupt signal line 82, transmission path control circuit 32 and storage unit 34, storage unit
34 address line 84, write pulse line 85 for writing data to the storage unit 34, reset signal line 316 for giving a master reset signal, and a transmission signal that turns on when data is to be sent to the loop transmission line 11 or 21. Request signal line for transmission 8
7. A signal line 88 for transmitting an interrupt signal when a specific frame is detected, and a signal line 89 for transmitting an interrupt signal when a frame enters the receiving buffer.

Referring to FIG. 3, the transmission line control circuit 32 shown in FIG. 2 includes a clock signal disconnection detection circuit 91, a transmission / reception circuit 92 for controlling data from or to a loop transmission line, and a decoder 9.
3, a clock generation circuit 94, a flip-flop 101 indicating that transmission is possible to the first loop transmission line, and a flip-flop 20 indicating transmission to the second loop transmission line
1, a flip-flop 102 indicating that reception is possible from the first loop system transmission line, a flip-flop 202 indicating that reception is possible from the second loop system transmission line,
A flip-flop 103 that gives a bypass instruction to the first loop-type transmission line, a flip-flop 203 that gives a bypass instruction to the second loop-type transmission line, a traffic signal 301 that sends a clock detection signal indicating detection of an uninterrupted signal, and a flip-flop. An output signal line 321 for transmitting the output signal of the flip-flop 102, an output signal line 322 for transmitting the output signal of the flip-flop 202, a clock signal line 315 for giving an internal clock from the clock generation circuit 94, and a signal for giving a signal generated by the decoder 93. Line 3
17 and 318, serial data line 311, receive clock line 31
2, and AND circuit.

Referring to FIG. 4, the clock signal loss detection circuit of FIG.
Reference numeral 91 denotes a flip-flop 110 that indicates that the loop transmission line is in a connected state, a flip-flop 114 that indicates a clock signal disconnection that transitions from the connected state to the unconnected state, a flip-flop 124, and a constant for the input data of the loop transmission line. the logical value to a value of T0 "1" is followed whether counter 111 for identifying, as long as either of the reception state flip-flop 102 or 202 counter 111 when on does not detect the value of the constant T ₀ constants A counter 112 that keeps counting until the value of T1 is reached, and a counter that keeps counting until the value of the constant T2 is reached unless the logical value "0" of the input data of the loop transmission line is detected when the connection status flip-flop 110 is turned on.
113, a counter 123 that keeps counting until the value of a constant T3 is reached unless a logical value "1" of the input data of the loop transmission line is detected when the connection state flip-flop 110 is on, a clock signal 315 that gives an internal clock, and a master reset A reset signal line 316 for giving a signal, signal lines 317 and 319 for transmitting a reset signal for resetting the clock break flip-flops 114 and 124 from the host device, a NAND circuit 402, an OR circuit 403, and a receiver 411. Has been done.

Referring to FIG. 7, which is a general form of a frame applied to the present invention, F indicates a flag pattern '01111110', DA indicates a destination address, SA indicates a source address, C indicates control information, I indicates data information (may be omitted), and FCS is a cyclic redundancy check bit for checking whether or not the frame is correctly transferred in the frame check sequence.

Referring to FIG. 8, in the status information stored in the storage unit 34, bit "0" is connected to the first loop system transmission line, bit "1" is connected to the second loop system transmission line, and bit "2". 'Is connected as loopback A (in this embodiment, the receiving side is connected to the first loop system transmission line and the transmitting side is connected to the second loop system transmission line), and bit' 3 'is a loop. Connected as back B (in this embodiment, it means that the receiving side is connected to the second loop type transmission line and the transmitting side is connected to the first loop type transmission line), and bit '4' is the first loop. Signal disconnection is detected on the system transmission line and bit '5' indicates that signal disconnection is detected on the second loop system transmission line.

Next, the operation of the embodiment will be described in detail. In the normal state, the first loop system transmission lines 11 to 14 are used. Now, assume that the first loop transmission line is used. In the data transmission device 1, a transmittable flip-flop 101 for the first loop transmission line, a receivable flip-flop 102 for the first loop transmission line, and a bypass flip-flop 203 for the second loop transmission line are set. Has been done. Further, the signal on the output signal line 301 of the clock signal disconnection detection circuit 91 is in the ON state. The other data transmission devices 2 to 4 shown in FIG. 1 are also in the same state as the transmission device 1 and are connected to the first loop transmission line.

Referring to FIG. 2, in this state, the first loop transmission line is
When 14 is disconnected, the first photoelectric conversion circuit 30 of the first loop transmission line in the data transmission device 1 sets the data lines 52 to all ones. That is, when the clock 51 stops flowing due to the disconnection of the first loop system transmission line 14, the signal on the data line 52 continuously becomes the logical value "1". In response to the signal applied via the data line 52, an interrupt signal is output to the signal line 82 from the clock signal disconnection detection circuit 91 in the transmission control circuit 32. In response to the interrupt signal provided via the signal line 82, the processor 33 stores the eighth signal stored in the storage unit 34.
Read the status of the figure. In response to this reading operation, the status bit 4 in FIG. 8 is set in order to know that it is connected to the first loop, and to indicate that it has gone down in the first loop system. Processor 33 sends data and write pulses to transmission control circuit 32 via data path 81 and write pulse line 86. In response to these data and write pulse, the respective states of the transmittable flip-flop 101 and the receivable flip-flop 102 for the first loop transmission line are turned off, and the data of all 0 is in the first loop. It will flow to the system transmission line. That is, in order to notify other transmission devices that the first loop system has been disconnected, all 0s are sent as a pattern different from the all 1s indicating the clock disconnection. At the same time, the transmittable flip-flop 201 for the second loop system transmission line is turned on and the bypass flip-flop 203 is turned off. At this time, since the signal of the transmission request signal line 87 is in the off state, the transmission / reception circuit 92 in the transmission control circuit 32 continuously sends a pattern (a valid signal) that does not cause a clock signal interruption to the loop transmission line. It is like this. After the elapse of a predetermined time, the receivable flip-flop 202 for the second loop system transmission line is turned on, and the processor 33 detects the signal of the clock detection signal line 301 which is the output of the clock signal disconnection detection circuit 91. .

On the other hand, the pattern of all 0s sent to the loop-shaped transmission line 11 is received by the data transmission device 2, and is transmitted / received through the photoelectric conversion circuit 30 of FIG. 1 and the clock signal break detection circuit 91 of FIG. Given to 92. In the transmission / reception circuit 92, an interrupt signal is output from the clock signal disconnection detection circuit 91 to the signal line 71 in response to a signal given via the data line 52. As a result, the processor 33 knows that the clock break has occurred on the loop transmission line. Further, except that the processor 33 of the data transmission device 2 does not set the bit 4 of the status in response to the detection of the clock loss in the data transmission device 1 (clock loss detection by the all 0 pattern in the data transmission device 2 is the status. Bit 4 of is not set),
Exactly the same operation is performed. On the other hand, on the other hand, the transmission line 22 has a pattern in which the clock signal is not interrupted. As a result, since the processor 33 of the data transmission device 1 is in the ON state when trying to detect the signal output from the clock detection signal line 301, the content of the bypass flip-flop 103 corresponding to the first loop system is in the ON state. Done After that, while switching from the first loop system to the second loop system, the status bit 0 in FIG. 8 is reset and bit 1 is set, so that the connection to the second loop transmission line is confirmed. The indicated status is stored in the storage unit 34. In this way, the data transmission device 4
The clock interruption propagates to all 0s, switches to the second loop transmission line, and ends. Referring to FIG. 5, there is shown a final state when the loop transmission line 14 is broken. Therefore, bit 4 of the status of the data transmission device 1
Since it is set, it can be seen from the whole system that there is an abnormality in the loop-shaped transmission line 14.

The method of knowing the abnormality of the loop-shaped transmission line and the data transmission device of the entire system is as follows. When the device for monitoring the loop is the data transmission device 3, the data transmission device 3 causes each of the data transmission devices to be set at predetermined intervals. The command frame for reading the status information of (1) may be defined in the format according to FIG. 7 (referred to as RSTS frame in this embodiment). Therefore, when the RSTS frame is sent to each data transmission device,
The signal on the receiving side of each data transmission device is a clock loss detection circuit
It is given to the reception buffer of the transmission / reception circuit 92 via 91, and the processor 33 is notified by an interrupt signal output from the signal line 89. Therefore, the processor 33 can read the contents of the reception buffer through the data bus 81 and the signal line group 83, and in response to the status read request from the data transmission device 3, the status stored in the storage unit 34 is read. To be In the frame format according to FIG. 8, destination address information DA, source address information SA, control information C containing status information, and status 8-bit 1 are written in this order in the transmission buffer of the transmission / reception circuit 92, and a transmission request is made. By turning on the signal of the signal line 87, the frame is sent out to the data transmission device 3 through conversion from parallel to serial and via the photoelectric conversion line 30 or 31. In the data transmission device 3, when a frame is given to the reception buffer of the transmission / reception circuit 92, the signal line 89 is sent to the processor 33.
Signaled by an interrupt signal from As a result, the processor 33 can read the contents of the reception buffer via the data bus 81 and the signal line group 83, know that the response frame to the RSTS frame has arrived from each data transmission device, and further read the status. By this, an abnormality of the loop-shaped transmission line and each data transmission device is known.

In addition, the method of knowing the abnormality of the loop-shaped transmission line and the data transmission device of the entire system is such that, when each data transmission device detects a clock loss in the data transmission device 3 which monitors the loop, a predetermined time ( In a method in which the processor 33 reads the status stored in the storage unit 34 during a time period in which the disturbance of the loop-shaped transmission line due to the switching of the loop is taken into consideration and the frame configuration according to FIG. 8 is sent to the data transmission device 3. is there. The procedure in which each data transmission device reads the status stored in the storage unit 34 and informs the transmission device 3 of the data for monitoring the loop is the same as the above-described procedure.

Next, when both the transmission lines 14 and 21 are broken, the last data transmission device 4 described in the above-mentioned disconnection of the transmission line 14
In the operation of the data transmission device 4, since the transmission line 21 is disconnected, the processor 33 of the data transmission device 4 operates.
Is off when it detects the signal on the clock detection signal line 301. Therefore, the receivable flip-flop 202 corresponding to the second loop system is turned off, and the receivable flip-flop 102 corresponding to the first loop system is turned off.
Is turned on, and the signal on the clock detection signal line 301 is about to be detected. At this time, since the data transmission devices 1 to 3 corresponding to the first loop system are in the bypass state, the clock signal is disconnected. Therefore, since the signal of the clock detection signal line 301 of the data transmission device 4 is in the off state, the processor 33 turns off the transmittable flip-flop 201 for a fixed time,
After a certain time, it returns to the on state. Along with this, the processor
33 resets bit 0 of the status shown in FIG. 8 and sets bit 2, and stores the status information in the storage unit 34. That is, the data transmission device 4 enters a loopback state in which the first loop system is on the reception side and the second loop system is on the transmission side, and causes a clock signal disconnection on the transmission line 24 for a certain time by a pattern of all 0s. Then, the data transmission device 3
The processor 33 detects the ON state of the interrupt signal line 88 of the clock signal interruption, sends the pattern of all 0s to the second loop transmission line, and outputs the data of the data path 81 and the write pulse line 86.
Is used to turn off the transmittable flip-flop 201 and the receivable flip-flop 202 corresponding to the second loop system, and to pass the pattern data of all 0s to the second loop system transmission line. Next, the transmittable flip-flop 101 corresponding to the first loop system is turned on and the bypass flip-flop 103 is turned off.

At this time, since the signal of the transmission request signal line 87 is in the off state,
The transmitting / receiving circuit 92 is adapted to continuously send a pattern that does not cause a clock signal interruption onto the line. After a lapse of a predetermined time, the content of the receivable flip-flop corresponding to the first loop system is turned on, and the processor 33 detects the signal of the clock detection signal line 301 which is the output of the clock signal disconnection detection circuit 91. go. However, since the pattern of all 0s flows in the loop transmission line 23, the data transmission device 2 also performs the same operation as the above-mentioned data transmission device 3. Therefore, the loop system transmission line 12 is not disconnected by the clock signal. Therefore, when the processor 33 of the data transmission device 3 goes to detect the signal of the clock detection signal line 301, it is in the ON state, so that the content of the bypass flip-flop 203 corresponding to the second loop system is in the ON state. And switch from the second loop system to the first loop system and
Bit 1 of the status in the figure is reset, bit 0 is set, and the status is stored in the storage unit 34.

In this way, the data transmission device 1 is also sequentially connected to the second loop system side.
A clock signal having a pattern of all 0s propagates to switch to the first loop transmission line.

The operation of the data transmission device 1 is in the off state when the processor 33 of the data transmission device 1 detects the signal of the clock detection signal line 301 because the transmission line 14 is disconnected. Therefore, the receivable flip-flop 102 of the first loop system is turned off, the receivable flip-flop 202 corresponding to the second loop system is turned on, and the signal of the clock detection signal line 301 is detected. At this time,
In the data transmission devices 2 and 3, the fourth loop system is in the connected state, the second loop system is in the bypass state, and the data transmission device 4 is in the loopback state. Data transmission line 1 → 2 → 3 patterns that are not interrupted by the clock signal output to the system side
→ 4 → 1 As a result, the signal on the clock detection signal line 301 of the data transmission device 1 is in the ON state. Therefore, the processor 33 of the data transmission device 1 resets the bit 1 of the status, sets the bit 3 to store the status in the storage unit 34, and ends the processing. That is,
The data transmission device 1 is in a loopback state in which the second loop system is received and the first loop system is set to the transmission side.

As described above, the data transmission apparatus of the present invention receives the data of all 0s from the first loop system transmission lines 11-14, but clocks the second loop system transmission lines 21-24 after a certain time. When a signal that does not cause a signal interruption cannot be detected, a failure in the second loop system transmission lines 21 to 24 is recognized. The occurrence of this situation is held in the second bit of the status information in the storage unit 34. Therefore, by reading the status information, the first loop transmission line
It is possible to know that a failure has occurred in both 11 to 14 and the second loop transmission lines 21 to 24, and the location of the failure. Furthermore, when the above situation occurs, the transmission line is reconfigured into a loopback connection. The device in which the above situation occurs is the end of loopback A. In addition, even though all the 0 data is received on the second loop system transmission lines 21 to 24, the device which cannot receive the signal which does not cause the clock disconnection on the first loop system transmission line after a certain time is a loopback. It becomes the end of B. Therefore, by reading the status information of each device, it is possible to determine which device is loopback A and B. FIG. 6 shows the final state when the loop transmission lines 14 and 21 are broken.

Next, the clock signal loss detection circuit 91 will be described in detail. Now, when the receivable flip-flop 102 is set, the signal on the signal line 321 is turned on, and the input data and the input from the first photoelectric conversion circuit 30 are input via the lines 52 and 51, the receiver 411 and the NAND gate 402. The clock is given and the counter 111 operates. The counter 111 continues counting if the input data 52 from the photoelectric conversion circuit 30 is a logical value "1", is reset if the logical value "0", and the value of the counter 111 is "T0". ", A pulse is generated. That is, when the clock is off, a pulse is generated because the logical value "1" is continuously generated, but in other cases, the pulse is not generated because the logical value "0" is reset. On the other hand, the counter 112 starts counting because the signal of the receivable state signal 321 is in the ON state, but when the value of the counter 111 becomes T0 or the connection state flip-flop 110 is set, the counter 112 1
12 is reset. A pulse is generated when the value of the counter 112 reaches "T1". As a result, the connection state flip-flop 110 is set. That is, in the clock-off state, the pulse is input from the counter 111 and the counter 112 is reset. Therefore, the connection state flip-flop 110 is not set. In this way, the flip-flop 11 can be operated by the functions of the counter 111 and the counter 112.
By turning on the signal of the clock detection signal 301, which is the output of 0, the connection state of the loop transmission line is changed to the processor 33.
Let us know.

With the connection status flip-flop 110 set,
When the internal clock 315 is applied and the input data is the logical value "1", the counter 113 counts. The counter 113 is reset if the input data is the logical value "0". Then, when the value of the counter 113 becomes “T2”,
Generates pulse and disconnects clock signal Flip-flop 11
4 is set. That is, after the connection state flip-flop 110 is set, the pattern of all 1 is “T2 ×
(Internal clock cycle) ”is detected continuously, and it is determined that a clock signal interruption has occurred. Therefore, in response to the setting of the clock signal disconnection flip-flop 114, the interrupt signal of the signal line 82 is turned on to notify the processor 33 of the occurrence of the clock signal disconnection.

On the other hand, when the flip-flop 110 is set and the input data is the logical value "0", the counter 123 counts. The count 123 is reset in response to the logical value "1" of the input data. If the input data of the logical value "1" does not come in by the time the counter 123 reaches the value of "T3" and it reaches the value of "T3", the clock signal disconnection flip-flop
124 is set. That is, after the connection state flip-flop 110 is set, the pattern of all 0 is "T3
It is determined that the specific pattern has occurred because the pattern continues for a time of "(internal clock cycle)". Therefore, in response to the setting of the clock signal disconnection flip-flop 124, the interrupt signal of the signal line 71 is turned on, and the processor 33 is notified of the occurrence of the specific pattern. In the description of FIG. 4, the counter 113 counts the input data as the logical value "1", but if the photoelectric conversion circuit directly detects a failure and there is a signal that turns on during this time, this If the signal is replaced as the input data, the counter 113 operates in the same manner as above.

Next, as a pattern in which the clock signal is not interrupted (the signal is valid), a block diagram in which the value of the logical value "1" is continuously suppressed within T0 is shown in FIG. 9 and described below. The reference number order 511 is a clock signal line for giving a clock for transmission, the reference number 501 is a counter, the reference number 513 is a line for outputting 1 bit of the counter value, and the reference number order 502.
Is a selector, and reference numeral 512 is a line for transmitting a pattern that does not cause a clock signal interruption at the output of the selector. Now, the selector 502 outputs the output signal line 512 '0' in response to the value "0" of the line 513 and outputs "1" to the output signal line 512 in response to the count value "1" of the line 513. Therefore counter 5
If the clock signal is constantly given to 01 via the clock signal 511, a continuous pattern can be repeatedly generated.
In this case, the counter 501 is a circuit in which the even number of "1" of "111 ... 1" is within the constant T0. The operation of each of the above data transmission devices is the operation shown in the flowchart of FIG. Clock reception in FIG. 7 means that the received signal is effective. However, when the bypass is considered in the photoelectric conversion circuit 30, the signal of the bypass signal line 56 is the transmission clock line 54 when the signal is on, the transmission data 55 is ignored, and the input signal of the photoelectric conversion circuit 30 is directly used as the output signal. It means going out in a loop.

In the above example, the reception clock line 51 and the reception data line 52 are valid even during bypass. Further, generation of a pattern due to abnormality detection due to a failure of the photoelectric conversion circuit, and loop switching, loopback due to the failure of the data transmission device connected upstream of the transmission path or the intentional occurrence of a specific pattern other than the above example, Obviously, fault detection is also included in the present invention.

Advantageous Effects of the Invention According to the present invention, when a signal loss or a specific pattern is detected, a specific pattern different from the signal loss is output to the operation system, the input / output is switched to the standby system, and the signal loss is detected if the signal is disconnected. By storing the information, there is an effect that the entire system can be automatically re-looped and an error point can be automatically detected.

[Brief description of drawings]

1 is a diagram showing a loop transmission system to which the present invention is applied, FIG. 2 is a diagram showing an embodiment of the present invention, FIG. 3 is a diagram showing an example of the transmission line control circuit of FIG. 2, FIG. 4 is a diagram showing an example of the clock signal loss detection circuit of FIG. 3, FIGS. 5 and 6 are diagrams showing a loop-shaped transmission system after the present invention is carried out, and FIG. 7 is applied to the present invention. FIG. 8 is a diagram showing the shape of a general frame, FIG. 8 is a diagram showing the format of status information showing the connection status and failure information of the data transmission apparatus applied to the present invention, and FIG. 9 is the transmission / reception of FIG. FIG. 10 is a diagram showing a part of the circuit, and FIG. 10 is a diagram for explaining the operation of one embodiment of the present invention. 1 to 10, 1 to 4 ... data transmission device, 11 to 14, 21 to 24 ... transmission line, 30, 31 ... photoelectric conversion circuit, 51, 52, 54 to 56, 61, 62, 64-66, 71, 81-89,
301, 311, 312, 315 to 319, 321, 322, 511 to 513 ... Signal line, 32 ... Transmission line control circuit, 33 ... Processor, 34 ...
... memory section, 91 ... clock loss detection circuit, 92 ... transmission / reception circuit, 94 ... clock generator, 101-103, 201-203, 11
0, 114, 124 ... Flip-flop, 111-113, 123, 50
1 ... Counter, 401-403 ... Gate, 411 ... Receiver, 502 ... Selector.

Continuation of front page (56) Reference JP-A-57-3153 (JP, A) JP-A-51-3509 (JP, A) JP-A-56-149850 (JP, A) JP-A-55-147850 (JP , A) JP-A-55-134560 (JP, A) JP-A-57-87648 (JP, A)

Claims (2)

[Claims] 1. A data transmission device in which a plurality of units are connected to a loop-shaped transmission line including an active transmission line and a standby transmission line, wherein a first pattern indicating disconnection of a received signal from the active transmission line. And a second detection means for detecting reception of a second pattern for switching to the standby transmission line, which is different from the first pattern from the active transmission line. Detection means and, when the first detection means detects the first pattern or when the second detection means detects the second pattern, the second pattern in the working transmission path. And a first sending means for sending a third pattern, which is an effective signal that is neither the first pattern nor the second pattern, to the standby system transmission line, and the first detecting means. The first pattern When it is detected or when the second detection means detects the second pattern, first switching means for switching to the standby system transmission line on both the transmitting and receiving sides, and the first detection means for the active system transmission. The first from the road
If the storage means stores the detection of the pattern and the content of the storage means is read to detect the first pattern, there is an abnormality on the receiving side of the operational transmission line of the data transmission apparatus. A data transmission device comprising: means for notifying that the data has occurred. 2. A data transmission device in which a plurality of units are connected to a loop-shaped transmission line including an active transmission line and a standby transmission line, wherein a first pattern indicating disconnection of a received signal from the active transmission line. And a second detection means for detecting reception of a second pattern for switching to the standby transmission line, which is different from the first pattern from the active transmission line. Detection means and, when the first detection means detects the first pattern or when the second detection means detects the second pattern, the second pattern in the working transmission path. And a first sending means for sending a third pattern, which is an effective signal that is neither the first pattern nor the second pattern, to the standby system transmission line, and the first detecting means. The first pattern Third detection means for detecting the reception of the third pattern from the standby transmission path after a predetermined time has elapsed after the detection or the second detection means detected the second pattern, First switching means for switching to the standby transmission path on both the transmitting and receiving sides when the first detecting means detects the first pattern or when the second detecting means detects the second pattern And the first detection means is configured to transmit the first signal from the active transmission line.
Storage means for storing that the third pattern has been detected or that the third detection means has not detected the third pattern, and when the third detection means has not detected the third pattern. Second switching means for performing a loopback connection in which the active transmission path is the reception side and the standby transmission path is the transmission side, and the third detection means does not detect the third pattern. Sometimes, second sending means for sending a second pattern to the standby system transmission path, fourth detecting means for detecting reception of the second pattern from the standby system transmission path, and the fourth And a third sending means for sending the second pattern to the standby system transmission path and the third pattern to the working system transmission path when the detecting means detects the second pattern. , The third sending means is Fifth detecting means for detecting reception of the third pattern from the operational transmission line after a predetermined time has passed after transmitting the third pattern, and the fifth detecting means does not detect the third pattern And a third switching means for performing a loopback connection in which the active transmission path is the transmission side and the standby transmission path is the reception side, and the storage means includes the third detection means and the third detection means. The data transmission device further comprising means for storing that the pattern No. 3 has not been detected and for reading the contents of the storage means to notify that an abnormality has occurred in the transmission path.