JPH0795615A - Digital chroma signal processing method - Google Patents

Abstract

PURPOSE:To dispense with the complicated address control by thinning out two color difference signals which are sampled in the frequency of an integer multiple as high as the frequency of a horizontal synchronizing signal based on a signal divided by a specific integer and then multiplexing both color difference signals in time division. CONSTITUTION:The low-band converted chroma signal applied to a terminal 1a is demodulated into two color difference signals by a demodulating circuit 101 based on the carrier signal applied to a terminal 1c. Then the demodulated two color difference signals are thinned out to 1/4 by a thinning out circuit 104 through the LPF 102 and 103 and then multiplexed. These multiplexed two color difference signals are processed by a comb-line filter 105 and a reproduction processing circuit 106 and then interpolated into the quadruple frequency, for example, by an interpolating circuit 107. The interpolated color difference signals are modulated by a modulating circuit 110 through the LPF 108 and 109. Thus the reproduced chroma signals are acquired. The circuits 104 and 107 are controlled by the flag signal produced by a flag signal generating circuit 111. Then the memory stage number of the filter 105 is set at 455 per line since the color difference signals are thinned out by the circuit 104 based on the flag signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital color signal processing method for transmitting a video signal such as a video tape recorder (hereinafter referred to as VTR) or a television, which mainly handles color difference signals by time division multiplexing. Is.

[0002]

2. Description of the Related Art In recent years, VTRs having a high image quality by applying digital signal processing technology to video signals have been announced one after another.

Many of these improve the noise removal effect by performing inter-line processing or inter-field processing, and some of them improve the basic performance by digitizing all recording / reproducing processing.

Although none of the above processes can be realized without the progress of semiconductor processes, it goes without saying that efficient use of memory is indispensable for executing a compact LSI design. Yes.

Since the color signal has a narrower band than the luminance signal, it is possible to perform processing with a lower sampling frequency.

Therefore, as long as the sampling theorem is satisfied, it is possible to perform thinning-out processing to a fraction, and the memory usage capacity can be reduced in proportion to the thinning-out ratio. If such thinning is not performed, the sampling points in the vertical direction are displaced, and the vertical arithmetic processing represented by the comb filter cannot be performed correctly.

This will be described with reference to the simple timing chart shown in FIG. FIG. 4A shows a sampling clock, and FIG. 4B shows a signal sampled by the above clock.

FIG. 4 (d) shows a case where the signal shown in FIG. 4 (c) obtained by dividing the sampling clock of FIG. 4 (a) by two is at "H" level. The data string in which the data of b) is selected is shown.

A data string obtained by continuously thinning out the data of the (n + 1) th line following the nth line is shown next.

In order to simplify the explanation, the data symbols between the lines are the same. As described above, if the data of 9 lines / line is thinned out based on the signal obtained by dividing the sampling clock by half, the continuity of the data is maintained one-dimensionally. It can be executed without problems.

However, when viewed two-dimensionally,
Originally (nth line data, n + 1th line data)
Should be (D0, D0), (D2, D2), ..., but the data phase is shifted by one clock (D
Since 0, D8), (D0, D1), ..., Vertical calculation cannot be performed as it is.

Therefore, when two-dimensionally processing the data thinned out by such a method, it is necessary to align the write start timing of the memory with the head of the video signal.

To solve this problem, conventionally, the horizontal synchronizing signal was used as a trigger to reset the timing of thinning out video signals at the beginning, and an operation was performed so that sampling points in the vertical direction were aligned.

However, if such a process is adopted, the number of sampling data of one line may be different, and it becomes necessary to control the address of the memory according to the excess or deficiency from the reference data number.

One means for solving the above problems by digitizing and processing the VTR color signal is disclosed in, for example, Japanese Patent Publication No. 4-38195, "Video Signal Digital Processing Method".

A conventional video signal digital processing method will be briefly described below. In this conventional example, a method of performing signal processing in almost the same circuit is provided by utilizing the similarity of both NTSC and PAL which are the current television broadcasting systems.

That is, the subcarrier frequencies of the NTSC and PAL color signals are both converted to a common frequency, and the signal processing is performed by thinning out the data to one third.

As a result, the memory capacity of, for example, the comb filter is reduced to one third, and it is possible to sufficiently supplement the increase in circuits required for the thinning process.

The condition for thinning to one third is that the sampling frequency is N times the horizontal synchronizing signal frequency (N is an integer), and the integer N is divided by 4 to obtain N = 4K + M.
(K is an integer and M is any one of 0, 1, 2, and 3), and similarly, the integer N is divided by 3 to obtain N = 3L + Q (L is an integer, Q is either 0 or ± 1). And P = M
This is to select N such that the integer P of + Q is an even number.

By selecting such a frequency,
Even if the sampling point in the vertical direction shifts because N is not a multiple of 3 and is thinned out to 1/3, it becomes data of 1 clock, and since it has a phase, it can be configured as a comb filter. I am trying.

[0021]

However, in the above-described conventional configuration, the sampling frequency is limited, and therefore, for example, in the NTSC system, the 4
There is a problem that the clock frequency of fsc (fsc is a color subcarrier frequency) cannot be used, and the baseband signal (two color difference signals) cannot be handled, so that it is very difficult to achieve consistency with peripheral circuits. Was there.

The present invention solves the above-mentioned problems of the prior art. A sampling frequency that is frequently used can be selected, color signal processing can be performed in the form of a color difference signal, and the data is thinned to a fraction of 0.5. SUMMARY OF THE INVENTION An object of the present invention is to provide a digital color signal processing method capable of performing vertical processing such as a comb filter without requiring memory address control even when the above occurs, and further reducing the memory usage capacity.

[0023]

In order to achieve this object, a digital color signal processing method of the present invention uses a clock frequency for sampling two color difference signals n times the horizontal synchronizing signal frequency (n is a positive integer). And n / m = k +
The polarity of the first frequency-divided signal divided by the integer value m satisfying the relationship of 0.5 (m is a positive integer and a multiple of 2, k is a positive integer) is a value twice the integer value n. The present invention provides a method of thinning out the two sampled color difference signals by time division multiplexing and transmitting the thinned color difference signals by using a flag signal whose inversion / non-inversion is switched by a second divided signal.

[0024]

According to the present invention, two color difference signals sampled at n times the horizontal synchronizing signal frequency are converted into
/M=k+0.5 The first frequency-divided signal divided by an integer value m satisfying the relationship of /m=k+0.5 is thinned out and time-division multiplexed.

At this time, since n / m does not take an integer value, the sampling points in the vertical direction are displaced when simply thinned out. Therefore, the second frequency division signal divided by the integer value 2n causes the first division for each line. Inverts the polarity of the frequency signal.

As a result, since the timing of the thinning process changes, it is possible to realize the transmission in the signal form in which the sampling points in the vertical direction coincide with each other even if a fraction of 0.5 occurs, so that special address control for the memory is performed. Does not need

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A digital color signal processing method of the present invention will be described below with reference to the drawings.

When the color signal is digitized and processed,
Particularly in the NTSC system, a sampling frequency of 4 fsc (fsc is a color subcarrier frequency: 14.3 MHz) is adopted.

This is because the frequency is suitable for performing the so-called Y / C separation for separating the color signal and the luminance signal during the recording processing by the digital processing. Therefore, considering the modulation of the color difference signal during the reproduction processing, this sampling is performed. It is common to use frequency.

Therefore, the sampling frequency n is set to 4fsc =
Set to 910fH (fH is the horizontal sync signal frequency) and n /
4. Select 4 as an integer value m that satisfies m = k + 0.5.

When data is thinned out in this setting, the timing normally becomes as shown in FIG.

FIG. 1A shows a sampling clock of 4 fsc, and FIGS. 1B and 1C show two color difference signals sampled by the above clock.

FIG. 1E shows a data string obtained by time-division-multiplexing the data shown in FIGS. 1B and 1C when the signal shown in FIG. 1D is at "H" level. Is represented.

That is, this is (R0, B0), (R
2, B2), ..., (R908, B908) is a time-division multiplexed data string of 455 color difference signals thinned out by half.

Further, FIG. 1 (g) is obtained when the signal shown in FIG. 1 (f) obtained by dividing the sampling clock of FIG. 1 (a) by 1/4 is at "H" level. The data of (e) is selected to represent a time-division multiplexed data string.

That is, this is (R0, B0), (R
4, B4), ..., (R904, B904), R90
It is a time-division multiplexed data string of 227 + 0.5 color difference signals thinned out to a quarter by 8 combinations.

Next, in the processing of the (n + 1) th line following the processing of the (n) th line of (b) to (g) of FIG. 1, when the signal of (f) of FIG. B908,
A combination of (R2, B2), ..., (R906, B906) forms a time-division multiplexed data string of 227 + 0.5 color difference signals decimated to a quarter.

In order to simplify the explanation, the data symbols (R0, B0, etc.) between the lines are the same.

As described above, when 910 pieces / line of data are thinned out based on the signal obtained by dividing the sampling clock by 1/4, the continuity of the data is maintained one-dimensionally, so that the horizontal direction is maintained. The operation of can be executed without any problem.

However, when viewed two-dimensionally,
Originally (nth line data, n + 1th line data)
Where (R0, B0), (R4, B4), ... should be (R0, B908), (B0, R2),
.., the calculation in the vertical direction cannot be performed as it is.

Even if one data is shifted (R
0, R2), (B0, B2), and so on, which is an operation with data separated by two sampling points, which also poses a problem in terms of accuracy.

That is, the same problem as shown in FIG. 4 occurs. FIG. 2 is a timing chart for explaining the operation of the digital color signal processing method of the present invention which solves the above-mentioned problems.

2A, 2B and 2C are the same as FIGS. 1A, 1E and 1F.

In the method shown in FIG. 1, since 910 pieces of data are continuously thinned out by a signal obtained by dividing the data by a quarter, the polarities are inverted at the beginning of each line, and the data are not aligned in the vertical direction.

Therefore, the polarity of the 1/4 frequency-divided signal shown in (d) of FIG. 2 is reversed by the 1/8 frequency-divided signal shown in (d) of FIG. If
The data will be aligned at the beginning of each line.

For example, if the polarity of (d) of FIG. 2 is "H" level, it is inverted, the head data of the data of the nth line and the data of the (n + 1) th line are both (R0, B0).

Moreover, if the present method is applied to the data string of FIG. 4, the data frequency becomes 2 at the boundary where the polarity of the divided signal is inverted.
As for the doubled problem, since the time division multiplexing causes the continuity of the multiplexing to be lost, the data frequency is constant and no problem occurs.

FIG. 3 shows a color signal processing apparatus realized by using the digital color signal processing method of the present invention, in which the sampling clock is 4 fsc and the thinning processing is 1/4.

The low-frequency conversion color signal applied to the input terminal 1a is demodulated into two color difference signals by the demodulation circuit 101 based on the carrier signal applied to the input terminal 1c.

The two demodulated color difference signals are band-limited by the low-pass filters 102 and 103, and then thinned out to 1/4 by the thinning circuit 104 and multiplexed.

The two multiplexed color difference signals are processed by the comb filter 105 and the reproduction processing circuit 106 for controlling the phase direction and the amplitude direction, and are interpolated by the interpolation circuit 107 to a frequency four times higher.

Then, the low-pass filters 108 and 109
After being band-limited, the signal is modulated by the modulation circuit 110 to obtain a reproduced color signal at the output terminal 1d.

Here, the thinning circuit 104 and the interpolation circuit 107 are controlled by the flag signal generated by the flag signal generating circuit 111.

In the flag signal generating circuit 111, the input terminal 1
The horizontal synchronizing signal given to b is divided to generate a signal corresponding to (d) of FIG. 2, and the sampling clock is divided by 1/4 according to its polarity to switch between inversion / non-inversion of the signal. , Is output as a flag signal.

Since the thinning-out circuit 104 thins out the data shown in FIG. 2 based on this signal, the number of memory stages of the next comb filter 105 is 455 for one line.

That is, 227 for one color difference signal.
Since +0.5 stages of memory are required, by multiplexing two signals, an integer of 455 stages is obtained, which eliminates the need for address control or the like.

Further, the interpolation circuit 107 needs a flag signal in order to increase the frequency four times and output the signal by dividing it into two signals. This signal takes into consideration the processing delay of the comb filter 105 and the reproduction processing circuit 106. It has become a thing.

[0058]

As described above, according to the present invention, the clock frequency for sampling the two color difference signals is set to n times the horizontal synchronizing signal frequency (n is an integer), and n / m = k + 0.5 (m
Is a positive integer and a multiple of 2, and k is a positive integer. The polarity of the divided signal divided by an integer value m that satisfies the relation
Using the flag signal, which has been switched between inversion and non-inversion with a frequency-divided signal that is divided by a doubled value, the two sampled color difference signals are thinned out, time-division multiplexed, and the number of data thinned out by transmission is 0. Even if there is a fraction of 5, the data fraction is constant and the sampling points in the vertical direction are aligned, so the memory such as the comb filter may be a mere shift register, and it is not necessary to perform complicated address control.

Further, since it is possible to reduce the number from the integral part to a half, the used capacity of the memory can be further reduced to a half.

[Brief description of drawings]

FIG. 1 is a timing chart for explaining the operation principle of a digital color signal processing method of the present invention.

FIG. 2 is a timing chart for explaining the operation principle of the digital color signal processing method of the present invention.

FIG. 3 is a block diagram of an embodiment of a circuit to which the digital color signal processing method of the present invention is applied.

FIG. 4 is a timing chart for explaining the operating principle of a conventional digital color signal processing method.

[Explanation of symbols]

 101 Demodulation circuit 102, 103, 108, 109 Low-pass filter 104 Decimation circuit 105 Comb filter 106 Reproduction processing circuit 107 Interpolation circuit 110 Modulation circuit 111 Flag signal generation circuit

Claims (1)

[Claims] 1. A clock frequency for sampling two color difference signals is set to n times the horizontal synchronizing signal frequency (n is a positive integer), and n / m = k + 0.5 (m is a positive integer and 2).
And the polarity of the first frequency-divided signal divided by an integer value m satisfying the following relationship is inverted by a second frequency-divided signal obtained by dividing the polarity of the first frequency-divided signal by a value twice the integer value n. A digital color signal processing method characterized by thinning out the two sampled color difference signals using a flag signal whose non-inversion is switched, time division multiplexing and transmitting.