JPH0793215A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To provide the semiconductor memory which eliminates unmatching between data held in a cache memory and data held in a main memory and can consist of a main storage device at high operating speed in a computer system using the cache memory. CONSTITUTION:Concerning the semiconductor memory for which a write buffer 7 to be operated at high speed for temporarily storing a write address and write data applied form the outside and a large storage capacity DRAM with comparatively low-speed operations are integrated on the same substrate and when the semiconductor memory is not accessed from the outside, the write buffer 7 can transfer the stored write address and write data to the DRAM and can update the transferred write address and write data after the transfer. Therefore, since write to a main memory 4a can be performed at high speed, even in the case of a write through system, system speed is not decelerated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device which is convenient for use as a main memory (main memory) of a computer system.

[0002]

2. Description of the Related Art A main memory is indispensable for a computer system. The main memory is usually a DRAM (Dynamic RA
M). Since the operating speed of this DRAM is considerably slower than the operating speed of the CPU, the waiting time of the CPU is increased and the operating efficiency of the CPU is lowered. In order to avoid this, a cache memory (buffer) which has a small storage capacity but operates at high speed is interposed between the CPU and the main memory. In a computer system having this cache memory, a data part that the CPU frequently accesses is copied from the main memory in advance,
The CPU accesses the high speed cache memory instead of accessing the main memory.

FIG. 3 shows a connection relationship between a CPU and a memory of a computer system having such a cache memory. In the figure, when an access from the CPU 1 to the memory occurs, first, an address signal is sent from the CPU 1 to the address bus 5. The cache memory 2 fetches the sent address signal, and determines whether or not it is an access to the data already stored in the cache memory 2. When the data is the data stored in the cache memory 2, the cache memory 2 closes the gate 3 of the address bus 5 and the data bus 6 to prevent data transmission / reception between the CPU 1 and the main memory 4. As a result, the CPU 1 accesses the cache memory 2. When the data is not stored in the cache memory 2, the gate 3 is opened by the cache memory 2 and the CPU 1 accesses the main memory 4. The control method of the cache memory 2 is roughly classified into
There are two types of write-through and write-back shown below.

In the write-through method, when the cache memory 2 is hit in the memory read cycle, that is, when the cache memory 2 holds the same data as the main memory 4 and the data is read. , CPU 1 reads data from cache memory 2. When the cache memory 2 misses in the memory read cycle, that is, when the data to be read is not in the cache memory, the data is read from the main memory 4 and the data is written in the cache memory 2. In the memory write cycle of this method, when the cache memory 2 is hit, that is, when the cache memory 2 has the data of the address of the main memory to be rewritten, the CPU 1 stores the data in both the cache memory 2 and the main memory 4. Write data. When the cache memory 2 misses, that is, when the cache memory 2 does not have the data of the address of the main memory to be rewritten, the writing to the main memory 4 is performed.

On the other hand, in the write-back method, when the cache memory 2 is hit in the memory read cycle, the CPU 1 reads data from the cache memory 2 as in the write-through method. When a miss occurs, the data having a low access frequency is selected from the data stored in the cache memory 2. When the selected data is the data that has been rewritten by the hit of the write cycle, the selected data is written to the main memory 4 and then erased to free the storage location of the cache memory 2. Further, if the data has not been rewritten in the write cycle, the data is erased as it is to free the storage location of the cache memory 2. Then, the data is read from the main memory 4 to the CPU 1, and the read data is written in the empty space of the cache memory 2.

In the memory write cycle of this system, when the cache memory 2 is hit, the CPU 1 writes data only to the cache memory 2 and not to the main memory 4. When the cache memory 2 is missed, the data having a low access frequency is selected from the data stored in the cache memory 2. When the selected data is the data that has been rewritten by the hit of the write cycle, the data is written to the main memory 4 and then erased to free the storage location of the cache memory 2. Further, if the data has not been rewritten in the write cycle, the data is erased as it is to free the storage location of the cache memory 2. Then, the write data from the CPU 1 is written into the empty space of the cache memory 2.

[0007]

In a computer system having such a cache memory, in the case of a read cycle, copy data in the main memory can be read out from the cache memory at high speed. However, in the write cycle, writing to the low-speed main memory is always required, and the following problems occur.

In the write-back method, since it is sufficient to access the cache memory in the case of hits in both read and write cycles, the system can operate at high speed as long as the hits continue. However, in a write cycle hit, only the cache memory is rewritten, so the contents of the data in the main memory and the data held in the cache memory differ. In this case, the master unit (CP
Although there is no problem in a system in which one unit that directly accesses the memory such as U and DMA is used, in a multi-master system, since multiple master units directly access the shared main memory, the data in the main memory and the cache memory are the same. Sex matters.

In the write-through method, when a hit occurs in the memory write cycle, writing is performed in both the cache memory and the main memory, so the cache memory is always a copy of the main memory. For this reason, the problem of the sameness of the data in the cache memory and the data in the main memory unlike the write-back method does not occur.

However, in the write cycle, the main memory is always written in addition to the cache memory. Therefore, when the write cycle continues twice or more, the operation speed of the system must be slowed down in accordance with the write speed of the main memory. I have to.

As described above, the write-back method can prevent a decrease in speed by reducing the number of times of writing to the main memory having a slow writing speed, but the contents of the cache memory and the main memory are kept the same. Absent. Therefore, it is difficult to use in a system composed of multiple masters. Further, the write-through method can maintain the same data contents in the cache memory and the main memory, but has a problem that the number of times of writing in the main memory increases and the operation speed of the system slows down.

Therefore, according to the present invention, in a computer system using a cache memory, there is no inconsistency between the data held in the cache memory and the data held in the main memory, and a main storage device having a high operation speed is constructed. It is an object of the present invention to provide a semiconductor memory device capable of performing the above.

[0013]

In order to achieve the above object, a semiconductor memory device of the present invention has a high speed operation write buffer for temporarily storing an externally supplied write address and write data, and a relatively low speed write buffer. Dynamic and high capacity DRAM
And the semiconductor memory device integrated on the same substrate, the write buffer transfers the stored write address and write data to the DRAM when the semiconductor memory device is not accessed from the outside. , It is possible to update the transferred write address and write data after transfer,
It is characterized by

[0014]

The semiconductor memory device has a structure in which a write buffer capable of high-speed operation is incorporated in a DRAM used as a main memory device (main memory) of a computer. When writing data to the memory, high-speed writing to the write buffer is performed. Data transfer from the write buffer to the cell array is performed when the main memory is in the standby state. Generally 90 in a system with cache memory
% Or more memory accesses are made to the cache memory, and the main memory is in the standby state during that time.

When writing to the main memory can be performed at high speed, the system speed does not slow down even in the write-through method.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the semiconductor memory device of the present invention will be described below with reference to FIG. In the computer system shown in the figure, parts corresponding to those in FIG. 3 are designated by the same reference numerals, and description of such parts will be omitted. The semiconductor memory device of the present invention is provided as a main memory 4a having a write buffer in the configuration of a computer system having a cache memory similar to the conventional one. Main memory 4a
Is a large-capacity DRAM formed on the same semiconductor substrate
And a write buffer that operates at high speed.

FIG. 2 shows the configuration of the main memory 4a. The DRAM is a data bus 11, a memory cell array 12, a row address bus 13, and a column address bus 1.
4, address buffer 15 and data input / output buffer 1
It is composed of 6 and the like. The write buffer 7 is a DRAM
High-speed operation data buffer 8 for temporarily storing data to be written to, high-speed operation tag buffer 9 for storing an address for the data, and write buffer control circuit 1
It is composed of 0 and the like. The data buffer 8 of the write buffer 7 is connected to the data bus 11 of the DRAM in parallel with the memory cell array 12. The memory cell array 12 is connected to the row address bus 13 and the column address bus 14.
The tag buffer 9 of the write buffer 7 is connected in parallel with a decoder (not shown). The control circuit 10 is composed of a write / read circuit for a write buffer, an address comparison circuit, and the like.

Next, the operation of the main memory 4a will be described. The main memory 4a is the semiconductor memory device 4 is D
In addition to the write operation mode and the read operation mode as the RAM, the write data transferred from the CPU 1 or the cache memory 2 is once written in the write buffer 7 at a high speed,
A transfer operation mode for moving write data from write buffer 7 to memory cell array 12 is provided.

First, in the write operation mode to the main memory 4a, the data to be written to the main memory 4a is transferred from the CPU 1 (or from the cache memory 2). A write command is given from the CPU 1 to the memory 4, and C
The address signal and the data signal output from PU1 are the address buffer 15 and the data input / output buffer 16, respectively.
Is taken into. Next, the control circuit 10 of the write buffer 7
And the write address held in the address buffer 15 by
The comparison with the tag data stored in the tag buffer 9 is performed. When the matching tag data is held, that is, when there is a hit, the data input / output buffer 1 is stored in the storage position of the data buffer 8 which is paired with the tag data.
The data held in 6 is written. When there is no matching tag data, that is, when there is a miss, if there is a vacancy in the buffer area of the write buffer 7, the data and address to be written are written in the data buffer 8 and the tag buffer 9, respectively. At this time, the memory cell array 1
2 is kept in the standby state by the control circuit 10. When the buffer area of the write buffer 7 does not have a space for temporarily holding the data to be written, the writing is performed to the normal memory cell array 12, and the memory cell array 12 stores the data at the address given by the address buffer 15. The data held in the output buffer 16 is written. DRAM including memory cell array 12 and the like
The operation of is known and will not be detailed here.

The data transferred from the CPU 1 to the main memory 4a and temporarily stored in the write buffer 7 is transferred from the write buffer 7 to D while the main memory is not accessed.
It is transferred to the RAM and stored. In a computer system having a cache memory, the hit rate to the cache memory (the ratio of access from the cache memory to all memory access times) is generally 90% or more. Further, the usage rate of the external bus including the write time in the write-through method is 50% or less. For this reason, in a computer system having a cache memory, the main memory 4a is kept at 5 even during system operation.
It is in a standby state for 0% or more and has not been used during that time. Utilizing this idle time in the standby state, C
The data group transferred at high speed from PU1 is transferred from write buffer 7 to DRAM. As a result, the apparent DR
The AM write operation is speeded up.

In the transfer mode from the write buffer 7 to the memory cell array 12 following the write operation mode to the main memory 4a, the control circuit monitoring the existence of the write command or the read command to the main memory 4a is If neither command exists, the write buffer 7 is caused to perform the read operation and the memory cell array 12 is caused to perform the write operation. Address data is output from the tag buffer 9 of the write buffer 7 to the address buses 13 and 14, and the memory cell array 1
The write address of the data input to 2 is specified. Data corresponding to the address data is read from the data buffer 8 to the data bus 11 and written in the memory cell array 12. After that, the transferred data is erased from the write buffer 7 and the buffer is emptied. If there is an access from the CPU 1 during execution of this transfer mode, the transfer mode is suspended. When it is a data write command, the write operation mode is given priority and the supplied write data is accepted. When it is a data read command, priority is given to execution of a read operation mode described later.

The method of selecting the data to be transferred to the cell array from the plurality of data stored in the write buffer is up to the designer of this memory device. For example, FI
It may be a FO (First-In First-Out) cyclic buffer. Further, instead of positively erasing the data in the write buffer that has been transferred to the DRAM, a flag can be used to determine whether or not the data can be updated. For example, CPU1
When the data is fetched from the write buffer 7 to the write buffer 7, the write flag is set for each data or each data block,
By resetting the flag when the transfer to the memory cell array 12 is completed, it is possible to judge the remaining data to be transferred to the memory cell array 12, and to judge whether the data can be updated.

In the read operation mode from the main memory 4a, the control circuit 10 compares the tag data stored in the tag buffer 9 with the read address given from the CPU 1. When there is matching tag data in the write buffer 7 (hit), the data is read from the storage position of the data buffer 8 which is paired with the tag data. The read data is not yet stored in the memory cell array 12. The read data is output to the external bus 6 via the data bus 11 and the input / output buffer 16. Simultaneously with this operation, the memory cell array 12 enters the write operation, and the data of the write buffer 7 output to the data bus 11 is taken in internally, and the address bus 1
It stores in the address output to 3 and 14. After that, the read data in the write buffer 7 is erased, or the write flag is reset to empty the buffer. If there is no matching tag data in the write buffer 7 (miss), the normal memory cell array 1
Data is read from the DRAM operation from 2. Thus, a semiconductor memory device having a large-capacity, relatively low-speed DRAM and a small-capacity, relatively high-speed write buffer is used as the main memory of a computer system having a cache memory.

In the main memory using this semiconductor memory device, continuous high-speed writing of the size of the write buffer is possible. When a write cycle occurs in the write-through method, execution can be continued without reducing the system speed as long as the write buffer has a free space. Also,
As described above, while the access from the master unit hits the cache memory, the main memory is in the standby state, and the free time is used to transfer from the write buffer to the cell array. As described above, in a computer system having a cache memory, the hit rate to the cache memory is generally 90% or more. Further, since the usage rate of the external bus including the write time in the write-through system is 50% or less, the data consistency between the cache memory 2 and the main memory 4a is maintained, and the computer does not slow down in the write cycle. The system becomes possible.

Although not particularly shown and described, as compared with a semiconductor memory device having a cache-DRAM structure in which the cache memory 2 and the main memory 4 are directly combined,
Since only the write buffer is used, the buffer capacity can be small, the merit of large storage capacity of the DRAM can be maintained, and the time for occupying the external buses 5 and 6 for data transfer can be reduced.

Further, in the embodiment, the memory cell array is a dynamic RAM, but the present invention can be applied to other RAMs.

[0027]

As described above, the semiconductor memory device of the present invention includes a high speed write buffer memory in addition to the DRAM. Therefore, if this is used in a computer system using a cache memory, for example, Since the contents written in the write buffer memory are copied to the DRAM while the memory is being accessed, there is no mismatch between the data held in the cache memory and the data held in the main memory, and the operation speed is fast. It becomes possible to configure the main storage device.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a computer system having a cache memory using a semiconductor memory device of the present invention.

FIG. 2 is a block diagram showing a configuration of the present semiconductor memory device (in the case of DRAM).

FIG. 3 is a block diagram showing a conventional configuration of a computer system having a cache memory.

[Explanation of symbols]

 1 CPU 2 cache memory 3 gate 4 main storage device (main memory) 5 address bus 6 data bus 7 write buffer 8 data buffer 9 tag buffer 10 write buffer control circuit 11 in-memory data bus 12 cell array 13 in-memory low address bus 14 In-memory column address bus 15 Address buffer 16 Data input / output buffer 17 Address input

Claims (2)

[Claims] 1. A semiconductor in which a high-speed operation write buffer for temporarily storing an externally supplied write address and write data and a DRAM having a relatively low speed operation and a large storage capacity are integrated on the same substrate. A memory device, wherein the write buffer transfers the stored write address and write data to the DRAM when the semiconductor memory device is not accessed from the outside, and the transferred write address after the transfer. And a write data updateable semiconductor storage device. 2. The write buffer searches for a corresponding write address and write data in response to a read command from the outside, and sends the searched write address and write data to the outside of the semiconductor memory device. 3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device outputs the data, transfers the data to the DRAM, and updates the transferred write address and write data after the transfer.