JPH0793031B2 - Access control system - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor memory technology, and more particularly to a technology particularly effective when applied to a read-only memory integrated into a semiconductor integrated circuit. For example, a memory cell for one column. The present invention relates to a technique effectively applied to an access control system including a so-called vertical ROM (read-only memory) in which are connected in series.

[Prior Art] Conventionally, a mask ROM which is one of non-volatile memories includes a so-called vertical ROM and a horizontal ROM. Of these, horizontal ROM
Is a system in which memory cells are arranged in parallel between a data line and the ground potential of a circuit, and high-speed reading can be performed. On the other hand, the vertical ROM is an M that constitutes each memory cell connected in series.
Since the diffusion layers as the source and drain regions of the OS transistor play the role of bit lines, it is unnecessary to connect the bit lines made of aluminum, polysilicon, or the like to each memory cell, that is, to provide the connection holes. Therefore, the vertical ROM is easier to achieve higher integration than the horizontal ROM.

[Problems to be Solved by the Invention] However, in the vertical ROM, the read speed is higher than that of the horizontal ROM because the stored information is read by passing a current through one column of memory cells connected in series. Will be considerably slower. On the other hand, the horizontal ROM is faster than the vertical ROM, but has a problem that it is difficult to achieve high integration and the chip size becomes large.

For the difference between the vertical ROM and the horizontal ROM, see Asakura Shoten Co., Ltd., June 30, 1981, "Integrated Circuit Application Handbook", pages 358 to 386.

The object of the present invention is to realize a mask RO that enables high integration and high speed.
It is to provide an access control system that can access M.

Another object of the present invention is to provide an access control system capable of accessing a mask ROM so that a substantial access time can be shortened.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[Means for Solving Problems] An outline of typical ones of inventions disclosed in the present application will be described below.

That is, in a vertical mask ROM in which MOS transistors forming memory cells are connected in series for each column in a memory cell array, a common sense amplifier is provided for each of a predetermined number of memory cell columns, and those sense amplifiers are provided. When there is a large address transition that changes the data held in the sense amplifier by providing a selection switch that selectively connects one of the above to the main amplifier and an address transition detection circuit. In other words, when the address signal for selecting the memory cell in the memory cell array is changed, in other words, the address signal other than the address signal for selecting the selection switch connected to the output of the sense amplifier is changed. In this case, a terminal for outputting a signal notifying it to the outside is provided. An access control system including a ROM such as the vertical mask ROM configured as described above further includes the R
Outputs an address signal for read access to the OM, and sets the read access cycle time from selection of the sense amplifier to output of read data, and input of a wait signal for delaying the fetch timing of data to be read. A central processing unit with terminals,
An input is coupled to an output terminal of a detection signal by the address transition detection circuit and an output terminal is coupled to an input terminal of the wait signal, and the detection signal is an address signal for selecting a memory cell in a memory cell array. , A wait signal forming circuit that outputs a wait signal for instructing at least the time from the selection operation of the memory cell until the sense amplifier output is determined as the wait time of the operation by the central processing unit, Be prepared.

[Operation] According to the above-described means, the data of a plurality of memory cells can be read at a time and held in the sense amplifier. Therefore, when desired data is read from the data held in the sense amplifier, the selection switch is used. It is possible to obtain the data immediately by simply switching, and it is possible to easily know from the outside whether or not the desired data is held in the sense amplifier. In other words, it is only necessary to reselect the output of the sense amplifier. Whether or not the memory cell selection operation has to be restarted can be detected by the wait signal formed based on the output of the address transition detection circuit. Time-dependent access is software-independent, which allows ROM access. High-speed access is realized.

[Embodiment] FIG. 1 shows an example of a basic configuration of a mask ROM applied to the access control system according to the present invention.

The memory cell array M-ARY of this embodiment is formed by collecting a plurality of memory cell columns in which m MOS transistors MC each constituting one memory cell are connected in series. Then, one end of each memory cell column is connected to the ground point of the circuit, and the other end is connected to the sense amplifier SA via the column switch Qy. Moreover, the sense amplifier SA is n
The column switch Qy, which is commonly provided for the memory cell columns and is selectively made conductive by the column decoder C-DEC, selectively selects one of the n memory cell columns to the sense amplifier SA. It is designed to be connected to.

In the memory cells MC belonging to the same row (one column in the vertical direction in the drawing) of each memory cell column, the gate electrodes are connected to the same word line W, and one of the m word lines W _{1 to} Wm is , The row decoder R-DEC brings the selection level to 0V. The threshold voltage of each MOS transistor forming the memory cell MC is set to, for example, −3V or 1V according to the write data “1” or “0”. And
Word lines other than the selected word line out of m are set to a non-selected level such as 5V. As a result, (m-1) non-selected MOS transistors in each memory cell column are
It is turned on regardless of the write data. On the other hand, the selection level (0
The cell to which the voltage V) is applied is turned on or off depending on the write data, that is, the threshold voltage. Therefore, at this time, in the memory cell string connected to the sense amplifier SA, current flows toward the ground point if the MOS transistor of the selected cell is in the on state, and no current flows in the off state. When the sense amplifier SA detects this difference in current, data is read.

Further, in this embodiment, the sense amplifier SA provided for each of the n memory cell columns can be connected to the common I / O line CL via the selection switch Qs. For the common I / O line CL,
The main amplifier MA is connected. Selection switch Qs above
Decoder DE that decodes the low order bits of the address
Any one of them is turned on by the selection signal SEL from C, and the corresponding sense amplifier SA is connected to the common I / O line CL. As a result, the read data held in the sense amplifier SA is amplified by the main amplifier MA and output to the outside by the output buffer DOB.

If the ROM is of a type configured to read data in 1-byte (8-bit) units, for example, a memory cell group, a sense amplifier row, and a main amplifier as shown in FIG. It suffices to provide eight circuits each consisting of 8 on the chip.

In the above embodiment (FIG. 1), for example, the memory cell array has 10
Considering the case of 24 memory cell columns, where n = 8, that is, one sense amplifier SA is provided for every 8 memory cell columns, in that case, each memory cell is supplied by supplying the address signal once. 12 in total from each group (m × n)
Eight pieces of data are read and held in 128 pieces of sense amplifiers SA.

Then, the data held in one of the sense amplifiers SA is sent to the main amplifier MA and amplified by the selection switch Qs.

Then, the next supplied address is the row decoder R-
If the selection signals output from the DEC and the column decoder C-DEC are not changed, that is, if one of the 128 sense amplifiers SA is already held, the decoder DEC outputs The selection signal QSEL switches the selection switch Qs, whereby the data held in the sense amplifier SA is immediately sent to the main amplifier MA for amplification.

Therefore, it is assumed that the access time until the data is read by the first access is 2 μsec and the access time required to read the data held in the sense amplifier SA is 80 nsec thereafter. Assume Then, with such a ROM, 128 sense amplifiers SA
In the case of continuously reading out the data held in, the total time is about 12 μs (2 μs + 127 × 80 ns). That is, the average access time is 95n seconds. On the other hand, in the conventional vertical ROM in which all the memory cells are connected to the same sense amplifier, it takes 256 microseconds, which is about 21 times faster. This average access time of 95 ns is based on the assumption that all data is read continuously, but considering the purpose of using a large capacity ROM (for example, storing a program), its addressing is based on locality. Since it has continuity, it is a value that can be expected sufficiently.

FIG. 2 is a block diagram showing an example of the entire mask ROM shown in FIG.

In this embodiment, in the mask ROM, of the address signals supplied from the outside such as a microcomputer, signals corresponding to the row address signal and the column address are monitored, and a detection signal (pulse) is output when the address changes. An address transition detection circuit ATD is provided. Further, the chip has a detection signal a in this address transition detection circuit ATD.
An external terminal AT is provided for outputting to the outside.
In FIG. 2, reference numerals ADB ₁ and ADB ₂ are address buffer circuits, respectively.

FIG. 3 shows an example of an access control system using the mask ROM shown in FIG.

That is, the address transition detection signal a output from the mask ROM 1 is input to the wait signal forming circuit 2 using a monostable multivibrator, and a pulse corresponding to the time (about 2 μs) required for access after the address transition. A width weight signal is formed. Then, this wait signal is input to the data transfer acknowledge signal input terminal of the asynchronous microcomputer 3 such as the 68000 CPU.
▼ is input. In FIG. 3, reference numeral 4 is a decoder which decodes the address signal output from the microcomputer and forms control signals such as a chip select signal and an out enable signal for the mask ROM.

Therefore, in the system as shown in FIG. 3 using the mask ROM of this embodiment, when the address is given first or the address corresponding to the row address and the column address is changed, the address transition detection circuit ATD detects it. The signal is output. As a result, a wait signal having a time width necessary for accessing the corresponding memory cell is formed and input to the ▲ ▼ terminal of the microcomputer 3 so that the reading of the data on the bus is made to wait for the time required for the access. Become.

Then, of the addresses supplied to the mask ROM, the signals corresponding to the row address and the column address do not change,
When only the address portion supplied to the decoder DEC of FIG. 2 has changed, no detection signal is output from the address transition detection circuit ATD. Therefore, the microcomputer can read the data output from the mask ROM on the bus in a short time such as 80 ns without particularly waiting.

Therefore, the microcomputer can automatically read data at a speed close to the maximum access time of the mask ROM without recognizing whether the address requires a long access time for the mask ROM. .

In the above embodiment, a wait signal having a pulse width corresponding to a long access time after the address transition is generated by the external weight signal forming circuit 2. However, the wait signal forming circuit 2 is provided inside the mask ROM 1. It is also possible to provide it in or to include it in the address transition detection circuit ATD.

FIG. 4 shows another block diagram of the mask ROM applied to the present invention. However, the memory cell array in this embodiment is the same as the memory cell array M in FIG.
This corresponds to a memory cell group composed of n memory cell columns in -ARY.

In this embodiment, a tag area TAG which is also composed of a nonvolatile memory element (MOSFET) is provided separately from the memory cell array M-ARY.

This tag area TAG is, for example, the decoders R-DEC and C-
When the memory cell array M-ART is accessed by the row decoder R-DEC and the data is read out by having the same number of bit lines (i) as the sum of the row address and the column address supplied to the DEC. The word address having the highest probability of containing data subsequent to the read data is stored as the next address.

Further, i sense amplifier groups SAt are provided corresponding to the tag area TAG, and the next address in the tag area TAG is selected by the row decoder R-DEC in the cell in the memory cell array M-ARY. Are simultaneously read out and amplified by the sense amplifier group SAt. Then, the next address can be supplied to the address buffer ADB via the address switching circuit CNG.

The address switching circuit CNG is switched by the control signal φ which is changed to the low level at the time when the access to the memory cell array M-ARY is started and the amplification by the sense amplifier SA is completed, and the address signal supplied from the outside is changed. Instead, the next address output from the sense amplifier SA is supplied to the address buffer ADB.

Further, since the data of one bit line selected from the n bit lines by the column decoder C-DEC is amplified, one data in the same n bit lines is separately provided from the sense amplifier SA. A sense amplifier SA 'for amplifying the signal is provided. And, 'between the changeover switch Qc, Qc' column switch group Qy ₁ ~Qyn and the sense amplifier SA and SA provided on the n bit lines are connected. The changeover switches Qc and Qc 'are turned on / off complementarily to each other by the control signal φ.

That is, the switch Qc is initially turned on, the memory cell array is accessed by an address signal from the outside, and when the read data is held in the sense amplifier SA, the switch Qc is turned off and Qc 'is turned on. The bit line group of the book is connected to the sense amplifier SA ′ side. And
When the memory cell array is accessed by the next address read from the tag area TAG, the data of the selected memory cell is amplified and held by the sense amplifier SA ′. During this read period, the original data held in the sense amplifier SA is sent to the main amplifier MA, amplified, and output by the output buffer DOB.

Further, the mask ROM of this embodiment is provided with an address comparison circuit CMP, and compares the next address read from the tag area TAG with the next address supplied from the outside. When they match, the selection switch Qs side is turned off by the selection signal of the decoder DEC, and the data held in the sense amplifier SA ′ is immediately sent to the main amplifier MA. As a result, desired data can be obtained without accessing the memory cell array.

Moreover, in this embodiment, when the address comparison circuit CMP detects an address match, a match detection signal is output, and the signal controls the gate G ₁ to output the wait signal output from the address transition detection circuit ATD. Signal
It is designed to decide whether to output to the outside. That is, the output of the wait signal is prohibited when the external address signal matches the next address. Therefore, the microcomputer promptly fetches the data on the bus and then outputs the next address.

On the other hand, when the address comparison circuit CMP detects an address mismatch, the selection switch Qs side is turned on and the wait signal from the address transition detection circuit ATD is output to the outside. As a result, the microphone columputer has to wait for the bus cycle until the access to the memory cell array by the external address is completed. As a result, the microcomputer can access without being aware of the address of the mask ROM, and moreover, it will not be kept waiting more than necessary.

When the data stored in the ROM is, for example, a program, it is possible to predict the page to be accessed next time with a fairly high probability by analyzing the addressing pattern in advance. By providing the tag area TAG to be inserted, the substantial access time can be shortened.

As described above, in the above-described embodiment, in the vertical mask ROM in which the MOS transistors forming the memory cells are connected in series for each column in the memory cell array, a common sense amplifier is provided for each predetermined number of memory cell columns. Provided with a selection switch that selectively connects one of those sense amplifiers to the main amplifier,
Since an address transition detection circuit is provided and a terminal that outputs a signal to notify the outside when there is a large address transition that changes the data of the sense amplifier is provided, data of multiple memory cells can be stored at once. Is read out and held in the sense amplifier, desired data can be immediately obtained from the held data, and it can be easily known from the outside whether or not the desired data is held in the sense amplifier. By virtue of the fact that it is possible, it is possible to access in accordance with the time required for reading, and there is an effect that the substantial access time of the vertical mask ROM that can be highly integrated is shortened.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments and various modifications can be made without departing from the scope of the invention. Nor. For example, in the above embodiment,
An address switching circuit that switches between an address signal supplied from the outside and a next address read from the tag area is provided in the preceding stage of the address buffer.However, an address switching circuit should be provided between the address buffer and the decoder. May be.

In the above description, the invention mainly made by the present inventor has been applied to the vertical mask ROM which is the field of application which is the background of the invention. However, the present invention is not limited to this, and is used in general semiconductor memory devices. can do.

[Effects of the Invention] The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

That is, a sense amplifier is provided for each of a plurality of memory cell columns, a plurality of data is read in advance and held in the sense amplifier, and a ROM is configured so that desired data can be read from the sense amplifier by switching a switch. The central processing unit for read access receives a wait signal corresponding to the time from the memory cell selection operation to the confirmation of the sense amplifier output only when receiving a wait signal formed based on the address transition detection signal output from the ROM. A vertical ROM that is convenient for high integration because a cycle is inserted, and other than that, the read operation is performed with the access cycle time from the output selection of the sense amplifier to the confirmation of the read data.
Will be able to achieve high-speed access to.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a basic configuration of a mask ROM applied to an access control system according to the present invention, and FIG. 2 is a block diagram showing an example of the entire mask ROM shown in FIG. FIG. 3 is a block diagram showing a configuration example of an access control system using the mask ROM of FIG. 2, and FIG. 4 is another block diagram of the mask ROM applied to the present invention. M-ARY ... Memory cell array, MC ... Nonvolatile memory element (memory cell), SA ... Sense amplifier, MA ... Main amplifier, TAG ... Tag area, DOB ... Output buffer, ATD
...... Address transition detection circuit, CMP ...... Address comparison circuit, CNG ...... Address switching circuit, Qy ...... Column switch, Qs ...... Switch.

Claims (1)

[Claims] 1. A plurality of memory cell column groups in each of which a plurality of memory cell columns in which a plurality of non-volatile memory elements are connected in series are arranged in parallel, and a crossing arrangement with each memory cell column is adopted. A plurality of word lines commonly connected to the selection terminals of the corresponding non-volatile memory elements of the memory cell column, a first decoder for supplying a selection signal to the word line according to an address signal, and other memory cell columns. A plurality of column switches, one end of which is coupled to the end and the other end of which is commonly connected to each memory cell column group, and one column switch is controlled to be turned on from each memory cell column group according to an address signal. And a second decoder that forms a selection signal for each of the memory cell column groups, the input is coupled to the common connection end of the column switch for each memory cell column group, and the input is amplified and output. Sense amplifier, a sense amplifier output selection switch provided between the output of each of the sense amplifiers and the common I / O line, and one sense amplifier output selection switch according to the address signal for controlling the ON state. A ROM provided with a third decoder for generating a selection signal and an address transition detection circuit for detecting a change in the address signal to be supplied to the first and second decoders, and read access to the ROM. Address signal for outputting the read access cycle time from the selection of the sense amplifier output by the third decoder to the output of the read data, and the wait signal for delaying the fetch timing of the data to be read. A central processing unit with an input terminal and an output terminal for the detection signal from the address transition detection circuit Together force is coupled, the output to the input terminal of the wait signal terminal is attached, the detection signal is, first and second
When a change in the address signal to be supplied to the coder is indicated, at least the time from the selection operation by the first and second decoders until the sense amplifier output is determined is designated as at least the wait time of the operation by the central processing unit. An access control system, comprising: a wait signal forming circuit for outputting a wait signal for