[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

JPH0792491A - Thin-film transistor substrate for active matrix display device - Google Patents

Thin-film transistor substrate for active matrix display device

Info

Publication number
JPH0792491A
JPH0792491A JP23517893A JP23517893A JPH0792491A JP H0792491 A JPH0792491 A JP H0792491A JP 23517893 A JP23517893 A JP 23517893A JP 23517893 A JP23517893 A JP 23517893A JP H0792491 A JPH0792491 A JP H0792491A
Authority
JP
Japan
Prior art keywords
electrodes
active matrix
display device
film transistor
worked
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23517893A
Other languages
Japanese (ja)
Inventor
Toshio Kawamura
敏雄 河村
Tetsuya Kawamura
哲也 川村
Yutaka Miyata
豊 宮田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP23517893A priority Critical patent/JPH0792491A/en
Publication of JPH0792491A publication Critical patent/JPH0792491A/en
Pending legal-status Critical Current

Links

Landscapes

  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To increase an opening rate and capacitance for charge accumulation and to improve a pixel display characteristic without increasing the number of stages by constituting capacitance parts for charge accumulation of transparent electrodes consisting of polycrystalline silicon and transparent electrodes used as pixel electrodes. CONSTITUTION:The film of the polycrystalline silicon is formed as an active semiconductor layer 2 on a light transparent glass substrate 1 and is worked to an island shape. The film of silicon dioxide is formed as a gate insulating layer 5 thereon and further, the film of, for example, chromium is formed as gate electrodes 6 and is worked to the island shape. Source regions 3, drain regions 4 and the capacitance electrodes 11 for charge accumulation are formed by using the gate electrodes 6 as a mask and introducing phosphorus as an impurity. Further, the silicon dioxide is formed as an interlayer insulating layer 7 thereon and thereafter, contact holes are formed. Films of source electrodes 8 and drain electrodes 9 are formed of, for example, titanium and aluminum in this order and are worked. The film of ITO is thereafter formed and worked as the pixel electrodes 10, by which the active matrix substrate is completed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、液晶表示装置などのア
クティブマトリクス表示装置用薄膜トランジスタ基板に
関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate for an active matrix display device such as a liquid crystal display device.

【0002】[0002]

【従来の技術】従来のアクティブマトリクス液晶表示装
置の単位画素の構成例を図7、図8、図9に示す。図7
は単位画素構成例の平面図を、図8、図9は、それぞれ
図7のE−E’線とF−F’線に沿った略示断面図を示
す。その製造方法を以下に説明する。
2. Description of the Related Art FIG. 7, FIG. 8 and FIG. 9 show structural examples of a unit pixel of a conventional active matrix liquid crystal display device. Figure 7
Is a plan view of a unit pixel configuration example, and FIGS. 8 and 9 are schematic cross-sectional views taken along lines EE ′ and FF ′ of FIG. 7, respectively. The manufacturing method will be described below.

【0003】まず、透光性ガラス基板1上に領域3、4
を含めて活性半導体層2を形成する。その上に、ゲート
絶縁層5およびゲート電極6、6’を形成する。次にフ
ォトレジストでマスクを形成してイオン注入法により不
純物を添加することによって、ソース領域3およびドレ
イン領域4を形成する。続いてフォトレジストを除去し
た後、層間絶縁層7を形成し、さらに開口を行った後、
ソース電極8、ドレイン電極9を形成する。最後に画素
電極10、パッシベーション層を形成し、薄膜トランジ
スタ基板が完成する。パッシベーション層は本発明に直
接関係しないので省略する。画像信号等を保持するため
の電荷蓄積用容量は、前段のゲート電極6’と層間絶縁
層7と画素電極10で構成されている。
First, regions 3, 4 are formed on the transparent glass substrate 1.
And the active semiconductor layer 2 is formed. A gate insulating layer 5 and gate electrodes 6 and 6'are formed thereon. Next, a source region 3 and a drain region 4 are formed by forming a mask with a photoresist and adding an impurity by an ion implantation method. Then, after removing the photoresist, the interlayer insulating layer 7 is formed, and after further opening,
The source electrode 8 and the drain electrode 9 are formed. Finally, the pixel electrode 10 and the passivation layer are formed to complete the thin film transistor substrate. The passivation layer is omitted because it is not directly related to the present invention. The charge storage capacitor for holding image signals and the like is composed of the gate electrode 6 ′ at the previous stage, the interlayer insulating layer 7, and the pixel electrode 10.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、このよ
うな従来の薄膜トランジスタ基板の画素構成では、光を
遮閉する他行のゲート電極と画素電極で電荷蓄積用容量
を形成するため、表示として有効な画素面積即ち開口率
が減少してしまうという欠点があった。
However, in such a pixel structure of the conventional thin film transistor substrate, since the charge storage capacitance is formed by the gate electrode and the pixel electrode of another row which shields light, it is effective as a display. There is a drawback that the pixel area, that is, the aperture ratio is reduced.

【0005】本発明は、このような従来の問題を解決す
るものであり、工程数を特に増加することなく、開口率
が大きくとれ、かつ電荷蓄積用容量も大きく良好な画像
表示特性を持つアクティブマトリクス表示装置用薄膜ト
ランジスタ基板を提供することを目的とする。
The present invention is intended to solve such a conventional problem, and has a large aperture ratio, a large charge storage capacity, and an active image display having a good image display characteristic without increasing the number of steps. An object is to provide a thin film transistor substrate for a matrix display device.

【0006】[0006]

【課題を解決するための手段】本発明は、上記目的を達
成するために、トランジスタ部の半導体層と同時に形成
された多結晶シリコンより成る第1の透明電極と、画素
電極となる第2の透明電極によって電荷蓄積用容量部を
構成するようにしたものである。
In order to achieve the above object, the present invention provides a first transparent electrode made of polycrystalline silicon formed at the same time as a semiconductor layer of a transistor portion and a second transparent electrode which becomes a pixel electrode. The transparent electrode constitutes the charge storage capacitor portion.

【0007】[0007]

【作用】本発明は、上記構成により、電荷蓄積用容量部
は光を透過するので、開口率を大きくとることができ、
さらに電荷蓄積用容量も大きくでき、なおかつ工程数を
増やすことなく良好な画像表示特性を持たせることが出
来る。
According to the present invention, with the above structure, since the charge storage capacitor section transmits light, a large aperture ratio can be obtained.
Further, the charge storage capacity can be increased, and good image display characteristics can be provided without increasing the number of steps.

【0008】[0008]

【実施例】以下、本発明の実施例について図面を参照し
て説明する。
Embodiments of the present invention will be described below with reference to the drawings.

【0009】(第1の実施例)本発明の第1の実施例に
おけるアクティブマトリクス液晶表示装置の単位画素の
構成例を図1,図2,図3に示す。図1は単位画素構成例
の平面図を、図2,図3は、それぞれ図1のA−A’線
とB−B’線に沿った略示断面図を示す。以下にその製
造方法を説明する。
(First Embodiment) FIG. 1, FIG. 2 and FIG. 3 show structural examples of a unit pixel of an active matrix liquid crystal display device according to a first embodiment of the present invention. FIG. 1 is a plan view of a unit pixel configuration example, and FIGS. 2 and 3 are schematic sectional views taken along the lines AA ′ and BB ′ of FIG. 1, respectively. The manufacturing method will be described below.

【0010】まず、透光性ガラス基板1上に活性半導体
層2として、例えばLP−CVD(Low Pressure Chemic
al Vapor Deposition)法により多結晶シリコンを成膜
し、フォトリソグラフィーおよびエッチングを用いて島
状に加工する。その上にゲート絶縁層5として、例えば
常圧CVD法により二酸化シリコンを形成する。さらに
ゲート電極6として例えばクロムを成膜し、フォトリソ
グラフィーおよびエッチングを用いて島状に加工する。
そしてゲート電極6をマスクとして、例えばイオン注入
法により燐を不純物として導入してソース領域3、ドレ
イン領域4、および電荷蓄積用容量部電極11を形成す
る。その上に、層間絶縁層7として、例えば常圧CVD
法により二酸化シリコンを形成した後フォトリソグラフ
ィーおよびエッチングによってコンタクトホールを形成
し、ソース電極8およびドレイン電極9を、例えば、チ
タン、アルミニウムの順で成膜し、加工する。その後、
画素電極10としてITOを成膜、加工してアクティブ
マトリクス基板を完成する。さらにパッシベーション層
も形成される場合もある。
First, as the active semiconductor layer 2 on the transparent glass substrate 1, for example, LP-CVD (Low Pressure Chemic) is used.
Al Vapor Deposition) method is used to form a polycrystalline silicon film, which is then processed into islands using photolithography and etching. As the gate insulating layer 5, silicon dioxide is formed thereon by, for example, the atmospheric pressure CVD method. Further, for example, a chromium film is formed as the gate electrode 6, and is processed into an island shape by using photolithography and etching.
Then, using the gate electrode 6 as a mask, phosphorus is introduced as an impurity by, for example, an ion implantation method to form the source region 3, the drain region 4, and the charge storage capacitor part electrode 11. On top of that, as the interlayer insulating layer 7, for example, atmospheric pressure CVD
After forming silicon dioxide by the method, contact holes are formed by photolithography and etching, and the source electrode 8 and the drain electrode 9 are formed, for example, in the order of titanium and aluminum, and processed. afterwards,
ITO is deposited and processed as the pixel electrode 10 to complete the active matrix substrate. Further, a passivation layer may be formed in some cases.

【0011】このように作製したアクティブマトリクス
基板の電荷蓄積用容量部は、図3に示すように、トラン
ジスタ部の半導体層と同時に形成された多結晶シリコン
と絶縁層と画素電極から構成される。単位画素をこのよ
うな構成にすると、電荷蓄積用容量部は光を透過するの
で、開口率を下げることなく電荷蓄積用容量を大きくこ
とができ、工程数を増やすことなく良好な画像表示特性
を持つアクティブマトリクス液晶表示装置用基板を提供
することができる。トランジスタ部の半導体層と同時に
形成された単位画素の電荷蓄積用容量部の多結晶シリコ
ン電極は、他段のゲート電極と接続される場合と、他段
のゲート電極とは独立して共通配線として接続される場
合とがある。後者の場合、ゲート線の電位変化の影響を
考慮することなく変調駆動ができ、輝度調整、コントラ
スト調整等の表示特性の制御が可能となる。
As shown in FIG. 3, the charge storage capacitance portion of the active matrix substrate thus manufactured is composed of polycrystalline silicon formed at the same time as the semiconductor layer of the transistor portion, an insulating layer and a pixel electrode. When the unit pixel is configured as described above, the charge storage capacitance section transmits light, so that the charge storage capacitance can be increased without lowering the aperture ratio, and good image display characteristics can be obtained without increasing the number of steps. A substrate for an active matrix liquid crystal display device having the same can be provided. The polycrystalline silicon electrode of the charge storage capacitor part of the unit pixel, which is formed at the same time as the semiconductor layer of the transistor part, is connected to the gate electrode of another stage and is connected to the gate electrode of the other stage as a common wiring. Sometimes connected. In the latter case, the modulation drive can be performed without considering the influence of the potential change of the gate line, and the display characteristics such as the brightness adjustment and the contrast adjustment can be controlled.

【0012】(第2の実施例)次に、本発明の第2の実
施例におけるアクティブマトリクス液晶表示装置の単位
画素の構成例を図4、図5、図6に示す。図4は単位画
素構成例の平面図を、図5、図6は、それぞれ図4のC
−C’線とD−D’線に沿った略示断面図を示す。以下
に、その製造方法を説明する。
(Second Embodiment) Next, examples of the constitution of a unit pixel of an active matrix liquid crystal display device according to a second embodiment of the present invention are shown in FIGS. 4, 5 and 6. FIG. 4 is a plan view of a unit pixel configuration example, and FIGS. 5 and 6 are C of FIG. 4, respectively.
The schematic sectional drawing along the -C 'line and the DD' line is shown. The manufacturing method thereof will be described below.

【0013】まず、透光性ガラス基板1上に活性半導体
層2として、例えばLP−CVD(Low Pressure Chemic
al Vapor Deposition)法により多結晶シリコンを成膜
し、フォトリソグラフィーおよびエッチングを用いて島
状に加工する。その上にゲート絶縁層5として例えば常
圧CVD法により二酸化シリコンを形成する。さらにゲ
ート電極6として例えばクロムを成膜し、フォトリソグ
ラフィーおよびエッチングを用いて島状に加工する。そ
してゲート電極6をマスクとして、例えばイオン注入法
により燐を不純物として導入してソース領域3、ドレイ
ン領域4、および電荷蓄積用容量部電極11を形成す
る。その上に、画素電極10としてITOを成膜、加工
する。その後、層間絶縁層7として例えば常圧CVD法
により二酸化シリコンを形成した後フォトリソグラフィ
ーおよびエッチングによってコンタクトホールを形成
し、ソース電極8およびドレイン電極9を、例えば、チ
タン、アルミニウムの順で成膜、加工し、アクティブマ
トリクス基板を完成する。さらにパッシベーション層も
形成される場合もある。
First, as an active semiconductor layer 2 on a transparent glass substrate 1, for example, LP-CVD (Low Pressure Chemic) is used.
Al Vapor Deposition) method is used to form a polycrystalline silicon film, which is then processed into islands using photolithography and etching. Silicon dioxide is formed thereon as the gate insulating layer 5 by atmospheric pressure CVD, for example. Further, for example, a chromium film is formed as the gate electrode 6, and is processed into an island shape by using photolithography and etching. Then, using the gate electrode 6 as a mask, phosphorus is introduced as an impurity by, for example, an ion implantation method to form the source region 3, the drain region 4, and the charge storage capacitor part electrode 11. Then, an ITO film is formed and processed as the pixel electrode 10. After that, for example, silicon dioxide is formed as the interlayer insulating layer 7 by the atmospheric pressure CVD method, and then a contact hole is formed by photolithography and etching, and the source electrode 8 and the drain electrode 9 are formed in the order of titanium and aluminum, Processing is completed to complete an active matrix substrate. Further, a passivation layer may be formed in some cases.

【0014】このように作製したアクティブマトリクス
基板の電荷蓄積用容量部は、図6に示すように、トラン
ジスタ部の半導体層と同時に形成された多結晶シリコン
と絶縁層と画素電極から構成される。この第2の実施例
により単位画素を構成すると、第1の実施例と同様な効
果に加えて、ソース、ドレイン電極形成時に、画素電極
であるITOが絶縁層を介して電気的に絶縁分離されて
いるために、ITO−異種金属間の電気化学的反応によ
るITOの腐食を回避することができる。
As shown in FIG. 6, the charge storage capacitance portion of the active matrix substrate thus manufactured is composed of polycrystalline silicon formed at the same time as the semiconductor layer of the transistor portion, an insulating layer and a pixel electrode. When the unit pixel is constructed according to the second embodiment, in addition to the effect similar to that of the first embodiment, the ITO as the pixel electrode is electrically insulated and separated through the insulating layer when the source and drain electrodes are formed. Therefore, corrosion of ITO due to electrochemical reaction between ITO and dissimilar metals can be avoided.

【0015】なお、第1、第2の実施例では画素電極と
なる第2の透明電極にITOを用いたが、多結晶シリコ
ンでもよく、また酸化亜鉛等の酸化物半導体をはじめと
する透光性の導電層なら任意の材料でよい。
In the first and second embodiments, ITO is used for the second transparent electrode which becomes the pixel electrode, but it may be made of polycrystalline silicon, or may be light-transmitting such as an oxide semiconductor such as zinc oxide. Any material may be used as long as it is a conductive layer.

【0016】[0016]

【発明の効果】以上説明したように、本発明によれば、
トランジスタ部の半導体層と同時に透光性の電荷蓄積用
容量部の電極を形成することができるので、工程数を増
やすことなく、開口率および電荷蓄積用容量も大きくす
ることができ、良好な画像表示特性を持つアクティブマ
トリクス表示装置用薄膜トランジスタ基板を実現でき
る。
As described above, according to the present invention,
Since the electrode of the light-transmitting charge storage capacitor can be formed at the same time as the semiconductor layer of the transistor portion, the aperture ratio and the charge storage capacitor can be increased without increasing the number of steps, and a favorable image can be obtained. A thin film transistor substrate for an active matrix display device having display characteristics can be realized.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例における単位画素構成を
示す平面図
FIG. 1 is a plan view showing a unit pixel configuration according to a first embodiment of the present invention.

【図2】図1のA−A’線に沿った略示断面図FIG. 2 is a schematic cross-sectional view taken along the line A-A ′ in FIG.

【図3】図1のB−B’線に沿った略示断面図3 is a schematic cross-sectional view taken along the line B-B ′ of FIG.

【図4】本発明の第2の実施例における単位画素構成を
示す平面図
FIG. 4 is a plan view showing a unit pixel configuration according to a second embodiment of the present invention.

【図5】図4のC−C’線に沿った略示断面図5 is a schematic cross-sectional view taken along the line C-C ′ of FIG.

【図6】図4のD−D’線に沿った略示断面図6 is a schematic cross-sectional view taken along the line D-D ′ of FIG.

【図7】従来の単位画素構成を示す平面図FIG. 7 is a plan view showing a conventional unit pixel configuration.

【図8】図7のE−E’線に沿った略示断面図8 is a schematic cross-sectional view taken along the line E-E ′ of FIG.

【図9】図7のF−F’線に沿った略示断面図9 is a schematic cross-sectional view taken along the line F-F ′ of FIG. 7.

【符号の説明】[Explanation of symbols]

1 透光性ガラス基板 2 活性半導体層 3 ソース領域 4 ドレイン領域 5 ゲート絶縁層 6 ゲート電極 6’前段のゲート電極 7 層間絶縁層 8 ソース電極 9 ドレイン電極 10 画素電極 11 電荷蓄積用容量部電極 1 Translucent Glass Substrate 2 Active Semiconductor Layer 3 Source Region 4 Drain Region 5 Gate Insulating Layer 6 Gate Electrode 6'Previous Stage Gate Electrode 7 Interlayer Insulating Layer 8 Source Electrode 9 Drain Electrode 10 Pixel Electrode 11 Charge Storage Capacitance Part Electrode

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 少なくともトランジスタ部と電荷蓄積用
容量部とを有し、その電荷蓄積用容量部が、第1の透明
電極と、画素電極となる第2の透明電極と、その間に挟
み込まれた絶縁層とを有する、アクティブマトリクス表
示装置用薄膜トランジスタ基板において、前記第1の透
明電極が多結晶シリコンから成り、前記トランジスタ部
の半導体層と同時に形成されることを特徴とするアクテ
ィブマトリクス表示装置用薄膜トランジスタ基板。
1. At least a transistor portion and a charge storage capacitance portion, the charge storage capacitance portion being sandwiched between a first transparent electrode, a second transparent electrode serving as a pixel electrode, and the second transparent electrode. In a thin film transistor substrate for an active matrix display device having an insulating layer, the first transparent electrode is made of polycrystalline silicon, and is formed at the same time as the semiconductor layer of the transistor section. substrate.
【請求項2】 第2の透明電極が、多結晶シリコンであ
ることを特徴とする請求項1記載のアクティブマトリク
ス表示装置用薄膜トランジスタ基板。
2. The thin film transistor substrate for an active matrix display device according to claim 1, wherein the second transparent electrode is polycrystalline silicon.
【請求項3】 第2の透明電極が、酸化物半導体層であ
ることを特徴とする請求項1記載のアクティブマトリク
ス表示装置用薄膜トランジスタ基板。
3. The thin film transistor substrate for an active matrix display device according to claim 1, wherein the second transparent electrode is an oxide semiconductor layer.
【請求項4】 酸化物半導体層が、酸化インジウムある
いは酸化錫あるいはその両方を主体とする層を含むもの
であることを特徴とする請求項3記載のアクティブマト
リクス表示装置用薄膜トランジスタ基板。
4. The thin film transistor substrate for an active matrix display device according to claim 3, wherein the oxide semiconductor layer includes a layer mainly containing indium oxide, tin oxide, or both.
JP23517893A 1993-09-21 1993-09-21 Thin-film transistor substrate for active matrix display device Pending JPH0792491A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23517893A JPH0792491A (en) 1993-09-21 1993-09-21 Thin-film transistor substrate for active matrix display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23517893A JPH0792491A (en) 1993-09-21 1993-09-21 Thin-film transistor substrate for active matrix display device

Publications (1)

Publication Number Publication Date
JPH0792491A true JPH0792491A (en) 1995-04-07

Family

ID=16982225

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23517893A Pending JPH0792491A (en) 1993-09-21 1993-09-21 Thin-film transistor substrate for active matrix display device

Country Status (1)

Country Link
JP (1) JPH0792491A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6313481B1 (en) 1998-08-06 2001-11-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and a method of manufacturing the same
KR100376338B1 (en) * 1999-06-28 2003-03-15 알프스 덴키 가부시키가이샤 Active matrix type liquid crystal display
US6690031B1 (en) 1998-04-28 2004-02-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the same
JP2010156963A (en) * 2008-12-05 2010-07-15 Semiconductor Energy Lab Co Ltd Semiconductor device
JP2013012774A (en) * 2009-10-21 2013-01-17 Semiconductor Energy Lab Co Ltd Manufacturing method for semiconductor device
US9660092B2 (en) 2011-08-31 2017-05-23 Semiconductor Energy Laboratory Co., Ltd. Oxide semiconductor thin film transistor including oxygen release layer
US9941393B2 (en) 2009-03-05 2018-04-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
JP2020031225A (en) * 2004-09-15 2020-02-27 株式会社半導体エネルギー研究所 Semiconductor device
US11233132B2 (en) 2009-03-05 2022-01-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6690031B1 (en) 1998-04-28 2004-02-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the same
US6313481B1 (en) 1998-08-06 2001-11-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and a method of manufacturing the same
US6576504B2 (en) 1998-08-06 2003-06-10 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating a liquid crystal display device having an improved storage capacitance
KR100376338B1 (en) * 1999-06-28 2003-03-15 알프스 덴키 가부시키가이샤 Active matrix type liquid crystal display
US11482624B2 (en) 2004-09-15 2022-10-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US10903367B2 (en) 2004-09-15 2021-01-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP2020031225A (en) * 2004-09-15 2020-02-27 株式会社半導体エネルギー研究所 Semiconductor device
JP2010156963A (en) * 2008-12-05 2010-07-15 Semiconductor Energy Lab Co Ltd Semiconductor device
US8999750B2 (en) 2008-12-05 2015-04-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9201280B2 (en) 2008-12-05 2015-12-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9941393B2 (en) 2009-03-05 2018-04-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US10326008B2 (en) 2009-03-05 2019-06-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US10686061B2 (en) 2009-03-05 2020-06-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US11233132B2 (en) 2009-03-05 2022-01-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US11955537B2 (en) 2009-03-05 2024-04-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US11961894B2 (en) 2009-03-05 2024-04-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US10079307B2 (en) 2009-10-21 2018-09-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method for the same
US8946700B2 (en) 2009-10-21 2015-02-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method for the same
JP2013012774A (en) * 2009-10-21 2013-01-17 Semiconductor Energy Lab Co Ltd Manufacturing method for semiconductor device
US9660092B2 (en) 2011-08-31 2017-05-23 Semiconductor Energy Laboratory Co., Ltd. Oxide semiconductor thin film transistor including oxygen release layer

Similar Documents

Publication Publication Date Title
JP3744980B2 (en) Semiconductor device
JP3708637B2 (en) Liquid crystal display device
US4958205A (en) Thin film transistor array and method of manufacturing the same
US4960719A (en) Method for producing amorphous silicon thin film transistor array substrate
US5828433A (en) Liquid crystal display device and a method of manufacturing the same
JP2776083B2 (en) Liquid crystal display device and manufacturing method thereof
US5231039A (en) Method of fabricating a liquid crystal display device
US20030169382A1 (en) Semipermeable liquid crystal display device and manufacturing method thereof
EP0329887B1 (en) Liquid crystal display device
US5981972A (en) Actived matrix substrate having a transistor with multi-layered ohmic contact
US5034340A (en) Amorphous silicon thin film transistor array substrate and method for producing the same
JPH0380226A (en) Active matrix substrate for liquid crystal display element and production thereof
JP2001109014A (en) Active matrix liquid crystal display device
US5751020A (en) Structure of a liquid crystal display unit having exposed channel region
JPH0792491A (en) Thin-film transistor substrate for active matrix display device
JPH04280231A (en) Thin film transistor array substrate and manufacture thereof
JPS6129820A (en) Substrate for active matrix display device
JPH04313729A (en) Liquid crystal display device
US20020037646A1 (en) Liquid crystal display and method
JPH0812539B2 (en) Display device and manufacturing method thereof
JP2639980B2 (en) Liquid crystal display
JP2653572B2 (en) Active matrix substrate manufacturing method
KR100267995B1 (en) Lcd and its fabrication method
KR100218578B1 (en) Structure and its manufacturing method of liquid crystal display device
KR100212270B1 (en) Thin film transistor and manufacture thereof