JPH0786609A - Multi-gate semiconductor element - Google Patents

Abstract

PURPOSE:To control the threshold voltage of a multi-gate semiconductor element arbitrarily after the completion of the element by mutually connecting the drain regions and source regions of adjacent thin-film transistors by an impurity region patterned in a specified shape and controlling the potential of the impurity region. CONSTITUTION:One multi-gate semiconductor element has a structure in which a plurality of TFTs are connected, and formed in the so-called double gate type. A common gate line GL is formed by a pattern so as to cross a pair of a source region S1 and a drain region D1 and a pair of a source region S2 and a drain region D2, thus constituting thin-film transistors TFT1, TFT2. A plurality of the multi-gate semiconductor elements 2 are connected mutually by a common control line CL. An adjusting means 3 Is connected to the control line CL, and the neutral point potential of each multi-gate semiconductor element 2 is controlled, thus adjusting the threshold potential of a plurality of the multi- gate semiconductor elements 2 in common.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a thin film transistor formed in a liquid crystal display, a contact image sensor or the like. More specifically, the present invention relates to a threshold voltage control technique for a multi-gate semiconductor device in which two or more thin film transistors are connected in series.

[0002]

2. Description of the Related Art Thin film transistors (hereinafter referred to as TFTs) have been actively developed in recent years because they can be applied to active matrix type liquid crystal displays, contact type image sensors and the like. In particular, a TFT using polycrystalline silicon (hereinafter referred to as poly-Si) as a thin film material
Has been drawing attention because the peripheral drive circuit can be integrated on the same substrate as the pixel array and the sensor array. However, a TFT using poly-Si has an advantage that it has a higher carrier mobility than a TFT using amorphous silicon, but a leak current flowing through a defect level in poly-Si is large. There was a flaw. Therefore, one thin film transistor element is provided with two or more gate electrodes as a means for reducing the leak current of the TFT.
A so-called multi-gate structure TFT has been conventionally proposed. FIG. 9 shows an example of a multi-gate structure TFT. This is equivalent to at least two TFs as shown in the figure.
The TFT has a structure in which Ts are connected in series. Hereinafter, such a multi-gate TFT will be referred to as a multi-gate semiconductor device. Since this multi-gate semiconductor element relaxes the electric field concentration at the drain end, it can suppress the leak current, and is applied to, for example, a pixel switching TFT in an active matrix liquid crystal display or a TFT forming a peripheral drive circuit. There is. Such a multi-gate semiconductor device is disclosed in, for example, JP-A-58-171860 and JP-A-58-180063.

Further, hydrogenation treatment has been conventionally known as a method for reducing the leak current of a TFT by improving the physical properties of the material of poly-Si. This hydrotreatment is
By diffusing hydrogen atoms in poly-Si, p
The defect level of poly-Si is terminated with hydrogen, and poly-
This is a method of reducing a leak current flowing through a defect level in Si. This hydroprocessing technique is disclosed in, for example, Japanese Patent Laid-Open No. 4-5.
No. 7098 is disclosed.

[0004]

In a TFT that constitutes a multi-gate semiconductor device using poly-Si, the threshold voltage Vth of the TFT often greatly changes due to variations in the manufacturing process. For example, when Vth shifts to the depletion side, there arises a problem that the off current extremely increases in the state where the gate voltage is 0V. In particular, when hydrogen is excessively taken into poly-Si in the above-mentioned hydrotreatment step, Vth shifts to the depletion side. In the past, when variations in the manufacturing process occurred, it was not possible to adjust Vth and control the off current after the TFT was completed. Generally, since the thin film transistor is formed on an insulating substrate made of quartz glass or the like, the channel potential is in a floating state. There is no TFT corresponding to the substrate potential Vs of a MOS transistor formed on a single crystal Si wafer. Therefore, the method of adjusting the substrate potential Vs to control Vth cannot be applied to the TFT.

[0005]

The present invention is intended to solve the above problems, and its purpose is to obtain the V after completion of the TFT.
The present invention provides a multi-gate semiconductor device capable of arbitrarily controlling th. The following measures have been taken in order to achieve this object. That is, in the multi-gate semiconductor element in which two or more thin film transistors are connected in series, the threshold voltage can be adjusted by providing adjusting means for controlling the potential of at least one of the series connection points. Specifically, the drain region and the source region of the adjacent thin film transistors are connected to each other by an impurity region patterned in a predetermined shape, and the adjusting means controls the potential of the impurity region. The multi-gate semiconductor device having such a structure can be applied to, for example, a peripheral drive circuit of an active matrix type liquid crystal display device.

[0006]

For example, in the n-channel type multi-gate semiconductor element, when the potential at the series connection point is swung to the plus side, the effective threshold voltage Vth of the multi-gate semiconductor element shifts to the plus side, that is, the enhancement side. Conversely, if the potential at the series connection point is shifted to the negative side, Vth will become the negative side,
That is, it shifts to the depletion side. In this way, by controlling the potential at the series connection point, the effective threshold voltage Vth of the multi-gate semiconductor element can be arbitrarily adjusted over a wide range. In the p-channel type multi-gate semiconductor element, Vth shifts to the enhancement side when the potential at the series connection point is shifted to the negative side, and Vth shifts to the depletion side when swinging to the positive side.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the drawings. 1A shows a planar structure of one multi-gate semiconductor element, and FIG. 1B shows an equivalent circuit in which a plurality of multi-gate semiconductor elements are connected. As shown in (A), one multi-gate semiconductor element has a structure in which two TFTs are connected in series, which is a so-called double gate type. However, the present invention is not limited to the double-gate semiconductor device, but can be applied to a multi-gate semiconductor device in which three or more TFTs are connected in series. The gate line GL is patterned to cross the pair of source region S1 and drain region D1.
One thin film transistor TFT1 is configured. Similarly,
A common gate line GL is arranged so as to intersect with another pair of source region S2 and drain region D2, and constitutes the other thin film transistor TFT2. Drain regions D1 of adjacent thin film transistors TFT1 and TFT2
The source region S2 and the source region S2 are connected to each other by the impurity region 1 which is patterned into a predetermined shape. Hereinafter, this connecting portion will be referred to as the midpoint. The impurity region 1 is formed in parallel with the gate line GL and constitutes the control line CL. The impurity region 1 is formed in the same thin film material as that of poly-Si which is the element region of the pair of TFT1 and TFT2. The impurity region 1 is doped with impurities in a high concentration like the source region and the drain region of each TFT, so that the resistance is reduced. For example, when the multi-gate semiconductor device is an n-channel type, As, P, etc. are doped. In the case of p-channel type, B or the like is doped.

As shown in (B), the plurality of multi-gate semiconductor elements 2 are connected to each other by a common control line CL. The adjusting means 3 is connected to the control line CL, and by controlling the midpoint potential of each multi-gate semiconductor element 2, the threshold voltages of the plurality of multi-gate semiconductor elements 2 can be adjusted in common. The adjusting means 3 can be composed of, for example, a variable power source.

Next, the threshold voltage control operation of the multi-gate semiconductor device will be described in detail with reference to FIG. Figure 1
FIG. 3 is a schematic equivalent circuit diagram of a single multi-gate semiconductor element 2. For the following description, the drain voltage applied to the drain end on the TFT1 side is Vds, and the other TFT
The source voltage applied to the second source end is Vss, the gate voltage applied to the common gate electrode is Vgs,
The midpoint potential applied to the midpoint is Vm. In this example, the TFT1 and the TFT2 are n-channel type, and the source potential Vss is set to 0V for convenience of the following description.

Generally, in a MOS transistor formed on a single crystal silicon wafer, its threshold voltage Vth is expressed by the following equation. Vth = Vfb + 2φb + (2εs · q · Na (2φb + Vbs)) ^1/2 / Ci In the above formula, Vfb represents a flat band voltage,
Vbs represents the substrate bias, εs represents the dielectric constant of silicon, φb represents the built-in potential, Na represents the acceptor concentration, q represents the elementary charge amount, and Ci represents the capacitance per unit area.

The above formula is basically applicable to a TFT having poly-Si as an element region. Therefore, the control operation of the threshold voltage Vth will be described in detail below based on the above equations and dividing the case according to the magnitude relation of the drain voltage Vds, the source potential Vss, and the midpoint potential Vm. As described above, in this description, the source potential Vss is 0V.
Is set to.

In the range of 0 <Vm <Vds, the average potential Vch1 in the channel of the TFT1 is larger than the average potential Vch2 in the channel of the TFT2, and Vch1> Vch2. Since the source potential of TFT1 is Vm, Vm>
In the case of Vgs, TFT1 is turned off, and Vm <V
In the case of gs, it is turned on. This is the substrate potential V in the above equation.
This is equivalent to increasing bs. At the same time TFT2 is TF
Since the channel potential is lower than T1, Vbs =
This corresponds to the case of 0V. Therefore, Vth of TFT2
It can be seen that is lower than Vth of TFT1. In the double-gate semiconductor element, the drain current of the entire pair is determined by the lower current value of the pair of TFT1 and TFT2. That is, the effective threshold voltage Vth of the double-gate semiconductor element becomes equal to the higher Vth of the two TFTs, so that Vth shifts to the plus side, that is, the enhancement side, compared to Vm = 0V.

In the range of Vm <0V, the directions of the drain currents are opposite between TFT1 and TFT2, and it is TF that effectively contributes to the drain current of the double-gate semiconductor element.
There is only the drain current flowing in T1. Therefore, in this case, the Vth of the TFT 1 may be considered. Since the source potential of the TFT1 is Vss1 = Vm <0, the gate of the TFT1 is open at Vgs = 0V. That is, V in the above formula
Corresponding to bs <0, Vth of the TFT1 shifts to the minus side, that is, the depletion side. Therefore, the effective threshold voltage Vth of the double gate semiconductor element also shifts in the depletion direction.

In the range of Vds <Vm, the drain current flows in the opposite direction, and each TFT does not function normally, so this range is not taken into consideration. The above discussion is similarly established in the case of the p-channel TFT only by reversing the polarity. The same holds true when the source potential Vss is other than 0V. In addition, a multi-gate semiconductor element in which two or more TFTs of a so-called LDD structure having an impurity concentration region thinner than the source / drain regions at the source / drain ends are connected in series can be similarly applied.

In FIG. 3, with Vm as a parameter, -4.0.
The Vgs-Ids characteristic of a double gate semiconductor element when changing in the range of V <Vm <+ 8.0V is shown. In this graph, the midpoint potential Vm is +8 from -4V to 2V step.
It changes to V. The drain voltage Vds is 10
It is set to V. As is clear from this graph, it is understood that the effective threshold voltage Vth of the double gate semiconductor element can be adjusted by controlling the midpoint potential Vm. Further, by controlling the midpoint potential, it is possible to turn on / off the double gate semiconductor device while keeping the potential of the gate electrode constant. As an example, when Vgs = 0V is considered, the double-gate semiconductor element is turned on when Vm <0, and turned off when Vm> 0.

Next, a method of manufacturing a multi-gate semiconductor device according to the present invention will be described in detail with reference to the process charts of FIGS. In this example, the multi-gate semiconductor element is a double gate type composed of a pair of TFTs.
Has an LDD structure. First, as shown in step A of FIG.
The Si thin film 12 is formed to a thickness of about 75 nm. If necessary, thereafter, Si + ions are ion-implanted to be amorphized, and subsequently furnace-annealed at a temperature of about 600 ° C. to increase the particle size of poly-Si. Excimer laser annealing may be used to increase the grain size. When amorphous silicon is formed in advance, it may be formed by plasma chemical vapor deposition (PCVD) at a temperature of about 150 to 250 ° C.

Next, in step B, the poly-Si thin film 12 is etched into a predetermined pattern. This pattern is shown in Figure 1.
As shown in (A), the TFTs are connected to each other at a series connection point. Further, as shown in FIG. 1B, double-gate semiconductor elements having the same conductivity type and having an equivalent role in the circuit are commonly connected through this pattern. Then, the poly-Si thin film 12 is oxidized to form the gate oxide film 1.
3 is formed to a thickness of about 60 nm.

Next, in step C, in order to control the threshold voltage Vth of the TFT as necessary, B + ions are added in an amount of 1 to 8 × 10 ¹² / cm 2.
Drive with a dose amount of about ² .

Next, in step D of FIG. 5, a silicon nitride thin film (Si ₃ N ₄ thin film) is formed on the gate oxide film 13 by LPCVD.
Is formed to a film thickness of about 10 to 20 nm. In some cases,
The surface of this Si ₃ N ₄ thin film 14 is oxidized to form a SiO ₂ film of about 1 to ₂ nm. If you adopt such a three-layer structure,
The gate withstand voltage can be sufficiently secured and reliability can be improved.

Next, in step E, a resist 15 is patterned on the poly-Si thin film 12 into a predetermined shape.
The resist 15 is patterned so as to be aligned with the region of the gate electrode formed in a later process. LDD structured TF
When forming T, the resist 15 is patterned so as to be wider than the width of the gate electrode so that a certain distance from both side surfaces of the gate electrode is left as an LDD region. If the LDD region is not formed, this resist coating step E can be omitted.

Subsequently, in step F, the Si ₃ N ₄ thin film 14 is cut.

Next, in step G in FIG. 6, impurity ions are implanted into the control line CL (see FIG. 1) including the series connection point and the source / drain regions of the TFT at a dose of 1 to 3 × 10 ¹⁵ / cm ^2. inject. In the case of n-channel type, As + ions or P + ions are implanted. In the case of p-channel type, B + ions are implanted. Thus, the reason why the ion implantation is performed on the source / drain regions before forming the gate electrode is to reduce the resistance of the control line located at a portion hidden under the gate line.

Next, in step H, after removing the resist 15, phosphorus-doped low resistance polycrystalline silicon is formed to a thickness of about 350 nm and patterned into a predetermined shape to form a gate electrode 16. There are three methods for forming the gate electrode 16. The first method is to form a non-doped polycrystalline silicon thin film and diffuse phosphorus from PClO ₃ gas. The second method is PCIO
_This is a method of performing phosphorus diffusion using a PSG film instead of ₃ gases. The third method is LPCVD method using SiH ₄ gas and PH.
_This is a method of thermally decomposing a mixed gas of _three gases to form a doped poly-Si film. Although either method may be used, the first method is adopted in this embodiment. In this embodiment, the channel length L and the channel width W of each TFT are L / W = 3
It was set to μm / 3 μm.

Then, the process moves to step I for forming the LDD structure. To form the LDD region 17, an n-channel TF is used.
In the case of T, As + ions or P + ions are implanted with a dose amount of 0.5 to 1.5 × 10 ¹³ / cm ² after forming the gate electrode 16. In the case of a p-channel TFT, B + ions are replaced by 0.1-2.
It may be similarly implanted with a dose amount of 0 × 10 ¹³ / cm ² .

Next, moving to step J of FIG. 7, the first PSG film 18 is formed to a thickness of about 600 nm by the LPCVD method, and the first PSG film 18 is formed to a thickness of 100 nm.
Each TFT was annealed at 0 ° C. for 10 minutes in N ₂ atmosphere.
The source region S, the drain region D, the LDD region 17, the control line including the series connection point, and the like are activated.

Next, in step K, the contact hole 19 is opened.

Next, in step L, the Al electrode 20 is set to about 600 nm.
Patterning is performed with the thickness of. 2nd PS on top of this
The G film 21 is formed with a thickness of about 400 nm.

Finally, in step M, a silicon nitride film (P-SiN _x film) 22 is formed with a thickness of about 100 nm by the PCVD method. Since the P-SiN _x film 22 contains a large amount of hydrogen, hydrogenation of each TFT can be efficiently performed by annealing after forming the film. The hydrogenation treatment can reduce the defect density of polycrystalline silicon and the leakage current of TFT due to the defects. The double gate semiconductor device is completed as described above.

Finally, with reference to FIG. 8, an example of the configuration of an active matrix liquid crystal display device constructed by using the multi-gate semiconductor element according to the present invention will be described. This device
It has a panel structure in which a main substrate 31 and a counter substrate 32 are bonded together by a spacer 33, and liquid crystal is held between both substrates. On the surface of the main substrate 31, a pixel array 36 including pixel electrodes 34 arranged in a matrix and switching elements 35 driving the pixel electrodes 34, and a peripheral drive circuit 37 connected to the pixel array 36 are formed. Has been done. The switching element 35 is a double gate semiconductor element. However, from the functional point of view, the threshold voltage adjusting means according to the present invention is not added. On the other hand, the peripheral drive circuit 37 also includes at least a part of the multi-gate semiconductor element. This multi-gate semiconductor element has the same conductivity type and is functionally equivalent as one group, and the threshold voltage adjusting means according to the present invention is added.

[0030]

According to the present invention, the threshold voltage Vth, which greatly varies due to variations in the manufacturing process, is controlled by controlling the potential of at least one of the series connection points of the TFTs forming the multi-gate semiconductor element. Can be adjusted to
Therefore, it is easy to adjust Vth even in a multi-gate semiconductor element whose threshold voltage is shifted due to process variations, and it is possible to significantly reduce defects due to Vth variations. Thus, the effects of the present invention are immense.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a planar shape and an equivalent circuit of a multi-gate semiconductor device according to the present invention.

FIG. 2 is an equivalent circuit diagram for explaining the operation of the multi-gate semiconductor device according to the present invention.

FIG. 3 shows Vg of a multi-gate semiconductor device according to the present invention.
It is a graph which shows s-Ids characteristic.

FIG. 4 is a manufacturing process diagram of a multi-gate semiconductor device according to the present invention.

FIG. 5 is also a manufacturing process drawing.

FIG. 6 is likewise a manufacturing process drawing.

FIG. 7 is likewise a manufacturing process drawing.

FIG. 8 is a schematic perspective view showing an active matrix liquid crystal display device in which a multi-gate semiconductor device according to the present invention is formed.

FIG. 9 is an equivalent circuit diagram of a conventional multi-gate semiconductor device.

[Explanation of symbols]

 1 Impurity region 2 Multi-gate semiconductor element 3 Adjustment means TFT1 One thin film transistor TFT2 The other thin film transistor S1 Source region S2 Source region D1 Drain region D2 Drain region GL Gate line CL Control line

Claims (3)

[Claims] 1. A multi-gate semiconductor device in which two or more thin film transistors are connected in series, wherein a threshold voltage can be adjusted by providing an adjusting means for controlling the potential of at least one of the series connection points. Gate semiconductor device. 2. The drain region and the source region of adjacent thin film transistors are connected to each other by an impurity region patterned into a predetermined shape, and the adjusting means controls the potential of the impurity region. Multi-gate semiconductor device. 3. A panel structure in which a pair of substrates are bonded to each other and liquid crystal is held between the two substrates. A pixel array and a peripheral drive circuit are formed on one substrate and a counter electrode is formed on the other substrate. In the active matrix liquid crystal display device, the peripheral drive circuit includes a multi-gate semiconductor element in which two or more thin film transistors are connected in series, and an adjusting means for controlling the potential of at least one of the series connection points is provided. An active matrix liquid crystal display device, which is capable of adjusting a threshold voltage of a semiconductor element.