JPH0786574A - Semiconductor device - Google Patents

Abstract

PURPOSE:To decrease source resistance and gate leaking current and to improve high-speed-operation performance by providing the high barrier layer of an AlGa thin film, which is inserted between an InGaP carrier supply layer and a gate electrode, and a source region and a drain region comprising a P-type impurity indtroducing region and an N-type impurity region reaching a carrier running layer. CONSTITUTION:The activating rate of impurities introduced into a carrier supply layer 4 comprising InGaP is high. Therefore, source resistance is sufficiently decreased. The contact part of a gate electrode 6 is a high barrier layer 6 comprising AlGaAs. Therefore, to gate current can be suppressed to the low value at the same time of ordinary HEMT. Thus, the improvement of the high-speed-operation performance and the achievement of low power dissipation can be accomplished at the same time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a complementary HEMT (high electron mobile) having improved characteristics.
The present invention relates to a semiconductor device including a ty transistor.

Since the complementary HEMT has a zero standby current, high speed is required and power consumption becomes a problem. For example, a battery-powered LSI (large scale) used in a mobile phone. integrat
ed circuit and MPU (micro pro)
It is suitable for a large-scale LSI such as a processing unit.

However, at present, CMOS (com
plementary metaloxide sem
The characteristics which are so good as to destroy the inductor have not been obtained, so further improvement is required.

[0004]

2. Description of the Related Art In manufacturing a complementary HEMT, a source and a drain corresponding to p-HEMT and n-HEMT are formed on a wafer in which a semi-insulating semiconductor substrate, a carrier transit layer, and a carrier supply layer are laminated in this order. Means are taken.

Usually, the carrier supply layer has a high Schottky barrier (1.0 [eV] for n-type and p-type) in order to suppress the gate leakage current, and the AlAs molar ratio is 0.5.
The above AlGaAs is used.

[0006]

Generally, the activation rate of the ion-implanted impurities is low, and about 10% of the implanted ions are activated, and the upper limit of the impurity concentration is the upper limit. It is about 10 ¹⁸ [cm ⁻³ ].

In addition to this, as described above, in order to suppress the gate leakage current, a material having a high Schottky barrier is used for carrier supply, so that the source resistance cannot be sufficiently reduced.

Due to this, the complementary H
EMT cannot improve high-speed operation characteristics, and CMO
You can't replace S.

For example, in p-HEMT, the transconductance g _m is 100 [m even when the gate length is 0.5 [μm].
S / mm] (if necessary, "A. Akinwa
nde et al IEDM 90-983 ").

This is because the source resistance is as high as about 1.2 [Ωmm]. If the resistance is reduced to about 0.5 [Ωmm], the mutual conductance g _m becomes 200.
It becomes possible to improve to [mS / mm].

The present invention aims to reduce the source resistance, suppress the gate leakage current to a low level, and simultaneously improve the high-speed operation performance and reduce the power consumption.

[0012]

In conventional complementary HEMTs, AlGaAs is often used as the material for the carrier supply layer, but AlGaAs has the above-mentioned drawbacks.

By the way, from the viewpoint of reducing the source resistance only, AlGaA is used as the material of the carrier supply layer.
s can be replaced by InGaP which is lattice matched to GaAs.

That is, InGaP can be sufficiently offset from GaAs in both the conduction band and the valence band, and p-HEM
It can function well as a carrier supply layer for both T and n-HEMT, and has a high activation rate for ion-implanted impurities of 100%, and the upper limit of impurity concentration is 10 ¹⁹ cm. ^-3 ] It depends on what is high.

However, InGaP has one problem that must be solved. That is, the Schottky barrier is as low as 0.7 [eV] for n-type and p-type, and therefore the gate leakage current is large (if necessary, "Y.
J. Chan et al. GaAs related 198
9 ”).

The present inventor has found that AlGaAs and InGa
By adopting the respective advantages of P, both reduction of the source resistance and maintenance of a high Schottky barrier were achieved.

FIG. 1 is a HEM for explaining the principle of the present invention.
It is a principal part cutting side view showing T. In the figure, 1 is a semi-insulating GaAs substrate, 2 is an AlGaAs buffer layer, 3 is an InGaAs traveling layer, 4 is an InGaP carrier supply layer,
5 is an AlGaAs high barrier layer, 6 is a gate electrode, 7 is a side wall film, 8 is a source region, 9 is a drain region,
Reference numeral 10 is a source electrode, and 11 is a drain electrode.

In this HEMT, the gate electrode 6 is made of AlG.
Since it is in contact with the aAs high barrier layer 5,
The leak current can be suppressed to a small value as in the conventional HEMT.

The carrier supply layer 4 can activate the ion-implanted impurities by about 100%.

From the above, in the semiconductor device according to the present invention, (1) between the carrier supply layer (for example, carrier supply layer 24) and the gate electrode (for example, gate electrode 26) made of InGaP as a material. Carriers are supplied from the surface to a region in which the high barrier layer of a thin film (for example, the high barrier layer 25) of a thin film made of AlGaAs and the high barrier layer which is distributed around the gate electrode are selectively removed. The source electrode (eg, source region 28) and the drain region (eg, drain region 29), which are p-type impurity introduction regions reaching at least the carrier transit layer (eg, carrier transit layer 23) through the layer, and the gate electrode are distributed in the center. At least the region where the high barrier layer has been selectively removed is reached from the surface through the carrier supply layer to at least the carrier transit layer. Source region (for example, the source region 30) and the drain region (for example, the drain region 3) which are n-type impurity introduction regions.
1) and are included.

[0021]

By adopting the above means, the activation rate of the impurities introduced into the carrier supply layer made of InGaP is high, so the source resistance is sufficiently reduced, and moreover, the gate electrode is in contact. Since it is a high barrier layer made of AlGaAs, gate leakage current is
As with MT, it can be suppressed to a low level, so that improvement in high-speed operation performance and low power consumption could be achieved at the same time.

[0022]

2 to 7 are side sectional views showing essential parts of a complementary HEMT in process steps for explaining a process for manufacturing an embodiment of the present invention. The description will be made with reference.

See FIG. 2 2- (1) For example, metalorganic vapor phase deposition (metalorganic)
vapor phase epitaxy: MOVP
The method E) is applied to epitaxially grow the buffer layer 22, the carrier transit layer 23, the carrier supply layer 24, and the high barrier layer 25 on the substrate 21.

The main data of the substrate 21 used here and each semiconductor layer epitaxially grown are as follows.

Substrate 21 Material: Semi-insulating GaAs buffer layer 22 Material: Undoped Al _x Ga _1-x As (x value = 0.5) Thickness: 3000 [Å]

About Carrier Travel Layer 23 Material: Undoped In _y Ga _1-y As (y value = 0.2
5) Thickness: 100 [Å] Regarding Carrier Supply Layer 24 Material: In _z Ga _1-z P (z value = 0.49) Thickness: 200 [Å]

About High Barrier Layer 25 Material: Undoped Al _x Ga _1-x As (x value = 0.5) Thickness: 20 [Å] It is necessary to adjust the threshold voltage in the carrier supply layer 24. For example, an ion implantation method may be applied to implant impurities.

See FIG. 3 3- (1) A WSi ₂ film having a thickness of 0.3 μm, for example, is formed by applying a sputtering method.

3- (2) Resist process in lithography technology, and
Reactive ion etching using SF ₆ gas as etching gas
g: RIE) by applying the step 3-
The WSi ₂ film formed in (1) is patterned to form the gate electrode 26.

See FIG. 4 4- (1) Plasma CVD (plasma chemical v)
By applying the apour deposition method, a SiON film having a thickness of, for example, 500 [Å] is formed.

4- (2) The SiON film formed in the step 4- (1) is anisotropically etched by applying the RIE method using SF ₆ as an etching gas to form the gate electrode 26. A side wall film 27 is formed on the side wall.

See FIG. 5 5- (1) Resist process in lithography technology, and
The etchant is HF: H ₂ O ₂ : H ₂ O = 1: 1: 10
The high barrier layer 25 is etched by applying a wet etching method using an etching liquid of 0 to form openings 25A in the portions where the source electrode and the drain electrode are to be formed.

See FIG. 6 6- (1) By applying a resist process in the lithography technique, for example, a resist film having an opening at a portion where a p-type impurity is to be introduced is formed.

6- (2) Acceleration energy is 20 [keV] and dose is 4 × 10 ^14.
Be ions were implanted as [cm ⁻² ], and p−
A source region 28 and a drain region 29 of HEMT are formed.

6- (3) After the resist film formed in the step 6- (1) is removed, an n-type impurity should be introduced by applying the resist process in the lithography technique again. A resist film having an opening at a portion is formed.

6- (4) Acceleration energy is 20 [keV] and dose is 4 × 10 ^14.
Implantation of Si ions as [cm ⁻² ], and n −
A source region 30 and a drain region 31 of HEMT are formed. Although the p-HEMT is formed first and the n-HEMT is formed here, the order may be reversed.

6- (5) RTA (rapid thermal anneal)
Depending on the application of the method, temperature 800 [℃], time 5
The activation process of the implanted impurities is performed for [seconds].

See FIG. 7 7- (1) The thickness is, for example, 1000 [Å] / 1000 [Å] by applying a resist process, a vacuum deposition method, and a lift-off method in the lithography technique. Ti / Pt
A source electrode 32 and a drain electrode 33 of the p-HEMT made of a film are formed.

7- (2) An AuGe / Au film having a thickness of, for example, 200 [Å] / 1000 [Å] depending on the application of a resist process, a vacuum deposition method, and a lift-off method in lithography technology. A source electrode 34 and a drain electrode 35 of the n-HEMT are formed. Although the p-HEMT electrodes are formed first and the n-HEMT electrodes are formed here, the order may be reversed.

7- (3) The drain electrode 33 in the p-HEMT having a thickness of, for example, 2000 [Å] is applied by applying the resist process, the vacuum deposition method, and the lift-off method in the lithography technique. And a wiring 36 made of an Al film that connects the drain electrode 35 in the n-HEMT to the wiring 36.

When the complementary HEMT completed through the above-described manufacturing process was actually measured, both p-HEMT and n-HEMT had a source resistance of 0.5 [Ωmm] and a mutual conductivity g _m of 400 for n-HEMT. [MS / mm],
200 [mS / mm] was obtained by p-HEMT. The reason for this is that the impurities ion-implanted into the source region and the drain region are activated up to 5 × 10 ¹⁹ [cm ⁻³ ].

A ring oscillator was prototyped using this complementary HEMT and the delay time was measured.
With a gate length of 0.5 [μm], 30 [picoseconds], that is, about twice as high speed as that of the complementary HEMT according to the conventional technique was recorded.

[0043]

In the semiconductor device according to the present invention, I
The high barrier layer of the AlGaAs thin film interposed between the nGaP carrier supply layer and the gate electrode and the high barrier layer at the position distributed around the gate electrode are selectively removed from the surface to the region where the high barrier layer is selectively removed. A carrier supply layer is formed from the surface to a source region and a drain region, which are p-type impurity introduction regions reaching the carrier transit layer via the gate, and a region where the high barrier layer is selectively removed at a position distributed around the gate electrode. It includes a source region and a drain region formed of an n-type impurity introduction region reaching the carrier transit layer through the region.

By adopting the above structure, InGaP
Since the activation rate of the impurities introduced into the carrier supply layer made of Al is high, the source resistance is sufficiently reduced. Moreover, since the gate electrode is in contact with the high barrier layer made of AlGaAs, the gate leakage current is reduced. Is normal H
As with the EMT, it can be suppressed to a low level, so that improvement in high-speed operation performance and low power consumption could be achieved at the same time.

[Brief description of drawings]

FIG. 1 is a side sectional view showing a main part of a HEMT for explaining the principle of the present invention.

FIG. 2 is a cross-sectional side view of essential parts showing a complementary HEMT in process steps for explaining a process for manufacturing an embodiment of the present invention.

FIG. 3 is a cross-sectional side view showing the essential part of the complementary HEMT in the process steps for explaining the process for manufacturing the embodiment of the present invention.

FIG. 4 is a cross-sectional side view of essential parts showing a complementary HEMT in a process key point for explaining a process for manufacturing the embodiment of the present invention.

FIG. 5 is a fragmentary side view showing a complementary HEMT in a process key point for explaining a process for manufacturing an embodiment of the present invention.

FIG. 6 is a side sectional view showing an essential part of a complementary HEMT at a process key point for explaining a process for manufacturing an embodiment of the present invention.

FIG. 7 is a side sectional view showing an essential part of a complementary HEMT in process steps for explaining a process for manufacturing an embodiment of the present invention.

[Explanation of symbols]

1 semi-insulating GaAs substrate 2 AlGaAs buffer layer 3 InGaAs transit layer 4 InGaP carrier supply layer 5 AlGaAs high barrier layer 6 gate electrode 7 side wall film 8 source region 9 drain region 10 source electrode 11 drain electrode 21 semi-insulating GaAs substrate 22 Undoped Al _x Ga _1-x As (x value = 0.5)
Buffer layer 23 Undoped In _y Ga _1-y As (y value = 0.2
5) Carrier traveling layer 24 In _z Ga _1-z P (z value = 0.49) Carrier supply layer 25 Undoped Al _x Ga _1-x As (x value = 0.5)
High barrier layer 25A Opening 26 Gate electrode 27 Side wall film 28 Source region 29 Drain region 30 Source region 31 Drain region 32 Source electrode 33 Drain electrode 34 Source electrode 35 Drain electrode 36 Wiring

Claims (1)

[Claims] 1. A high barrier layer of a thin film made of AlGaAs, which is interposed between a carrier supply layer made of InGaP and a gate electrode, and the high barrier at positions distributed around the gate electrode. In the region where the layer is selectively removed, a source region and a drain region, which are p-type impurity introduction regions reaching at least the carrier transit layer from the surface through the carrier supply layer, and the above-mentioned high position at a position distributed around the gate electrode. A semiconductor device comprising a region where the barrier layer is selectively removed, and a source region and a drain region which are n-type impurity introduction regions reaching at least the carrier transit layer from the surface through the carrier supply layer.