JPH0786427A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To improve the dimensional uniformity of gate length of an MOS transistor, by defining the gate length of the gate electrode of an MOS transistor of a trench capacitor cell by using a punched-out pattern. CONSTITUTION:Poly silicon doped with N-type impurities is deposited on a substrate, a resist pattern 23 for forming a gate electrode 22 is formed on the poly silicon, it is etched by using a resist pattern 23 as a mask, and the gate electrode 22 of an MOS transistor is formed. In this case, the upper part of the gate electrode 22 is etched so as to cover a part on a silicon oxide film. The gate length (the length in the direction of a channel which faces the substrate surface via a gate insulating film 19) of the gate electrode 22 is defined by a punched-out pattern of a wiring layer containing a poly silicon wiring 16, so that the dimensional uniformity of the gate length of the MOS transistor can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a structure of a dynamic memory cell (DRAM cell) of a trench capacitor system and a method of forming the same.

[0002]

2. Description of the Related Art As a DRAM (dynamic random access memory) is highly integrated, one transistor
Three-dimensionalization of the structure of the one-capacitor type DRAM cell is essential.

Cell structures used in DRAMs of 4 Mbit DRAM and later are roughly classified into a method using a so-called stack capacitor, in which a charge storage node is formed above a silicon substrate, and a method in which a groove is formed in a silicon substrate and the inside thereof is formed. It can be divided into a method using a so-called trench capacitor, which forms a charge storage node.

In a DRAM cell using a trench capacitor (trench capacitor cell), it becomes difficult to maintain the withstand voltage between adjacent trenches as the device becomes finer. As a countermeasure against this, a structure in which the inner wall of the trench is covered with an insulating film and a charge storage node is formed of polysilicon therein is becoming mainstream.

5 to 8 are sectional views showing an example of a sectional structure of a substrate in a conventional process of forming a trench capacitor cell. First, as shown in FIG. 5, with respect to the p-type silicon substrate 51 in which the n + diffusion layer 50 is embedded and formed as the plate electrode of the charge storage capacitor,
+ Ditch the groove 52 to reach the diffusion layer 50, and
Insulating film (for example, silicon oxide film) on the inner surface other than the bottom surface of
53 is formed. Further, a capacitor electrode (polysilicon film doped with an n-type impurity) 54 of the capacitor for charge storage is buried up to an intermediate height in the groove 52, and a capacitor insulating film (for example, silicon) is formed on the capacitor electrode 54 and on the inner peripheral surface of the groove 52. (Composite film of nitride film and silicon oxide film)
55 is formed.

Next, after a polysilicon film doped with n-type impurities is deposited on the entire surface of the substrate including the capacitor insulating film 55, a portion (capacitor charge storage node) filled up to the height of the capacitor electrode 54 in the groove is formed. Etch back by plasma etching, leaving 56).

Next, as shown in FIG. 6, using the resist 57 patterned by the photolithography technique as a mask, a part of the capacitor insulating film 55 (the inner peripheral surface of the groove on the MOS transistor side for the charge transfer gate). Are removed by plasma etching.

Next, after removing the resist 57, as shown in FIG. 7, a part (M) of the insulating film 53 on the inner peripheral surface of the groove is formed.
Buffered hydrofluoric acid solution (BFH)
Then, the capacitor charge storage node (polysilicon film doped with an n-type impurity) 5 is formed on the upper part of the groove by
8 and then this capacitor charge storage node 5
A silicon oxide film 59 is formed on the n-type polysilicon film for 8 and the substrate 51 by a thermal oxidation method, and at the same time, n-type impurities are diffused from the n-type polysilicon film for the capacitor charge storage node 58 to the substrate 51. By this, M
An n-type impurity diffusion layer 60 adjacent to a part of the inner peripheral surface of the groove on the OS transistor side is formed.

Next, as shown in FIG. 8, a part of the silicon oxide film 59 (including the MOS transistor formation planned region) on the substrate 51 is removed by using a photolithography technique and BFH, and a MOS transistor is formed. A silicon oxide film 61 for the gate insulating film is formed by a thermal oxidation method. Further, a polysilicon film doped with an n-type impurity is deposited on the silicon oxide film 61, a resist pattern 63 is formed on the polysilicon film, and the polysilicon film is subjected to reactive ion etching using the resist pattern 63 as a mask. By removing by (RIE) method,
The gate electrode 62 is formed by patterning.

Subsequently, the substrate 5 is formed by an ion implantation method.
1 is doped with an n-type impurity to form an n-type impurity diffusion layer to be the source region 64 and the drain region 65 of the MOS transistor. As a result, the source region 64 of the MOS transistor is electrically connected to the capacitor charge storage node 58 via the n-type impurity diffusion layer 60.

However, as described above, in order to connect the source region 64 of the MOS transistor and the capacitor charge storage node 58, the n-type impurity diffusion layer 60 adjacent to a part of the inner peripheral surface of the groove on the MOS transistor side is formed. The structure is
Since the contact area between the n-type impurity diffusion layer 60 and the source region 64 of the MOS transistor / capacitor charge storage node 58 is small, the source region 64 of the MOS transistor is formed.
The connection resistance of the capacitor charge storage node 58 increases,
There is a problem that the memory cell characteristics are impaired.

On the other hand, in order to electrically couple the source region 64 of the MOS transistor and the capacitor charge storage node 58, the source of the MOS transistor is brought into contact with the source region 64 of the MOS transistor and the capacitor charge storage node 58. A structure in which wiring is formed on the substrate surface from the region 64 to the capacitor charge storage node 58 is disclosed in, for example, Japanese Patent Laid-Open No. 63-278268.

An example of the one-transistor / one-capacitor type trench-capacitor cell having the above structure will be described with reference to FIG. In FIG. 9, 80
Is a p-type silicon substrate, 81 is a p-type epitaxial layer, 8
2 is an n-type diffusion layer region, 83 is an insulating film formed on the inner peripheral surface of the groove dug in the silicon substrate, 84 is a capacitor electrode (n-type) of a charge storage capacitor embedded up to an intermediate height in the groove. Polysilicon film doped with impurities), 85
Is a capacitor insulating film, 86 is a capacitor charge storage node (polysilicon doped with an n-type impurity) buried on the capacitor insulating film in the groove, and 87 is a field insulating film.

Reference numeral 91 is a gate insulating film formed on the surface of the silicon substrate, and 92 is a gate electrode (word line) formed on the gate insulating film 91. Reference numerals 94 and 95 denote a source region and a drain region of the n-channel MOS transistor for the charge transfer gate, which are formed by selectively forming diffusion layers on the surface layer of the silicon substrate.

Reference numeral 96 denotes the source region 9 of the MOS transistor.
4 is a wiring that is deposited and patterned on the surface of the substrate including the capacitor charge storage node 86 from above, and is formed of polysilicon doped with an n-type impurity. In this case, the wiring 86 and the gate electrode 92 of the MOS transistor are formed separately in the horizontal direction.

Reference numeral 97 is an interlayer insulating film formed so as to cover the gate electrode (word line) 92 and the wiring 86. Reference numeral 98 is a bit line formed on the interlayer insulating film 97, and is in contact with the drain region 95 through a contact hole formed in the interlayer insulating film 97 and the gate insulating film 91.

When forming the gate electrode of the conventional trench capacitor cell shown in FIGS. 8 and 9, a resist pattern formed on the material (for example, a polysilicon film doped with an n-type impurity) is used as a mask. Is patterned to leave some of the material,
That is, the gate length of the gate electrode (length in the channel length direction) is defined by the remaining pattern.

However, in the case where the gate length of the gate electrode is defined by the pattern as it is, the local gate electrode wiring width is caused by the halation in the photolithography process when the resist pattern is formed on the gate electrode material. The dimensional reduction may occur, and the dimensional uniformity of the gate length of the MOS transistor of each DRAM cell may be reduced, which in turn may reduce the uniformity of the threshold voltage of each MOS transistor.

[0019]

As described above, in the conventional trench capacitor cell structure, since the gate length of the gate electrode of the MOS transistor for charge transfer gate is defined by the pattern left, the gate length of the MOS transistor is However, there is a problem that the dimensional uniformity is deteriorated, and the uniformity of the threshold voltage of the MOS transistor is deteriorated.

The present invention has been made to solve the above-mentioned problems, and the gate length of the gate electrode of the MOS transistor of the trench capacitor cell is defined by a blanking pattern, so that the dimensional uniformity of the gate length of the MOS transistor is improved. Therefore, it is an object of the present invention to provide a semiconductor device capable of precisely controlling the uniformity of the threshold voltage of a MOS transistor and a method for manufacturing the semiconductor device.

[0021]

The semiconductor device of the present invention comprises:
A semiconductor substrate in which a diffusion layer is embedded and formed as a plate electrode of a charge storage capacitor, and a groove is formed so as to reach the diffusion layer; and a first insulating film formed on an inner peripheral surface other than the bottom surface of the groove. A capacitor electrode of a charge storage capacitor embedded to an intermediate height in the groove, a capacitor insulating film formed on the capacitor electrode and on an inner peripheral surface of the groove, and a capacitor insulating film embedded in the groove. A capacitor charge storage node made of a conductive material, a wiring continuously formed on the capacitor charge storage node and on the substrate in the vicinity of the groove, a second insulating film formed on the wiring, The gate insulating film formed on the end face of the wiring and the surface of the substrate where the gate is to be formed, the gate electrode formed on the gate insulating film, and the gate layer on the surface layer of the substrate. Characterized by comprising a source region and a drain region formed across the lower gate electrode.

The semiconductor device manufacturing method of the present invention is
A groove is formed so as to reach the diffusion layer on a part of the surface of the semiconductor substrate in which the diffusion layer used as the plate electrode of the charge storage capacitor is embedded, and a first groove is formed on the inner peripheral surface other than the bottom surface of the groove. The step of forming an insulating film, and filling a first conductive material to be a capacitor electrode of the charge storage capacitor up to an intermediate height in the groove, and forming a second insulating film for a capacitor insulating film on the first conductive material. Further, a step of forming a capacitor charge storage node made of a second conductive material so as to be embedded in a groove surrounded by the capacitor insulating film, and a third conductive material is deposited on the entire upper surface of the substrate, and the third conductive material is deposited. A step of depositing a third insulating film on the conductive material, and at least a MO for a charge transfer gate is formed on the third insulating film.
A first resist pattern is formed to expose the gate region of the S-transistor, and the third insulating film and the third conductive material are anisotropically etched using the first resist pattern as a mask to form the MOS transistor. Exposing the surface of the substrate under the gate region of the transistor; and forming the gate insulating film of the MOS transistor on the exposed surface of the surface of the substrate and simultaneously oxidizing the etched end face of the third conductive material. A step of diffusing impurities from the third conductive material into a substrate to form a drain region and a source region of the MOS transistor; depositing a gate electrode material on the entire upper surface of the substrate, and forming a gate on the gate electrode material. A second resist pattern for forming an electrode is formed, and the gate electrode material is patterned using the second resist pattern as a mask. And forming a gate electrode of the MOS transistor, and forming a bit line so as to connect to the third conductive material on the drain region of the MOS transistor. Is characterized by.

[0023]

In the semiconductor device and the method of manufacturing the same according to the present invention, the MOS is formed by using the wiring layer including the wiring for connecting the source region of the MOS transistor for the charge transfer gate in the trench capacitor cell and the capacitor charge storage node. Since the gate length of the gate electrode of the transistor is defined by the extraction pattern, the dimensional uniformity of the gate length of the MOS transistor is improved, and the uniformity of the threshold voltage of the MOS transistor can be precisely controlled. .

[0024]

Embodiments of the present invention will now be described in detail with reference to the drawings. 1 to 4 show an example of a sectional structure of a substrate in a process of forming a trench capacitor cell of a DRAM according to an embodiment of the present invention.

That is, first, as shown in FIG. 1, with respect to a p-type silicon substrate 11 in which an n + diffusion layer 10 is buried as a plate electrode of a charge storage capacitor, the n + diffusion layer 10 is reached so as to reach the n + diffusion layer. The groove is dug, an insulating film (for example, a silicon oxide film) 12 is formed on the inner peripheral surface other than the bottom surface of the groove, and the capacitor electrode of the charge storage capacitor (polysilicon doped with an n-type impurity) is formed to an intermediate height in the groove. A silicon film 13 is buried, and a capacitor insulating film (for example, a composite film of a silicon nitride film and a silicon oxide film) 14 is formed on the capacitor electrode 13 and on the inner peripheral surface of the groove 12.

Next, a polysilicon film doped with an n-type impurity is deposited on the entire surface of the substrate including the capacitor insulating film 14, and then the portion filled up to the height of the capacitor electrode 13 in the groove (capacitor charge storage node) is formed. Etch back by plasma etching to leave 15).

Then, a polysilicon film 16 doped with an n-type impurity is formed on the entire surface of the substrate (including the n-type polysilicon film 15 for the capacitor charge storage node) by low pressure CVD.
It is deposited by a (chemical vapor deposition) method, and a silicon oxide film 17 is deposited on this polysilicon film 16 by a low pressure CVD method.

Next, a resist pattern 18 is formed on the silicon oxide film 17 by a photolithography technique so as to expose at least the gate region of the MOS transistor for charge transfer gate, and the resist pattern 18 is used as a mask to form the silicon. The oxide film 17 and the polysilicon film 16 are etched by RIE,
The substrate surface under the gate region of the S transistor is exposed.

In this case, the remaining portion of the polysilicon film 16 includes a portion on the drain formation planned region of the MOS transistor and a portion (wiring) extending from the source formation planned region to the capacitor charge storage node 15.

Next, after removing the resist pattern 18, as shown in FIG. 2, a silicon oxide film to be the gate insulating film 19 of the MOS transistor is formed on the exposed surface of the substrate by a thermal oxidation method. The etched end surface of the polysilicon film 16 is also oxidized.

Next, as shown in FIG. 3, an n-type impurity is diffused from the n-type polysilicon film 16 into the substrate 11 by a thermal diffusion method, and the source region 20 and the drain region of the MOS transistor are formed on the surface layer portion thereof. Then, an n-type impurity diffusion layer to be 21 is formed. Here, the n-type impurity diffusion layer (source region 20) adjacent to a part of the inner peripheral surface of the trench on the MOS transistor side stores the capacitor charge via the wiring made of the polysilicon film 16 doped with the n-type impurity. It is electrically connected to the node 15.

Next, polysilicon doped with n-type impurities is deposited on the entire surface of the substrate by a low pressure CVD method, and a resist pattern 23 for forming a gate electrode (word line) 22 is formed on the polysilicon by a photolithography technique. Then, using the resist pattern 23 as a mask, the polysilicon is etched by RIE to form the gate electrode (word line) 22 of the MOS transistor.

In this case, the upper portion of the gate electrode 22 is etched so as to cover a part of the silicon oxide film 17, but the gate length of the gate electrode 22 (gate insulating film 19
The length in the channel direction opposed to the substrate surface via the) is defined by the cut pattern of the wiring layer including the polysilicon wiring 16.

Then, after removing the resist pattern 23, an insulating layer 24 is formed on the entire surface of the substrate as shown in FIG. 4, and a bit is formed in a portion of the insulating layer corresponding to the drain region of the MOS transistor. The bit line 25 is connected by forming a line connection hole, forming a bit line wiring layer on the entire surface of the insulating layer, and performing patterning.

According to the structure of the trench capacitor cell of the DRAM and the method of forming the same in the above-described embodiment, the polysilicon wiring 16 for connecting the source region 20 of the MOS transistor for the charge transfer gate and the capacitor charge storage node 15 is formed. Since the gate length of the gate electrode of the MOS transistor is defined by an extraction pattern by using the wiring layer including, the dimensional uniformity of the gate length of the MOS transistor is improved, and by extension, the uniformity of the threshold voltage of the MOS transistor is improved. It becomes possible to control precisely.

[0036]

As described above, according to the present invention, the gate length of the gate electrode of the MOS transistor of the trench capacitor cell is defined by the cut pattern.
The dimensional uniformity of the gate length of the MOS transistor is improved,
As a result, it is possible to realize a semiconductor device capable of precisely controlling the uniformity of the threshold voltage of a MOS transistor and a manufacturing method thereof.

[Brief description of drawings]

FIG. 1 is a sectional view showing a substrate structure in a part of a process of forming a trench capacitor cell according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a substrate structure in a step that follows the step of FIG.

FIG. 3 is a cross-sectional view showing a substrate structure in a step that follows the step of FIG.

FIG. 4 is a sectional view showing a substrate structure in a step that follows the step of FIG.

FIG. 5 is a cross-sectional view showing a substrate structure in a part of a conventional process of forming a trench capacitor cell.

FIG. 6 is a cross-sectional view showing the substrate structure in a step that follows the step of FIG.

7 is a sectional view showing a substrate structure in a step that follows the step of FIG.

8 is a sectional view showing a substrate structure in a step that follows the step of FIG.

FIG. 9 is a cross-sectional view showing another example of the structure of a conventional trench capacitor cell.

[Explanation of symbols]

10 ... Plate electrode (n + diffusion layer) of charge storage capacitor, 11 ... P-type silicon substrate, 12 ... Insulating film, 13 ...
Capacitor electrodes (polysilicon film doped with n-type impurities), 14 ... Capacitor insulating film, 15 ... Capacitor charge storage node, 16 ... Polysilicon wiring, 17 ... Silicon oxide film, 18 ... Resist pattern, 19 ... Gate insulating film, 20 ... Source region of MOS transistor, 21 ... M
Drain region of OS transistor, 22 ... Gate electrode (word line), 23 ... Resist pattern, 24 ... Insulating layer, 25 ... Bit line.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/822

Claims (2)

[Claims] 1. A semiconductor substrate in which a diffusion layer is embedded and formed as a plate electrode of a charge storage capacitor, and a groove is formed so as to reach the diffusion layer, and a first substrate formed on an inner peripheral surface other than the bottom surface of the groove. No. 1, an insulating film, a capacitor electrode of a capacitor for charge storage embedded in the groove to an intermediate height, a capacitor insulating film formed on the capacitor electrode and on an inner peripheral surface of the groove, and capacitor insulating in the groove. A capacitor charge storage node made of a conductive material embedded in the film, a wiring continuously formed on the capacitor charge storage node and on the substrate near the groove, and a second wiring formed on the wiring. An insulating film; a gate insulating film formed on an end face of the wiring and on a surface of a region where a gate is to be formed on the substrate; a gate electrode formed on the gate insulating film; A semiconductor device, comprising: a source region and a drain region formed below the gate electrode in a surface layer portion of the plate. 2. A groove is formed on a part of the surface of a semiconductor substrate in which a diffusion layer used as a plate electrode of a charge storage capacitor is buried so as to reach the diffusion layer, and a portion other than the bottom surface of the groove is formed. A step of forming a first insulating film on the peripheral surface, and a step of forming a first conductive material to be a capacitor electrode of a charge storage capacitor up to an intermediate height in the groove, and forming a second insulating film for the capacitor insulating film on the first conductive material. Forming a film and further forming a capacitor charge storage node made of a second conductive material so as to be embedded in a groove surrounded by the capacitor insulating film; and depositing a third conductive material on the entire upper surface of the substrate. And this third
Depositing a third insulating film on the conductive material, and at least M for the charge transfer gate is formed on the third insulating film.
First to expose the gate region of the OS transistor
Forming a resist pattern, and using the first resist pattern as a mask, anisotropically etching the third insulating film and the third conductive material to expose the substrate surface under the gate region of the MOS transistor. Forming a gate insulating film of the MOS transistor on the exposed surface of the substrate and oxidizing the etched end surface of the third conductive material at the same time; and impurities from the third conductive material to the substrate. Spread the M
Forming a drain region and a source region of the OS transistor; depositing a gate electrode material on the entire upper surface of the substrate; forming a second resist pattern for forming a gate electrode on the gate electrode material; Patterning the gate electrode material using the resist pattern as a mask to form the gate electrode of the MOS transistor; and forming a bit line so as to connect to the third conductive material on the drain region of the MOS transistor. A method of manufacturing a semiconductor device, comprising the steps of: