JPH0782749B2 - Bused signal drive circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a boosted signal drive circuit, and more particularly to improvement of a boosted word line drive circuit in a dynamic RAM.

[Conventional technology]

Taniguchi et al., "Fully boosted 64K dynamic RAM with automatic self-refresh function" IEEE
Journal of Solid State Circuits
Solid State Circuit-16, No. 5, October 1981 (M. Taniguchi eta
l., “Fully Boosted 64K Dynamic RAM with Automatic
and Self-Refresh. "IEEE Journal of Solid-State Ci
rcuit, vol.sc-16, No5, Oct.1981),
In the dynamic RAM, a boosted word line boosted to a power supply voltage (power supply potential) supplied from the outside of the dynamic RAM is used to secure an operation margin.

FIG. 3 shows a conventional boosted word line drive circuit.
In the figure, 1 to 10 are MOS transistors, 11 and 12 are capacitive elements, a, b and c are nodes, and 150 is a charge / discharge circuit.
Comprised of transistors 1-10 and capacitive element 1,
To charge the signal line, which is a word line, to near the power supply potential Vcc (when the word point drive signal φW is set to the H level) and discharge it to the ground potential (when the word line drive signal φW is set to the L level). Although the MOS transistor 5 functions as a charging transistor and the MOS transistor 9 functions as a discharging transistor, the capacitive element 12 has one electrode connected to the signal line. Together with the boost signal φP on the other electrode
Is configured to form a boost capacitive element.

Further, φR is a precharge signal, φT is a word line drive trigger signal, and φF is a signal output before the boost timing.

Next, the operation principle of the above-mentioned conventional example will be described with reference to the waveform chart of FIG. When the precharge signal φR is at a high level (substantially the power supply potential), the MOS transistor 9 which is a discharging transistor is in a conductive state during the so-called precharge period of the dynamic RAM, and the word line drive signal φW is at a low level (ground potential). , The MOS transistor 1 is conductive and the MOS transistor 2 is non-conductive, the node a
Is high level (approximately power supply potential), the MOS transistor 6 is conductive, the node b is low level (ground potential), and the MOS transistor 10 is conductive, node c is low level (ground potential). At this time, the MOS transistors 3, 4, 5, 7, 8 are non-conductive.

After the precharge is completed, that is, after the precharge signal φR is changed from the high level to the low level, the word line drive trigger signal φT is changed from the low level (ground potential) to the high level as shown in FIG. 4B. When (approximate power supply potential), MO
Since the S transistor 3 becomes conductive, the node c is charged by the power supply potential Vcc supplied to the power supply potential node. Therefore, the MOS transistor 4 is in the conductive state, but the MOS transistor 6 is also in the conductive state, and the ON resistance of the MOS transistor 4 is set to 5 times or more than the ON resistance of the MOS transistor 6, so that the potential of the node b is increased. Is maintained at approximately ground level. At the same time, the MOS transistor 5 becomes conductive, and the load capacitance (parasitic capacitance) of the word line itself and the boost capacitive element 12 are charged by the power supply potential Vcc supplied to the power supply potential node. as a result,
The word line drive signal φW rises to a potential (high level, H level) obtained by subtracting the threshold value of the MOS transistor 5 from the power supply potential Vcc. On the other hand, when the word line drive signal φW becomes H level, the MOS transistor 2 becomes conductive, and at this time, the MOS transistor 1 is non-conductive. The potential of node a is low level (ground potential)
And the gate electrode receives the potential of this node a.
The MOS transistor 6 changes from the conducting state to the non-conducting state. At this time, the node b is charged via the MOS transistor 4, and the potential of the node c is boosted to the power supply potential Vcc or higher due to the capacitive coupling of the capacitive element 11. As a result, the word line drive signal φW is set to the power supply potential (H level) via the MOS transistor 5.

After that, when the word line drive trigger signal φT changes from the high level to the low level, and the signal φF changes from the low level (ground potential) to the high level (substantially the power supply potential) as shown in FIG. The transistor 7 becomes conductive and the node b
Is set to a low level (ground potential), and the MOS transistor 8 is turned on to set the potential of the node c to a low level (ground potential).

As a result, the word line to which the word line drive signal φW is applied is brought into an electrically floating state (an electrically floating state).

After that, as shown in FIG. 4 (d), the boost signal φP
Changes from a low level (ground potential) to a high level (approximately power supply potential), and due to the capacitive coupling of the boosting capacitive element 12, the word line drive signal φW is higher than the power supply potential as shown in (e) of FIG. Is raised to the potential (H level).

After that, the signal φF and the boost signal φP change from the high level to the low level, the precharge signal φR changes from the low level to the high level, the discharge MOS transistor 9 becomes conductive, and the load capacitance of the word line itself. Then, the charge of the boosting capacitive element 12 is discharged, the word line drive signal φW is set to a low level (L level, ground potential), and the same state as in the precharge period described above is brought about.

[Problems to be Solved by the Invention]

By the way, in a normal dynamic RAM, the bit lines are charged to a high level (precharge period) and a large number of bit lines are sensed (at this time, the word line drive signal φW is H level).
Must be maintained at the level) to discharge. In this case, since the word line is in an electrically floating state as described above, due to the capacitive coupling between the bit line and the word line, H of the word line drive signal φW as shown by the broken line in (e) of FIG. The level potential drops.

Therefore, in the configuration of the conventional boosted signal drive circuit as described above, the write voltage of the memory cell (the information stored in the memory cell is read out and the information is read out to the memory cell in which the information is read out based on the read out information). The voltage at the time of writing) decreased, and the operation margin decreased.

This invention has been made in view of the above points,
For example, even if a potential higher than the power supply potential, which is the H level potential in the word line, decreases due to capacitive coupling between the bit line and the word line during the sensor, the H level potential higher than the power supply potential is recovered. The purpose of the invention is to obtain a boosted signal drive circuit that can be used.

[Means for solving problems]

A boosted signal drive circuit according to the present invention comprises a boosted signal line to which a boosted signal whose H level potential is higher than a power supply potential is supplied, and a capacitance larger than the load capacitance of the boosted signal line. Capacitive elements connected between the power supply potential output node and the L level potential node, and a plurality of capacitive elements, each of which is diode-connected and connected in series with each other between the power supply potential node and the internal power supply potential output node. A transistor and a capacitive element connected between one main electrode of one of the plurality of transistors and a signal input node to which an intermittent signal is input, and an internal power supply potential output node Between the internal power supply generation circuit that outputs a potential higher than the power supply potential and the boosted signal line and the internal power supply potential output node Is continued, the signal supplied to the boosted signal line is in a conductive state when an H level,
The boosting signal line is connected between the boosting signal line and the L level potential node, and the charging transistor is turned off when the signal supplied to the boosted signal line is at the L level. And a discharge transistor that is rendered non-conductive when the signal supplied to the H level is set to the H level and is rendered conductive when the signal supplied to the boosted signal line is set to the L level. .

Further, the boosted signal drive circuit according to the present invention is
Between a boosted signal line supplied with a boosted signal whose level potential is higher than the power source potential and a capacitance larger than the load capacitance of the boosted signal line, between the internal power source potential output node and the L level potential node. A capacitive element connected to the plurality of transistors, a plurality of transistors each being diode-connected and connected in series with each other between the power supply potential node and the internal power supply potential output node, and one transistor of the plurality of transistors. An internal power supply having a capacitive element connected between one of the main electrodes and a signal input node to which an intermittent signal is input, and outputting a potential higher than the power supply potential to the internal power supply potential output node. A circuit, connected between the boosted signal line and the internal power supply potential output node, and supplied to the boosted signal line. Signal when the signal is at the H level and when the signal supplied to the boosted signal line is at the L level is in the non-conductive state. A signal that is connected between a power supply potential node to be supplied and the boosted signal line, is rendered conductive when the signal supplied to the boosted signal line is at H level, and is supplied to the boosted signal line. A second charging transistor which is made non-conductive when L level is set to L level, and is connected between the boosted signal line and the L level potential node, and a signal supplied to the boosted signal line is set to H level. And a boosting signal that is turned off when the signal supplied to the boosted signal line is set to L level. It is obtained by the boosted signal generating circuit having a boosting capacitive element boost signal is supplied to the other electrode 備Ru so with one electrode connected to the Route.

Further, the boosted signal drive circuit according to the present invention is
Between a boosted signal line supplied with a boosted signal whose level potential is higher than the power source potential and a capacitance larger than the load capacitance of the boosted signal line, between the internal power source potential output node and the L level potential node. A capacitive element connected to the plurality of transistors, a plurality of transistors each being diode-connected and connected in series with each other between the power supply potential node and the internal power supply potential output node, and one transistor of the plurality of transistors. An internal power supply having a capacitive element connected between one of the main electrodes and a signal input node to which an intermittent signal is input, and outputting a potential higher than the power supply potential to the internal power supply potential output node. A circuit, connected between the boosted signal line and the internal power supply potential output node, and supplied to the boosted signal line. Signal is made conductive when the signal is at the H level, and is made nonconductive when the signal supplied to the boosted signal line is set at the L level, the boosted signal line, and the L level potential node. Is connected between the boosted signal line and the boosted signal line when it is at H level, and is in a non-conductive state, and when the signal supplied to the boosted signal line is at an L level, it is in a conductive state. A transistor for discharging and a transistor whose one main electrode is connected to the boosted signal line and which is made conductive when the boost signal is at the H level. One electrode is connected to the other main electrode of this transistor and the other is connected to the other main electrode. And a switched capacitor circuit having a capacitive element to which the boost signal is supplied.

[Action]

According to the present invention, the internal power supply generation circuit charges the signal line even when the H level potential of the signal line is lowered when the H level potential of the signal is higher than the power source potential. The transistor is used to compensate for the decrease.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.
FIG. 1 shows an embodiment of the present invention. 1 in the figure
Reference numeral 12 is the same as that shown in FIG. 3, and 250 is a charge / discharge circuit 150 having a charging MOS transistor 5 and a discharging MOS transistor 9 and a boost signal φP on the other electrode.
Boosted signal generating circuit composed of a boosting capacitive element 12 to which is supplied, and 100 is an internal power supply potential output of an internal power supply generation circuit (details will be described later) at the same time as or after boosting the word line drive signal φW. A connection circuit for connecting a node to a signal line supplied with a word line drive signal, and between the internal power supply potential output node and a signal line supplied with the word line drive signal φW (hereinafter referred to as a signal line). When the signal supplied to this signal line is set to the H level, it is rendered conductive, and the signal supplied to this signal line is set to L level.
It has a first charging transistor 105 which is brought into a non-conducting state when being set to a level, and the connection circuit 100 also has MOS transistors 101 to 104 and a capacitive element 106 in addition to this. Also, x and y are nodes.

The internal power supply generation circuit outputs a constant level potential Vs higher than the power supply potential Vcc to the internal power supply potential output node, and between the internal power supply potential output node and a predetermined potential node (ground potential node), The capacitive element has a capacitance larger than the load capacitance (parasitic capacitance) of the signal line.

Next, the operation will be described with reference to the waveform chart of FIG.

Since the parts other than the connection circuit 100 are the same as those shown in FIG. 3, detailed description thereof will be omitted, and the connection circuit will be mainly described.
100 will be described.

First, when the precharge signal φR is at high level, the MOS
Transistor 101 is conducting and MOS transistor 10
3 is in the non-conducting state because the signal φF is at the low level, the node x is at the high level (approximately the power supply potential), and the MOS transistor 104 is in the conducting state, so that the node y is in the low state. It is at the level (ground potential). At this time, the word line drive signal φW is at a low level (L level). After that, the word line drive trigger signal φT changes from the low level to the high level, the charging MOS transistor 5 of the charging / discharging circuit 150 becomes conductive, and the load capacitance of the word line itself and the boosting capacitive element 12 become the power source. It is charged by the power supply potential Vcc supplied to the potential node, and as the word line drive signal φW rises to a potential (high level, H level) obtained by subtracting the threshold value of the MOS transistor 5 from the power supply potential Vcc, the gate electrode MOS transistor 102 which is in a conductive state when a high level is applied to the node x.
The node y is charged to a high level via. At this time, MO
The S transistor 104 is in a non-conductive state due to the low level of the precharge signal φR. Further, in the charging MOS transistor 105 in the connection circuit 100, the gate electrode thereof has a high-level potential at the node y (substantially the power supply potential, but a potential lower than the power supply potential), and one main electrode has the word line drive signal φW. H-level potential (approximately power supply potential,
A potential lower than the power supply potential) is applied to the other main electrode with a potential Vs (about 8 V) higher than the power supply potential appearing at the internal power supply potential output node of the internal power supply generation circuit.

When the signal φF changes from the low level to the high level as shown in FIG. 2C after the word line drive trigger signal φT changes from the high level to the low level, the MOS transistor 103
Becomes conductive, the potential of the node x is set to a low level (ground potential), the MOS transistor 102 is made non-conductive, and the node y is electrically floated. After that, when the boost signal φP changes from the low level to the high level as shown in (d) of FIG. 2, the node y receives the boost signal φP at the other electrode, and the capacitive element 106 receives the power supply potential by capacitive coupling. It is boosted to a potential higher than Vcc (for example, 8V). Therefore, the charging MOS transistor 105 of the connection circuit 100 has a potential higher than the power supply potential Vcc applied to its gate electrode, so that it becomes conductive and the potential Vs appearing at the internal power supply potential output node of the internal power supply generation circuit is increased. Is set to a chargeable state for the signal line to which the drive signal φW is supplied to the word line.
At this time, the word line drive signal φW is a boost capacitive element.
At the same time, it is boosted to a potential higher than the power source potential Vcc (usually 7 V) by capacitive coupling of 12.

Then, after the sensing, when the potential of the word line is lowered due to capacitive coupling with the bit line, the charging MOS transistor 105 of the connection circuit 100 is in a conductive state. Therefore, as shown in (e) of FIG. The H level potential of the word line drive signal φW is recharged by the internal power supply generation circuit to a high potential (about 7V) higher than the power supply potential Vcc through the charging MOS transistor 105 of the connection circuit 100. Therefore, the write voltage is written in the memory cell without decreasing the write voltage of the memory cell. At this time, the potential Vs appearing at the internal power supply potential output node of the internal power supply generation circuit
As shown in (f) of FIG. 2, since the capacitive element which is several times or more the load capacitance of the word line which is the signal line is connected to the internal power supply potential output node, it hardly decreases. Further, as will be described later, since the internal power supply potential output node of the internal power supply generation circuit is supplemented with a potential higher than the power supply potential, the potential Vs appearing at the internal power supply potential output node is always the target. Word line drive signal φW
Of the power source potential Vcc or higher at the H level of the above.

After that, the signal φF and the boost signal φP change from the high level to the low level, the precharge signal φR changes from the low level to the high level, the discharge MOS transistor 9 becomes conductive, and the load capacitance of the word line itself. Then, the charge of the boosting capacitive element 12 is discharged, the word line drive signal φW is set to a low level (L level, ground potential), and the same state as in the precharge period described above is brought about.

FIG. 5 shows an internal power supply generation circuit. 20 in the figure
Reference numeral 23 is a MOS transistor, 24 and 25 are capacitive elements, and 26 is a word line connected between an internal power supply potential output node and a predetermined potential node (ground potential node) where a constant level potential Vs higher than the power supply potential Vcc appears. A capacitive element having a capacitance several times or more the load capacitance (parasitic capacitance) of the signal line to which the drive signal φW is supplied, φR is a precharge signal, and φcp is a signal asynchronous with the precharge signal φR. This is a signal that is periodically generated immediately after the power is turned on. V, W
Indicates a node.

Next, the operation principle of the internal power supply generation circuit shown in FIG.
This will be described with reference to the waveform chart of FIG. When the power of the dynamic RAM is turned on, the power supply potential Vcc is supplied to the power supply potential node and the MOS transistors 20 and 22 become conductive,
The potentials of the nodes V and W are Vcc-Vt (Vcc is the power supply potential, Vt is MO
The threshold voltage of the S transistor), the MOS transistors 21 and 23 become conductive, and the potential Vs appearing at the internal power supply potential output node of the internal power supply generation circuit becomes Vcc-2Vt. As shown in FIG. 6 (a), when the signal φcp changes from low level (ground potential) to high level (substantially the power supply potential), node W is generated by capacitive coupling of the capacitive element 25 which receives this signal φcp in one electrode. Potential of 2Vcc-Vt is about to be reached. However, since the MOS transistor 23 is in the conductive state, the capacitance of the capacitive element 25 × the charge of the power supply potential node flows into the capacitive element 26 connected to the internal power supply potential output node, and the potential of the node W changes from Vcc−2Vt. It becomes Vcc-Vt.

On the other hand, when the signal φcp changes from high level to low level,
The potential of the node W is -Vt due to the capacitive coupling of the capacitive element 25.
Trying to become. However, since the MOS transistor 22 is in the conductive state, the power supply potential Vcc supplied to the power supply potential node is charged again to Vcc-Vt. Signal φcp 1
To the extent that the level of Vs that appears at the internal power supply potential output signal node during the cycle rises, capacitive element 25 and capacitive element 26
It is decided by the ratio with. In the case of a dynamic RAM, there is usually a very small amount of setup time from power-on, and during this setup time the potential Vs is set to 2Vcc-2Vt.
It is possible to raise it up to (about 8V). Further, this internal power supply generation circuit uses a circuit composed of the MOS transistors 20 and 21 and the capacitive element 24 for each cycle of the dynamic RAM, that is, the precharge signal φ.
Every time R becomes high level, the reduction of the potential Vs is compensated by the same operation principle as the above-described operation by the signal φcp.

While one embodiment of the present invention has been described above, another embodiment of the present invention will be described below.

FIG. 7 shows another embodiment of the present invention. In the figure,
Reference numeral 200 denotes a circuit called a switched capacitor circuit, which is used for boosting the H level potential of the word line drive signal φW to the power source potential Vcc or higher as in the boosting capacitive element 12 in the embodiment shown in FIG. It is a thing. The circuit 2
00 is composed of MOS transistors 32 to 37 and capacitive elements 18 and 19, and MOS transistor 34
Has its one main electrode connected to a signal line to which the word line drive signal φW is supplied, and is rendered conductive when the boost signal φp is at the H level.
One electrode is connected to the other main electrode of the MOS transistor 34, and the boost signal φp is supplied to the other electrode. d and e indicate nodes.
The same reference numerals as those shown in FIG. 1 indicate the same parts.

Next, the operation of the other embodiment described above will be described. In another embodiment, the switched capacitor circuit 200
Since the other parts are the same as those of the embodiment shown in FIG. 1 described above, the detailed description will be omitted and the switched capacitor circuit 200 will be mainly described.

First, when the precharge signal φR is at high level, the MOS
Transistor 36 is conducting and MOS transistor 37
Is in a non-conductive state because the signal φF is at a low level, the node d is at a high level (approximately the power supply potential), and the MOS transistor 33 is in a conductive state, so that the node e is at a low level. (Ground potential). At this time, since the MOS transistors 9, 32, 33 are conductive,
The word line drive signal φW is at low level (L level). After that, after the precharge signal φR becomes low level, the word line drive trigger signal φT changes from low level to high level, the charging MOS transistor 5 of the charge / discharge circuit 150 becomes conductive, and the word line itself. Is charged by the power supply potential Vcc supplied to the power supply potential node, and the word line drive signal φW rises to a potential (high level, H level) obtained by subtracting the threshold value of the MOS transistor 5 from the power supply potential Vcc. Along with this, the node e is charged to a high level via the MOS transistor 32 which is in a conductive state by applying a high level at the node d to the gate electrode. At this time, the MOS transistor 33 outputs the precharge signal φ
The low level of R makes it non-conductive. Also,
Since the power supply potential is applied to the gate electrode of the MOS transistor 35, the potential of the node f is charged to the high level of Vcc-Vt. As a result, the MOS transistor 34
Is at a high level (potential lower than the power supply potential) on its gate electrode, and on one main electrode is an H level potential of the word line drive signal φW (almost power supply potential, but lower than the power supply potential).
However, the high level (Vcc-Vt) is applied to the other main electrode, respectively.

After that, when the signal φF changes from the low level to the high level after the word line drive trigger signal φT becomes the low level,
The MOS transistor 37 becomes conductive, the high-level potential of the node d is discharged to the ground potential, and the MOS transistor 32
Becomes non-conductive. Therefore, the node e is in an electrically floating state. After that, when the boost signal φP changes from the low level to the high level, the potentials of the nodes e and f are boosted to a high level (about 8V) which is higher than the power supply potential Vcc by the capacitive coupling of the capacitive elements 18 and 19. Since the capacitance of the capacitive element 19 is set to be at least twice the load capacitance of the word line, the high-level charge of the node f flows into the word line via the MOS transistor 34, so that the word line drive signal φ
The H level potential of W becomes a high level (about 7V) which is higher than the power source potential Vcc.

Then, after sensing, when the potential of the word line decreases due to capacitive coupling with the bit line, the charging MOS transistor 105 of the connection circuit 100 is in a conductive state, so that the H-level potential of the word line drive signal φW is The internal power supply generation circuit recharges the battery through the charging MOS transistor 105 of the connection circuit 100 to a high potential (about 7 V) higher than the power supply potential Vcc.

After that, the signal φF and the boost signal φP change from the high level to the low level, the precharge signal φR changes to the low level, the discharge MOS transistor 9 becomes conductive, and the charge of the load capacitance of the word line itself is changed. The word line drive signal φW is discharged to a low level (L level, ground potential), and the same state as in the above precharge period is entered.

Also in another embodiment of the present invention in which this type of switched capacitor circuit is provided, the same effect as that of the embodiment shown in FIG. 1 is obtained.

Furthermore, the switched capacitor circuit 200 is connected to the connection circuit 100.
Since the same operation as in the above is performed, instead of the connection circuit 100, as shown in FIG. 8, the gate electrode is connected to the node e, one main electrode (source electrode) is connected to the signal line to which the word line drive signal φW is supplied, and the internal power supply is connected. Even if the connection circuit 300 including the MOS transistor 301 having the other main electrode (drain electrode) connected to the internal power supply potential output node of the generation circuit is provided, the effect does not change.

Further, in each of the above-described embodiments, the boost signal φP changes from the low level to the high level to boost the word line drive signal φW at the same time as the connection between the internal power supply potential output node of the internal power generation circuit and the signal line. Although what has been done is shown, at the timing of entering the cycle of the dynamic RAM and writing the power supply potential level to the memory cell, even after the boost signal φP becomes high level,
The effect remains the same.

Further, in each of the above-mentioned embodiments, the example applied to the boosted word line drive circuit of the dynamic RAM has been described, but it goes without saying that the level reduction can be compensated for in other boosted signal drive circuits.

〔The invention's effect〕

As described above, according to the boosted signal drive circuit of the present invention, the boosted signal line to which the boosted signal whose H level potential is higher than the power source potential is supplied, and the load of the boosted signal line are loaded. A capacitive element having a capacitance larger than the capacitance and connected between the internal power supply potential output node and the L level potential node, each being diode-connected, and mutually connected between the power supply potential node and the internal power supply potential output node. A plurality of transistors connected in series, and a capacitive element connected between one main electrode of one of the plurality of transistors and a signal input node to which an intermittent signal is input. ,
An internal power supply generation circuit that outputs a potential higher than the power supply potential to the internal power supply potential output node, and a signal that is connected between the boosted signal line and the internal power supply potential output node and is supplied to the boosted signal line. To the H level, the charging transistor is made conductive, and the signal supplied to the boosted signal line is made nonconductive when the signal is set to the L level, the boosted signal line, and the L level potential node. The signal supplied to the boosted signal line is turned off when the signal supplied to the boosted signal line is set to H level.
Since the discharging transistor is made conductive when the level is set to the level, when the potential of the signal at the H level higher than the power source potential is supplied to the boosted signal line, for example, the boosted signal Even if the H level potential on the line drops, the internal power supply generation circuit can compensate for the drop through the charging transistor, and the H level of the signal is reduced.
The effect that the level potential can be recovered is obtained.

Further, according to the boosted signal drive circuit of the present invention, the boosted signal line to which the boosted signal whose H level potential is higher than the power source potential is supplied and the load capacitance of the boosted signal line are larger than the boosted signal line. A capacitive element formed of a capacitor and connected between the internal power supply potential output node and the L level potential node, each being diode-connected and connected in series between the power supply potential node and the internal power supply potential output node. And a capacitive element connected between one main electrode of one of the plurality of transistors and a signal input node to which an intermittent signal is input, and an internal power supply. An internal power supply generation circuit that outputs a potential higher than the power supply potential to the potential output node, the boosted signal line, and the internal power supply potential output node. Connected to the boosted signal line and brought into a conductive state when the signal supplied to the boosted signal line is at H level, and brought into a non-conductive state when the signal supplied to the boosted signal line is at L level. A connection circuit having a first charging transistor, a power supply potential node to which the power supply potential is supplied, and the boosted signal line, and a signal supplied to the boosted signal line is set to H level. Between the boosted signal line and the L level potential node, the second charging transistor is rendered conductive when the signal is supplied to the boosted signal line and is rendered non-conductive when the signal supplied to the boosted signal line is set to the L level. The signal supplied to the boosted signal line is brought into the non-conduction state when the signal supplied to the boosted signal line is set to the H level, and the signal supplied to the boosted signal line is set to the L level. A boosting signal generating circuit having a boosting capacitive element in which one electrode is connected to the boosted signal line and a boost signal is supplied to the other electrode. Since it was set to H
When a potential whose level potential is higher than the power source potential is supplied to the boosted signal line, even if the H level potential in the boosted signal line decreases, the internal power supply generation circuit passes through the charging transistor. The effect of being able to compensate for the decrease and recovering the H level potential of the signal is obtained.

Further, according to the boosted signal generating circuit of the present invention, the boosted signal line to which the boosted signal whose H level potential is higher than the power source potential is supplied and the load capacitance of the boosted signal line are larger than the boosted signal line. A capacitive element formed of a capacitor and connected between the internal power supply potential output node and the L level potential node, each being diode-connected and connected in series between the power supply potential node and the internal power supply potential output node. And a capacitive element connected between one main electrode of one of the plurality of transistors and a signal input node to which an intermittent signal is input, and an internal power supply. An internal power supply generation circuit that outputs a potential higher than the power supply potential to the potential output node, the boosted signal line, and the internal power supply potential output node. Connected between the boostered signal line and the boosted signal line and brought into the conductive state when the signal is supplied to the boosted signal line at the H level, and is brought into the non-conductive state when the signal supplied to the boosted signal line is set to the L level. Transistor, the boosted signal line, and the L level potential node are connected to each other, and when the signal supplied to the boosted signal line is set to the H level, the transistor is turned off and the boosted signal line is connected to the boosted signal line. A discharging transistor that is turned on when a supplied signal is at L level, a transistor that is connected to the boosted signal line when one main electrode is connected, and is turned on when a boost signal is at H level. One of the main electrodes of the switch is connected to one electrode and the boost signal is supplied to the other electrode of the switched capacitor. Since so and a capacitor circuit, when higher than the H-level potential is the power supply potential of the signal potential is supplied to the boosted signal line,
For example, even if the H-level potential of the boosted signal line drops, the internal power supply generation circuit can compensate for the drop through the charging transistor, and the H-level potential of the signal can be recovered. It is what is done.

[Brief description of drawings]

FIG. 1 is a diagram showing a boosted signal drive circuit according to an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the circuit operation of FIG. 1, and FIG. 3 is a conventional boosted word line drive circuit. FIG. 4, FIG. 4 is a waveform diagram for explaining the circuit operation of FIG. 3, FIG. 5 is a diagram showing an embodiment of the internal power supply generation circuit, and FIG. 6 is a diagram showing the operation principle of FIG. Waveform diagrams for explaining, FIG. 7 and FIG. 8 are views showing boosted signal drive circuits which are other embodiments of the present invention. In the figure, 100 is a connection circuit, 105 is a first charging MOS transistor, 250 is a boosted signal generation circuit, 150 is a charging / discharging circuit, 5 is a second charging MOS transistor, and 9 is a discharging MOS.
Transistor, 12 is a capacitive element for boosting, 200 is a switched capacitor circuit, 34 is a transistor, 34 is a capacitive element, Vs is a potential appearing at the internal power supply potential output node of the internal power supply generation circuit, and 26 is an internal power supply generation circuit. It is a capacitive element. In the drawings, the same reference numerals indicate the same or corresponding parts.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Hideto Hidaka 4-1-1 Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric Corporation LSI Research Laboratory (72) Inventor Katsumi Dosaka 4 Mizuhara, Itami City, Hyogo Prefecture 1-chome, Mitsubishi Electric Co., Ltd. LSI Research Laboratory (72) Inventor Yasuhiro Konishi 4-1-1, Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric Co., Ltd. LSI Research Laboratory (56) Reference JP 57 -18080 (JP, A) JP-A-57-133589 (JP, A) JP-A-59-38996 (JP, A)

Claims (6)

[Claims] 1. An internal power supply potential output node, which comprises a boosted signal line supplied with a boosted signal whose H level potential is higher than the power supply potential, and a capacitance larger than the load capacitance of the boosted signal line, and an L node. Capacitive element connected between the level potential node, a plurality of transistors diode-connected and connected in series between the power supply potential node and the internal power supply potential output node, and the plurality of transistors A capacitive element connected between one main electrode of one of the transistors and a signal input node to which an intermittent signal is input, and a potential higher than the power supply potential at the internal power supply potential output node. Is connected between the boosted signal line and the internal power supply potential output node, and the boosted signal is output. A charging transistor that is rendered conductive when the signal supplied to the line is at H level and is rendered non-conductive when the signal supplied to the boosted signal line is at L level; and the boosted signal line. It is connected between the boosted signal line and the L level potential node and is in a non-conducting state when the signal supplied to the boosted signal line is at the H level, and when the signal supplied to the boosted signal line is at the L level. A boosted signal drive circuit comprising: a discharge transistor that is made conductive. 2. The boosted signal line is dynamic
The boosted signal drive circuit according to claim 1, wherein the boosted signal drive circuit is a word line arranged orthogonal to a bit line in a RAM. 3. An internal power supply potential output node and an L, which comprises a boosted signal line supplied with a boosted signal whose H level potential is higher than the power supply potential, and a capacitance larger than the load capacitance of the boosted signal line. Capacitive element connected between the level potential node, a plurality of transistors diode-connected and connected in series between the power supply potential node and the internal power supply potential output node, and the plurality of transistors A capacitive element connected between one main electrode of one of the transistors and a signal input node to which an intermittent signal is input, and a potential higher than the power supply potential at the internal power supply potential output node. Is connected between the boosted signal line and the internal power supply potential output node, and the boosted signal is output. A connection circuit having a first charging transistor which is rendered conductive when a signal supplied to the line is at an H level and is rendered non-conductive when a signal supplied to the boosted signal line is at an L level. The boosted signal line is connected between a power supply potential node to which the power supply potential is supplied and the boosted signal line, and is rendered conductive when a signal supplied to the boosted signal line is set to H level. A second charging transistor that is rendered non-conductive when the signal supplied to the L level is connected to the boosted signal line and the L level potential node, and is supplied to the boosted signal line. A discharging transistor that is rendered non-conductive when the signal that is set to the H level and is rendered conductive when the signal that is supplied to the boosted signal line is set to the L level, And a boosted signal generating circuit having a boosting capacitive element in which one electrode is connected to the boosted signal line and a boost signal is supplied to the other electrode. . 4. The boosted signal line is dynamic.
4. The boosted signal drive circuit according to claim 3, wherein the boosted signal drive circuit is a word line arranged orthogonal to a bit line in a RAM. 5. An internal power supply potential output node and an L, which is composed of a boosted signal line supplied with a boosted signal whose H level potential is higher than the power supply potential, and a capacitance larger than the load capacitance of the boosted signal line. Capacitive element connected between the level potential node, a plurality of transistors diode-connected and connected in series between the power supply potential node and the internal power supply potential output node, and the plurality of transistors A capacitive element connected between one main electrode of one of the transistors and a signal input node to which an intermittent signal is input, and a potential higher than the power supply potential at the internal power supply potential output node. Is connected between the boosted signal line and the internal power supply potential output node, and the boosted signal is output. A charging transistor that is rendered conductive when the signal supplied to the line is at H level and is rendered non-conductive when the signal supplied to the boosted signal line is at L level; and the boosted signal line. It is connected between the boosted signal line and the L level potential node and is in a non-conducting state when the signal supplied to the boosted signal line is at the H level, and when the signal supplied to the boosted signal line is at the L level. A discharging transistor which is made conductive, one main electrode of which is connected to the boosted signal line and which is made conductive when the boost signal is at the H level, and the other main electrode of which has one electrode And a switched capacitor circuit having a capacitive element connected to the other electrode to which the boost signal is supplied. Suteddo signal driving circuit. 6. The boosted signal line is dynamic.
6. The boosted signal drive circuit according to claim 5, wherein the boosted signal drive circuit is a word line arranged orthogonal to a bit line in a RAM.