JPH0779234B2 - Semiconductor integrated circuit device - Google Patents

Description

The present invention relates to a semiconductor integrated circuit device.

Although TTL (transistor-transistor logic) can operate at high speed, it has the drawbacks of high power consumption and low gate array integration.

On the other hand, CMOS (complementary MOS) and the like, which are composed of MOSFETs (insulated gate field effect transistors), have the advantages of relatively low speed, low power consumption, and high gate array integration. Regarding the gate array, for example
1982 AIE International Solid State Circuits Conference Digest of Technical Papers (1982 IEEE International Solid-Sta
te Circuits Conference DIGEST OF TECHNICAL PAPE
RS) 174 to 175, and regarding TTL, Showa 52
November 30, 2013 Published by Ohmsha Bookstore, Semiconductor Handbook No. 47
It is described on pages 9 to 480, respectively.

Therefore, the inventor of the present application configures the internal logic block with a CMOS circuit or the like and configures the output circuit with a TTL circuit.
It was considered to obtain a semiconductor integrated circuit device of relatively high speed, low power consumption and high integration. However, the current at the input part of the TTL circuit is large when viewed from a CMOS circuit with a relatively small drive current, so the operation speed of the interface here will be significantly slowed down.

Also, because the number of fan-outs (Fan-Out) of CMOS circuits etc. cannot be large, many CMOS buffers of relatively large chip size are required between the CMOS circuits etc. and the TTL output buffer, and the degree of integration is reduced. There is a drawback that it causes it.

An object of the present invention is to provide a semiconductor integrated circuit device which has relatively high speed, low power consumption, and high integration.

Other objects of the present invention will be apparent from the following description and drawings.

Hereinafter, the present invention will be described in detail together with examples.

FIG. 1 shows a block diagram of an embodiment of the present invention.

In the figure, the TTL input buffer and the TTL output buffer are composed of bipolar transistors except for the input elements in the TTL output buffer, and the internal logic block and TT
The input device in the L output buffer is composed of a MOSFET. Further, the input buffer unit may have a TTL level input interface characteristic, and may be composed of a MOSFET. Each of these circuit elements is formed on one semiconductor substrate by a known semiconductor manufacturing method. Although not particularly limited, the internal logic block is
To reduce its power consumption, it is composed of a CMOS circuit.

Further, the semiconductor integrated circuit device IC of this embodiment is not particularly limited, but its circuit function is determined by the master slice method. That is, transistors, diodes,
A semiconductor integrated circuit device having various circuit functions by creating a basic pattern in which circuit elements such as resistors and MOSFETs are appropriately arranged and changing only the wiring mask that interconnects these basic patterns as necessary. Is what you get.
As a result, the mass productivity of various types of semiconductor integrated circuit devices is improved.

A TTL level input signal is applied to the external terminals IN ₁ to IN _n . The input buffer receives these and converts them into the signal level of the CMOS circuit.

The CMOS gate array receives a signal from the input buffer, performs information processing according to its circuit function, and forms an information signal to be output.

The output buffer circuit receives the above-mentioned information signal to be output, and drives an external load as it is or through a predetermined logic process through the external terminals OUT ₁ to OUT _m . This output buffer is designed to have a high TTL level driving capability, thereby achieving higher speed than when a CMOS output buffer is used.

In this case, if the CMOS gate and the TTL output circuit are simply combined, the above-mentioned problem occurs.

Therefore, the TTL output buffer has the following circuit configuration.

A circuit diagram of an embodiment of the TTL output buffer is shown in FIG.

The TTL output buffer of this embodiment has M as its input element.
OSFET is used.

That is, the information signal to be output formed by the CMOS gate array is applied to the gates of the MOSFETs M ₁ to M ₃ . The sources of the MOSFETs M ₁ to M ₃ are not particularly limited, but are grounded, and their drains are commonly provided with a load resistor R ₁ .

The drain outputs of the MOSFETs M ₁ to M ₃ are applied to the base of the phase splitter transistor Q ₁ . The emitter and collector outputs of this transistor Q ₁ are transmitted to a totem pole type output circuit composed of transistors Q ₃ to Q ₅ . In this totem pole type output circuit, the base of the transistor Q ₃ , the transistor Q ₂ provided between the emitters and the resistors R ₅ and R ₆ are active pull-down circuits, and the base of the output transistor Q ₃ at the time of switching to off. This is to forcibly extract the electric charge and to improve the input / output characteristics.

Further, a bias resistor R ₄ is provided between the base and emitter of the output transistor Q ₅ .

A Schottky diode D ₁ is provided between the base of the output transistor Q ₅ and the collector of the transistor Q ₁ for extracting the base charge when the output transistor Q ₅ is switched off. . The above
Other circuits are similar to the known TTL output buffers, except for the inputs by MOSFETs M ₁ to M ₃ .

FIG. 3 is a circuit diagram of a TTL output buffer according to another embodiment of the present invention.

In this embodiment, the following circuit element is added to the second TTL output buffer in order to have an output enable function, in other words, a three-state output function including output high impedance.

The enable signal ▲ ▼ is applied to the gate of MOSFET M ₄ . The source of this MOSFET M ₄ is not particularly limited,
It is grounded and its drain is provided with a load resistor R ₇ .

The drain output of this MOSFET M ₄ is applied to the base of the transistor Q ₆ . In the collector of this transistor Q ₆ ,
Resistance R ₈ is provided. Then, the emitter output is applied to the base of the transistor Q ₈ . This transistor Q ₈
Transistor Q ₇ and resistors R ₉ and R between the base and emitter of
An active pull-down circuit similar to the above, consisting of _10, is provided. The output circuit composed of the transistor Q ₈ and the diodes D ₂ , D ₃ , D ₄ may be the same circuit as the TTL output buffer.

The collector output of the transistor Q ₈ is transmitted to the collector and the base of the phase split transistor Q ₁ via the Schottky diodes D ₃ and D ₄ . A clamp Schottky diode D ₂ is provided between the collectors of the transistors Q ₆ and Q ₈ .

Now, if the enable signal ▲ ▼ is high level, MOSF
ETM ₄ turns on, turning off transistor Q ₆ . When the transistor Q ₆ is turned off, the transistor Q ₈ is turned off, so that the TTL output buffer outputs a TTL level high-level or low-level two-state output signal to its output terminal OUT according to the input signal of its input terminals T ₁ to T _3. To form.

On the other hand, if the enable signal ▲ ▼ is low level, MOSF
ETM ₄ turns off, turning on transistor Q ₆ . Since the transistor Q ₈ is turned on by turning on the transistor Q ₆ , the base potentials of the phase split transistor Q ₁ and the high-level side output transistor Q ₄ are forced to be low level. Therefore, in the TTL output buffer, the output transistors Q ₃ and Q ₅ are both turned off to put the output terminal OUT into a high impedance state regardless of the input signals of its input terminals T ₁ to T ₃ .

According to this embodiment described above, since the MOSFETs M ₁ to M ₄ are used as the input elements of the TTL output buffer, the CM
When viewed from the OS circuit side, its input impedance is high, and since it can be directly driven by a CMOS gate having a small driving capability, the signal delay time here becomes short.

That is, without providing the present invention, when the CMOS output buffer is provided on the CMOS circuit side as described above and the TTL output buffer is driven by such a CMOS buffer, the TTL output buffer requires a relatively large input current. And 1 CM
Since driving multiple TTL output buffers by the OS buffer occurs in some cases, the CMOS buffer must have a large fan-out as described above, and the MOSFET that constitutes the CMOS buffer must be enlarged. You will lose money. The CMOS buffer accordingly constitutes a large capacitive load on the CMOS internal logic circuit, which, in combination with its own operation delay, greatly reduces the overall operation speed.

When the input element of the output buffer is composed of a MOSFET as in the embodiment, such an input MOSFET is provided for driving only the corresponding output transistor, and thus only needs to have a small driving capability. , Can be configured in a small size. Accordingly, the input MOSFET
Will constitute a relatively light load on the internal logic circuit.

Therefore, according to the embodiment, as compared with the case where the CMOS buffer is used, the operation speed can be increased due to the larger current driving capability of the TTL output circuit.

Moreover, since the input element of the TTL output buffer is composed of a MOSFET, a large number of fan-outs of the CMOS gate can be obtained.

Therefore, unlike the conventional TTL output buffer, a buffer circuit required when using a diode or a transistor as an input element becomes unnecessary, and high integration and low power consumption on the gate array side can be achieved.

Further, as the input element, the parallel type as in the above embodiment is used.
If the MOSFETs M ₁ to M ₃ are prepared, the logic processing in the output buffer circuit can be performed.

The present invention is not limited to the above embodiment.

The TTL output buffer is, for example, as shown in FIG.
A similar transistor Q ₁ ′ may be provided in parallel with the phase split transistor Q ₁ so that the logical processing can be performed here as well. In this case, for each of the transistors Q ₁ and Q ₁ ′, for example, the MOS
FET M ₁ to M _3, M ₁ 'to M _3' input circuit constituted by a resistor R _1, R ₁ 'is provided.

Further, to MOSFETM no ₁ as the input element M ₃ and M ₁ '
Alternatively, the level shift diode D ₅ may be provided with the source of M ₃ ′ common.

In this case, the threshold voltage of the above MOSFET M ₁ to M ₃ ′
Forward voltage V _F of diode D ₅ with V _th about 1.6 V
Is about 0.7 volts, the input logic threshold voltage V _LT is about 2.3 volts, which can be approximately matched to the CMOS gate logic threshold.

Furthermore, the signal amplitude at the base of the phase split transistor Q ₁ can be reduced.

That is, the high level is 2V _BE, which is defined by the base-emitter voltage of the transistors Q ₁ and Q ₃ . on the other hand,
The low level becomes V _F + V _ON (voltage between the drain and source of MOSFETs M ₁ to M ₃ etc.) by providing the level shift diode D _5, and is raised by the level shift amount V _F by the diode D ₅ .

Therefore, the signal amplitude is reduced, and the signal transmission speed from the CMOS gate through the TTL output buffer can be increased. Also, since the base current to the phase split transistor Q ₁ can be reduced by the amount of the above swing amplitude being reduced, the power consumption of the TTL output buffer can be reduced by increasing the resistance value of the resistor R _1. You can

The level shift diode D ₅ may be provided on the source side of each MOSFET M ₁ to M ₃ ′ in addition to the common one.

Further, as shown in FIG. 5, MOSFET M ₁ as an input element
Through a common level shift diode on the drain side of M ₃
D ₅ ′ may be provided. In this case, only the input signal amplitude of the phase split transistor (not shown) that receives the signal level-shifted by the diode D ₅ ′ becomes small, and the logic threshold voltage at the input section becomes equal to that of the MOSFETs M ₁ to M ₃ . Threshold voltage V
almost determined by _th . The level shift diode D ₅ ′ may be provided at the drain of each MOSFET M ₁ to M ₃ . However, in the case of the multi-input configuration, it is useful to provide the level shift means in common as in the embodiment of FIG. 4 or 5 in order to reduce the number of elements. The level shift diode may use a diode type transistor, MOSFET, or Schottky diode. Further, also in the circuit for producing the output impedance state (FIG. 3), the level shift means can be provided on the source or drain side of the input MOSFET M ₄ .

The internal logic block may be composed of only n- or p-channel MOSFETs in addition to the CMOS gate array. In this case, the power consumption becomes larger than that in the case of using the CMOS circuit, but the gate integration degree is significantly improved.

A circuit diagram of one embodiment of the TTL input buffer is shown in FIG.

Although not particularly limited, in this embodiment, the pnp transistor Q
The input signal of TTL level is received by ₁₅ and this emitter output is transmitted to the base of the phase split transistor Q ₁₀ similar to the output buffer circuit to drive the similar output circuit. The accompanying circuits of the TTL input and output buffers can be modified in various ways.

INDUSTRIAL APPLICABILITY The present invention can be widely used in digital semiconductor integrated circuit devices such as gate array semiconductor integrated circuit devices, 1-chip microprocessors, microcomputers and the like.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a circuit diagram showing an embodiment of the output buffer, FIG. 3 is a circuit diagram showing another embodiment of the output buffer, and FIG. FIG. 6 is a circuit diagram showing another embodiment of the output buffer, FIG. 5 is a circuit diagram showing another embodiment of the input section of the output buffer, and FIG. 6 is a view showing one embodiment of the input buffer. It is a circuit diagram.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Koshiro Iwasaki 111 Nishiyokote-cho, Takasaki City, Gunma Hitachi Takasaki Plant (72) Inventor Yukio Suzuki 111 Nishiyokote-cho, Takasaki City, Gunma Hitachi, Ltd. Takasaki Factory (72) Inventor Kazuo Yamazaki 111 No. Nishiyote-cho, Takasaki City, Gunma Prefecture Takasaki Factory, Hitachi, Ltd. (56) Reference JP 54-69949 (JP, A) JP 53-126252 JP, A) JP 55-45259 (JP, A) JP 54-148469 (JP, A) JP 56-34229 (JP, A) JP 47-43997 (JP, B1)

Claims (6)

[Claims] 1. A semiconductor integrated circuit device comprising a gate array, wherein an internal logic block composed of a MOSFET and outputs from said internal logic block are provided between said internal logic block and a plurality of external terminals. At least a plurality of output buffers that output signals to be supplied to the corresponding external terminals, and each of the output buffers consists of a MOSFET that receives the output signal of the internal logic block at its gate. An input section having an element, a phase split transistor which receives outputs of the input section and forms first and second signals having mutually opposite phases, and the phase split transistor provided between the power supply terminal and the output terminal of the circuit. First output transistor comprising a bipolar transistor driven by the first signal supplied through the transistor And a second output transistor comprising a bipolar transistor driven between the output signal and the ground terminal of the circuit and driven by the second signal supplied through the phase split transistor. A semiconductor integrated circuit device. 2. The input device comprises a plurality of MOSFETs connected to drive corresponding output transistors according to a combination of a plurality of outputs of the internal logic block. 2. A semiconductor integrated circuit device according to claim 1. 3. The semiconductor integrated circuit device according to claim 1, wherein a level shifting diode is provided on the source side of the MOSFET as the input element. 4. The semiconductor integrated circuit device according to claim 1, wherein a level shift diode is provided on the drain side of the MOSFET as the input element. 5. The output buffer has an input element of MOSF.
5. The semiconductor integrated circuit device according to claim 1, further comprising an output enable circuit made of ET. 6. The semiconductor integrated circuit device according to claim 1, wherein the internal logic circuit block is composed of a CMOS circuit.