JPH0778492A - Nonvolatile storage device - Google Patents

Abstract

PURPOSE:To easily relieve many defects by providing latching circuits holding integer multiple writing data with respect to a readout bit and performing writings onto plural redundant data lines in a flash EEPROM. CONSTITUTION:Writing data of two pairs of memory arrays are held by MOSFETs Q9 and Q10 corresponding to one latching circuit FF and one of voltage supplying MOSFETs Q11 and Q12 corresponding to the circuit FF is selected by a column decoder YDCR1. Moreover, since four latching circuits corresponding to eight pairs of memory arrays are selected by a YDCR4, a writing of the unit of 8 bits is performed substantially in eight numbers of memory arrays having eight pairs of memory arrays respectively and the operation of the writing becomes the same as that of a readout-Latching circuits of a redundant circuit are provided by four numbers in accordance with a normal circuit and redundant data lines of eight lines are provided with respect to one memory array. Thus, the relief of defective data lines of eight lines at the muximum is made possible.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile memory device, for example, a batch erasing type EEPROM (Electrical Erasable & Programmable Read Only.
The present invention relates to a technique effectively used as a defect relief technique for memory).

[0002]

2. Description of the Related Art An electrical batch erasing type EEPROM is a system in which all of the memory cells formed on a chip are collectively operated, or a group of memory cells among the memory cells formed on the chip are collectively operated. It is a non-volatile memory device that has a function of erasing physically. Such a batch erase type EEPR
Regarding OM, the 1980 IEEE SOLID-STA, International, Solid-State Circuits Conference
TE CIRCUITS CONFERENCE) pages 152-153, 1987 IEE, International, Solid-State Circuits Conference (IEEE IN
TERNATIONAL SOLID-STATE CIRCUITS CONFERENCE) Page 76
~ 77, I-E-E-Journal of Solid State Circuits, Vol. 23, No. 5 (198
8 years) pp. 1157 to 1163 (IEEE, J. Solid-State Cic
uits, vol.23 (1988) pp.1157-1163).

FIG. 4 shows a schematic diagram of a cross-sectional structure of a memory cell of an electrically collective erase type EEPROM, which was announced at the International Electron Device Meeting in 1987. The memory cell shown in the figure has a structure very similar to that of a normal EPROM memory cell. That is, a memory cell is an insulated gate field effect transistor (hereinafter referred to as a MOS) having a two-layer gate structure.
FET or simply referred to as a transistor). In the figure, 8 is a P-type silicon substrate, 11 is a P-type diffusion layer formed on the silicon substrate 8, 10 is a low concentration N-type diffusion layer formed on the silicon substrate 8, 9
Are N-type diffusion layers formed in the P-type diffusion layer 11 and the N-type diffusion layer 10, respectively. Further, 4 is a floating gate formed on the P-type silicon substrate 8 via a thin oxide film 7, 6 is a control gate formed on the floating gate 4 via the oxide film 7,
Reference numeral 3 is a drain electrode, and 5 is a source electrode. That is,
The memory cell shown in the figure is constituted by an N-channel MOSFET having a double-layer gate structure, and information is stored in this transistor. Here, the information is substantially retained in the transistor as a change in threshold voltage.

Unless otherwise specified, a case where a memory cell has a transistor for storing information (hereinafter referred to as a storage transistor) of an N-channel type will be described below. The operation of writing information to the memory cell shown in FIG. 5 is similar to that of EPROM. That is,
The writing operation is performed by injecting hot carriers generated in the vicinity of the drain region 9 connected to the drain electrode 3 into the floating gate 4. Due to this write operation, the threshold voltage of the memory transistor seen from the control gate 6 becomes higher than that of the memory transistor which has not performed the write operation.

On the other hand, in the erase operation, the control gate 6 is grounded and a high voltage is applied to the source electrode 5 to generate a high electric field between the floating gate 4 and the source region 9 connected to the source electrode 5. Then, the electrons accumulated in the floating gate 4 are extracted to the source electrode 5 through the source region 9 by utilizing the tunnel phenomenon through the thin oxide film 7. As a result, the stored information is erased. That is, the erase operation lowers the threshold voltage of the memory transistor as viewed from the control gate 6.

In the read operation, the drain electrode 3 and the control gate 6 are applied so that weak writing to the memory cell, that is, undesired injection of carriers into the floating gate 4 is not performed. Voltage is limited to a relatively low value. For example, a low voltage of about 1 V is applied to the drain electrode 3 and a low voltage of about 5 V is applied to the control gate 6.
By detecting the magnitude of the channel current flowing through the storage transistor by these applied voltages, "0" and "1" of the information stored in the memory cell are determined.

Generally, in electrical erasing, if erasing is continued for a long time, the threshold voltage of the storage transistor can be a negative value, unlike the threshold voltage of the storage transistor in a thermal equilibrium state. On the other hand, when the stored information is erased by ultraviolet rays like EPROM, the threshold voltage of the storage transistor which changes by the erase operation settles at the threshold voltage when the storage device is manufactured, that is, The threshold voltage of the storage transistor after the erase operation can be controlled by the manufacturing conditions or the like when manufacturing the memory device.

However, in the case of electrically erasing the stored information, since the stored information is erased by drawing out the electrons accumulated in the floating gate to the source electrode as described above, it takes a relatively long time. If the erase operation is continued, more electrons will be extracted than the amount of electrons injected into the floating gate during the write operation. Therefore, when electrical erasing is continued for a relatively long time, the threshold voltage of the storage transistor becomes a value different from the threshold voltage when manufactured. In other words, when the erase operation is performed, in contrast to the EPROM, the threshold voltage determined by the manufacturing conditions at the time of manufacturing does not settle down.

[0009]

The applicant of the present invention considered to perform a pre-write operation prior to erasing the storage transistor so that the storage transistor does not have a negative threshold voltage. Also, in the writing operation, it was considered to suppress the excessive writing to suppress the variation in the writing amount and to stabilize the erasing operation.
Then, in order to increase the product yield, it was considered to repair the data line with a simple configuration.

An object of the present invention is to provide a non-volatile memory device which realizes data line defect relief with a simple structure. Another object of the present invention is to provide a nonvolatile memory device which suppresses stable erase operation and variation in write amount. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0011]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, in the flash EEPROM, a latch circuit for holding write data consisting of an integral multiple of the read bit is provided, and a plurality of redundancy data are assigned to each redundancy latch circuit provided corresponding to this write data. Make a line.
When a repair address is selected and a write operation is performed, a write signal is supplied to the normal circuit and the redundant data line, and when a repair address is selected and a read operation is performed, the read switch on the normal circuit side is turned off. . In the write verify, the latch circuit corresponding to the bit of which the desired write amount is set is reset, and the bit of which the write amount is insufficient is rewritten with the data of the latch circuit as it is.

[0012]

According to the above-mentioned means, since a plurality of redundant data lines can be written by the latch circuit, many defects can be relieved with a simple structure. For the data line relief, the normal circuit side is cut off in correspondence with the relief address during the read operation, so that the circuit can be simplified. When a write operation is performed by the data held in the latch circuit, the write amount can be prevented from varying by leaving the bit latch circuit corresponding to the insufficient write in the write verify as it is.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 shows an overall block diagram of an electrical batch erasing type EEPROM (hereinafter also referred to as a flash EEPROM) to which the present invention is applied. Although not particularly limited, each circuit block shown in the figure is formed on one semiconductor substrate by a well-known semiconductor integrated circuit technique. Further, in the figure, the mark “◯” indicates an external terminal provided in the flash EEPROM.

In the present application, a signal whose low level becomes an active level is generally an upper line attached to an alphabet indicating a control signal, but a signal corresponding thereto is first marked with / (meaning a bar). expressing. For example, the chip enable signal is represented as / CE.

In the figure, M-ARY-0 to M-AR
Each of Y-7 is a memory array having a similar configuration to each other, and is not particularly limited, but includes a plurality of word lines, a plurality of data lines arranged to intersect these word lines, and a word line. And a memory cell provided at each intersection of the data line and the data line.

XADB is a row address buffer, which receives an external row address signal AX supplied via an external terminal and forms an internal complementary row address signal according to the row address signal AX. XDCR is a row address decoder, and is the row address buffer XADB.
The internal complementary row address signal formed by is received, and the internal row address signal is decoded.

Although not particularly limited, in the present embodiment,
The row address buffer XADB and the row address decoder XDCR are provided in the memory array M-ARY-0.
It is made common to M-ARY-7. That is,
The row address decoder XDCR is instructed by an external row address signal AX from a plurality of word lines in each of the memory arrays M-ARY-0 to M-ARY-7 by decoding an internal complementary row address signal. A word line selection signal for selecting one word line is formed. As a result, each memory array M-AR
One word line commonly used for Y-0 to M-ARY-7 is selected.

With this arrangement, a circuit such as a decoder can be simplified, but the length of the word line becomes long and the memory access becomes slow. Therefore, a shunt aluminum layer is formed on the word line formed of a polysilicon layer integrally formed with the floating gate via an insulating film to reduce the resistance value of the word line. In addition,
Instead of this configuration, the word line may be divided to reduce its length, and a decoder circuit may be provided for each.

In the figure, YADB is a column address buffer, which receives an external column address signal AY supplied through an external terminal and forms an internal complementary column address signal according to the external column address signal AY. YDCR is a column address decoder, which decodes the internal complementary column address signal formed by the column address buffer YADB to form a data line selection signal according to the external column address signal AY. Although not shown in the figure, the memory array M-ARY-
1 to 0-M-ARY-7 designated by the external column address signal AY of the plurality of data lines in the memory array in response to the data line selection signal.
A column switch is provided for coupling the data line of the book to a common data line corresponding to the memory array. Also,
The memory array is provided with redundant data lines as described later, and the decoder YDCR includes a memory circuit for storing a defective address and an address comparison circuit.

Memory array M-ARY-0 to M-ARY
In each of -7, in the read operation, one word line and one data line according to the external row address signal AX and the external column address signal AY are selected, and the selected word line and data line are selected. The memory cell provided at the intersection of is selected. That is, the memory cell coupled to the selected word line and data line is selected from the plurality of memory cells in the entire memory array. As a result, one memory cell is selected from each memory array.

Although not particularly limited, in the present embodiment, it is possible to simultaneously write an integer multiple of the read bit number in the memory array. Therefore, each of the data buffers DIB-0 to DIB7 is provided with a plurality of latch circuits. The write operation is composed of a first write operation of holding the write data in the latch circuit and a second write operation of simultaneously writing the data held in the latch circuit to the memory array. However, if only one latch circuit among the plurality of latch circuits holds the write data and the other latch circuits are in the reset state, the write operation is performed in the unit of 8 bits which is substantially the same as the read operation. It can be carried out.

Taking one memory array M-ARY-0 as an example, in the case of a write operation, the selected memory cells are composed of a plurality of memory cells corresponding to the number of latch circuits. It is coupled to the output node of the data input buffer DIB-0 via MOSFET Q18 which is turned on by wr. In the case of the read operation, one storage transistor is selected by the switch and the sense amplifier SA− is turned on via the MOSFET Q16 which is turned on by the read control signal re.
Tied to 0 input nodes. External input / output terminal I / O0
Is coupled to the input node of the data input buffer DIB-0 and the data output buffer DOB-0.
The output node of the sense amplifier SA-0 is coupled via. Remaining memory arrays M-ARY-1 to M-AR
Also for Y-7, the above-mentioned memory array M-ARY-
Like 0, they are connected to external input / output terminals I / O1 to I / O7.

In the figure, LOGC is an internal circuit for controlling the automatic erase and write operations. Also, CNTR is a timing control circuit, and the external terminal /
In response to an external signal supplied to CE, / OE and / WE and a signal from the internal circuit LOGC, a timing signal including the control signals wr and re described above is formed.

In the figure, Vcc is an external terminal for supplying the power supply voltage Vcc to each timing block, and Vcc
ss is an external terminal for supplying the circuit ground potential Vss to each circuit block. Although not particularly limited, each operating voltage required for the write, read, and erase operations is formed by the power supply voltage by the voltage generating circuit configured by the charge pump circuit included in the timing control circuit CNTR.

FIG. 1 shows one memory array M-ARY in the flash EEPROM shown in FIG.
A block diagram of a column address decoder, a column selection circuit, a redundancy circuit and a write circuit is shown. As can be easily understood from the above description, each circuit element shown in FIG. 1 is not particularly limited, but a well-known CMOS
(Complementary MOS) An integrated circuit is manufactured on a single semiconductor substrate such as single crystal silicon by a manufacturing technique.

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single crystal P-type silicon. The N-channel MOSFET comprises a source region, a drain region, and a polysilicon layer formed on the surface of the semiconductor substrate between the source region and the drain region via a thin gate insulating film between the source region and the drain region. It is composed of such a gate electrode. P-channel MOSFET
Are formed in the N-type well region formed on the surface of the semiconductor substrate. As a result, the semiconductor substrate constitutes a common substrate gate of the plurality of N-channel MOSFETs formed on the semiconductor substrate, and the ground potential Vss of the circuit is supplied. N
The mold well region has a P channel MO formed thereon.
It constitutes the substrate gate of the SFET. P channel MOS
The power supply voltage Vcc is supplied to the substrate gate of the FET, that is, the N-type well region. However, the N-type well region in which the P-channel MOSFET is formed, which constitutes a circuit for processing a high voltage higher than the power supply voltage Vcc, is not particularly limited, but the internally generated high voltage or the like is supplied. .

The integrated circuit may be formed on a semiconductor substrate made of single crystal N-type silicon. In this case, the N-channel MOSFET and the non-volatile memory element are formed in the P-type well region, and the P-channel MOSFET is formed on the N-type semiconductor substrate.

The regular data line is not particularly limited, but is 3
One is selected by the column switch corresponding to the column decoder YDCR with the memory cell array including two data lines as a unit. The column decoder YDCR3 is Y
The address signals A3 to A7 are decoded and one data line is selected. In the figure, three data lines of the above-mentioned 32 data lines are shown as an example, and the switch MOSF
It is selected by ETQ3 to Q5. In the above data line,
Storage transistors are arranged at the intersections with the word lines as shown by way of example.

The memory cell array having the 32 data lines is one memory array M-ARY-0 to M-7.
In, 8 sets are provided for each. In the same figure, four sets of them are shown as representatives. Of the eight sets of memory cell arrays, two sets correspond to four latch circuits FF that hold write data. That is, a writing MO corresponding to one latch circuit FF
Two sets of memory cell arrays are selected by SFETs Q9 and Q10. MOSFETs Q11 and Q12 for supplying a write voltage Vpp are connected in series to the MOSFETs Q9 and Q10. These MOSFETs Q11 and Q12
One is selected by the column decoder YDCR1. The column decoder YDCR1 receives the 1-bit address signal A2 and selects one of the two sets of memory cell arrays. In this way, during the write operation, four write paths are formed in one memory array.

As a result, at the time of the write operation, four latch circuits enable writing of up to 4 bits in one memory array. Since eight memory arrays are provided as described above, writing can be performed in units of 32 bits as a whole. The latch circuit FF
When the output of is set to low level, the corresponding MOS
The FET is turned off. As a result, the write current does not flow in the memory cell, and the selected memory transistor maintains the erased state. Therefore, when the outputs of the four latch circuits FF are set to the low level, substantial writing is not performed. Therefore, when the write data is input to only one latch circuit FF during the write operation in the first stage of fetching the write data to the latch circuit FF, the write operation is formally performed in the unit of 32 bits. However, substantially the same as the read operation, 8
The write operation is performed in bit units.

The four latch circuits FF are selected by the column decoder YDCR4. Address signals A1 and A2 are supplied to the column decoder YDCR. In the write operation in the first stage, the address signals A0 and A1 can be sequentially changed to input write data of up to 4 bits.

On the other hand, during the read operation,
One of the eight memory cell arrays is selected by the column decoder YDCR2. Therefore, the address signal A0 is applied to the column decoder YDCR2.
3 bits of ~ A2 are provided to decode and turn on one switch MOSFET. The common data line passing through these switch MOSFETs is connected to the input terminal of the sense amplifier SA. In the figure, the data output buffer DOB is illustrated to include the sense amplifier SA.

Redundant data lines are provided to relieve defects generated in the normal data lines as described above. Also in the redundant circuit, four latch circuits FF are provided because it is necessary to perform the write operation by the latch circuit as described above. In the figure, two of them are shown as representatives.

The redundant data line is not particularly limited, but is 1
Two redundant data lines are provided for one latch circuit. As described above, since four redundant latch circuits FF are provided corresponding to the normal circuit, eight redundant data lines are provided for one memory array. As a result, a maximum of eight defective data lines can be repaired by the four latch circuits. Latch circuit FF
Output signal is a switch MOS such as MOSFET Q16
Supplied to the FET. These MOSFETQ16 and the like have the MOSFETQ controlled by the selection signal MSi.
17 etc. are connected in series, and these MOSFETQ17
The voltage Vpp for writing is supplied through the above.

The pair of redundant data lines are connected to the MOSFET Q16 and the like corresponding to the latch circuit FF via MOSFETs Q14 and Q15 which are switch-controlled by the selection signal formed by the fuse circuit FUSE. In contrast to such a write path, the read path is connected to the input terminal of the sense amplifier SA via the MOSFET Q13 which is switch-controlled by the signal formed by the fuse circuit FUSE. This lead path is
There are four types corresponding to the latch circuit FF. The signals corresponding to the selection signals of these read paths are used as the signal f for prohibiting the reading of the normal circuit and are performed by the column decoder Y.
It is supplied to DCR2. That is, in the read operation, whichever of the four redundant data lines is selected, the column decoder YDCR2 is controlled by the signal f formed by the selection signal, and the switch MOSFETQ
1, Q2, etc. are turned off and the read path on the normal circuit side is disconnected.

On the other hand, during the write operation, the write path on the normal circuit side is left unchanged. That is,
A write path is always formed on the apparent normal circuit side, and an apparent write operation is performed on a defective data line simultaneously with a write operation on the redundant data line. When the defective data line is selected in the read operation, the read path on the normal circuit side is disconnected so that the read signal from the redundant data line and the read signal from the defective data line do not conflict with each other.

In the defective data line relieving system of this embodiment, the read signal from the redundant data line is effectively taken out by cutting the read path of the defective data line only during the read operation. The circuit for switching the data line to the redundant data line and the control can be simplified. That is, when the Y address is determined to be the relief address, the read path on the normal circuit side corresponding to the Y address needs to be cut by the signal from the fuse circuit FUSE, so that the circuit can be simplified and the switching control can be simplified. Become.

The fuse circuit FUS is not particularly limited.
E stores a repair address by irradiating a fuse made of a polysilicon layer or the like with a laser beam to store the repair address, compares the read signal with an address signal input from the outside, and determines whether or not the repair address is accessed. Whether or not it is determined. The fuse circuit FUSE is provided with eight fuse sets corresponding to each redundant data line, and four fuse sets each identify which redundant data line of the pair is used. . In the figure, an input signal such as an address signal to the fuse circuit FUSE or a decode signal thereof is omitted.

Each of the memory cells provided on the data line and the redundant data line is composed of one storage transistor having a stacked gate structure having a control gate and a floating gate. As described above, the storage transistor is not particularly limited,
The structure is similar to that of the memory transistor of EPROM. However, the point that the erase operation is electrically performed by utilizing the tunnel phenomenon between the floating gate and the source region coupled to the source line as described before or after is that ultraviolet rays are used. This is different from the EPROM erasing method.

The erase mode in the flash EEPROM of this embodiment will be described in detail below with reference to the operation flowchart of FIG. 3 showing an example of the algorithm. The internal circuit LOGC in FIG. 2 functions as an erase control circuit and a write control circuit.

In the flowchart of FIG. 3, a series of pre-write operations as indicated by the dotted line in FIG. 3 are executed prior to the actual erase operation. This is the storage information of the memory cells in the memory array M-ARY before erasing, in other words, the threshold voltage of the storage transistor is the presence or absence of writing as described above (presence or absence of injection of electrons into the floating gate). Performed according to different highs and lows. That is, the memory array M-AR before erasing
This is executed because a storage transistor having a high threshold voltage and a storage transistor having a relatively low threshold voltage are mixed in Y.

The above-mentioned pre-write operation is to write into all the storage transistors prior to the electrical erasing operation. As a result, an internal automatic erase according to this embodiment is performed on a memory cell which is in an erased state, that is, an unwritten memory cell (electrons are not substantially injected into the floating gate of the storage transistor constituting the memory cell). The operation prevents the threshold voltage of the memory transistor in the unwritten memory cell from becoming a negative threshold voltage.

In this prewrite operation, first, in step (1), address setting is performed. That is,
The address counter circuit is set so that an address signal for selecting an individual memory cell is generated by the address counter circuit. By this address setting, although not particularly limited, an address signal designating an address of a memory cell to be written first is generated by the address counter circuit.

In step (2), a write pulse is generated and writing (pre-write) is performed to the memory cell designated by the address signal generated by the address counter circuit.

After this writing, step (3) is executed. In this step (3), an address increment is performed in which the address counter circuit is incremented (+1).

In step (4), it is determined whether the address signal generated by the address counter circuit indicates the final address. If the above prewrite is not performed up to the final address (NO), the process returns to step (2) above and prewrite is performed. This is repeated until the final address. After the step (3) of incrementing the address as described above, it is determined whether or not the pre-write has been performed up to the final address, so the actually determined address is the final address + 1. Of course, the step (3) of address increment may be provided after the step (4) of determining the final address. In this case, when the determination is NO, step (3) is provided on the route returning from step (4) to step (2) so that the address is incremented. When the above prewrite is performed up to the final address (YES),
The following erase operation is performed next.

In step (5), initialization of addresses for erase operation is performed. That is, the address counter circuit is initially designed. In this embodiment, since the memory cells connected to the memory block for which the erase operation is designated are collectively erased, the initial setting of this address has no special meaning in the erase operation itself. This address setting is necessary for the verify operation (erase verify) performed after the erase operation.

In step (6), an erase pulse for collective erase is generated and the erase operation is performed. After that, the verify operation is performed in step (7) according to the address setting. In this verify operation, the read operation is performed under a low voltage such as 3.5 V, which is lower than the voltage for the normal read operation. That is, the address decoders XDCR and YDCR
Also, the operating voltage of the sense amplifier SA is set to a voltage lower than the power supply voltage at the time of reading.

At this time, the operating voltage of the internal circuit LOGC and the timing control circuit CNTR is the power supply voltage Vcc which does not change. In this read operation,
If the read signal is "0", that is, if the memory transistor is turned on, it is recognized that the threshold voltage of the memory transistor is in the erased state of 3.5 V or less. 8) is executed. In this step (8), the address increment of the address counter circuit is performed.

As in the case of the above-mentioned pre-write operation, in step (9), it is determined whether the address signal formed by the address counter circuit indicates the final address. If it is not the final address (NO), the process returns to step (7), and the erase verify operation similar to the above is performed. By repeating this operation until the address counter circuit indicates the final address, the erase operation is completed.

As described above, in the present embodiment, since the stored information in the memory array M-ARY is erased at once, in the above-mentioned erase operation, the threshold voltage of the write operation is the highest among all the memory cells. The number of erases is determined by the memory transistor whose voltage is increased. That is, the erase pulse is applied (erasing operation) in step (6) until the memory transistor having the highest threshold voltage can be read at 3.5 V, that is, the threshold voltage is low.

Then, it is detected by the erase verify operation in step (7) whether or not the storage transistor has the low threshold voltage. That is, the presence or absence of the erase pulse application (erase operation) in step (6) is determined based on the verification result in step (7).

Although not particularly limited, when the number of memory cells to be erased is fixed, steps (4) and (9) are performed.
The final address can be determined by a counting operation. That is, it is performed by detecting that the address has been incremented a predetermined number of times.

[0054]

[Table 1]

Table 1 shows the potential of each word line, data line and source line at the time of erasing and reading and writing as described above in the nonvolatile memory device according to the present invention. In this embodiment, charges and charges are discharged to and from the floating gate for writing and erasing operations according to the relative potential relationship between the word line, the data line and the source line as shown in Table 1 above. , The stored information is read by sensing the change in the threshold voltage corresponding to the charge amount of the floating gate.

The write operation to the memory cell is performed by the above-mentioned FIG.
Can be performed by a step similar to the erasing operation. next,
The write operation will be described with reference to the flowchart of FIG. In steps (5) to (9) of FIG. 3, the step (6) of generating the erase pulse may be replaced with the write pulse generation. In this embodiment, since the write data is fetched into the latch circuit FF and the write operation is performed in the unit of maximum 32 bits, the data is fetched into the latch circuit FF prior to the write operation to the memory cell. The data input operation of the first stage is performed.
This data input is for addressing and inputting data to four latch circuits FF divided into four times.

The inventor of the present application paid attention to the fact that the write operation is performed by inputting the data to the latch circuit FF, and considered to suppress the variation in the write amount. That is, when the latch circuit FF is reset, the write operation to the storage transistor is not performed, and if the desired threshold voltage is obtained in the write verify in step (7), it is dealt with. The latch circuit FF is reset and the process proceeds to step (8). Alternatively, the latch circuit FF is reset after the address increment in step (8).

When it is determined in step (7) that the write amount is insufficient, the write pulse is not immediately generated, but the write pulse is stored and the final address is verified, and then the write amount is insufficient. A write pulse may be generated again or the write operation may be ended depending on the result of determination as to whether or not an object exists. With this configuration, it is possible to make the threshold voltages of the memory transistors in which the writing operation is substantially performed and the threshold voltages of the storage transistors are made uniform only for those for which the writing amount is insufficient. This uniform writing amount brings about a uniform erasing amount in the erasing operation, and the operation can be stabilized as a whole.

The operational effects obtained from the above embodiment are as follows. That is, (1) In the flash EEPROM, a latch circuit that holds write data that is an integer multiple of the read bit is provided, and a plurality of latch circuits are assigned to the redundancy latch circuit that is provided corresponding to the write data. By providing the redundant data line, it is possible to remedy many defective data lines with a simple structure.

(2) When a repair address is selected and a write operation is performed, a write signal is supplied to the normal circuit and the redundant data line, and when a repair address is selected and a read operation is performed, a read operation on the normal circuit side is performed. By turning off the switch, it is possible to obtain an effect that the switching circuit between the defective data line and the redundant data line can be simplified and the switching control can be simplified.

(3) The write circuit is reset by resetting the latch circuit corresponding to the bit for which the desired write amount is set in the write verify, and rewriting the bit for which the write amount is insufficient while leaving the data of the latch circuit as it is. The effect that the variation in the amount can be suppressed can be obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example,
The memory cell may be erased by performing the erase operation in units of word lines by setting the relative potentials of the word line and source line potentials. As the memory transistor forming the memory cell, a FLOTOX type memory transistor using a tunnel phenomenon for the write operation may be used in addition to the stacked gate structure MOS transistor used in the EPROM.

The high voltage for writing / erasing may be entirely or partially supplied from the outside. EEPR
The OM has a circuit portion (CNTR) for controlling normal writing / reading and a circuit portion (LOGC) for controlling an erasing algorithm, as long as the circuit performs the above operation sequence. It doesn't matter. That is, in addition to random logic circuits,
A programmable logic array (PLA), a built-in microcomputer and software, or an asynchronous circuit in the above embodiments may be used, but a synchronous circuit may be used instead. As described above, the circuit that realizes the above operation sequence can adopt various embodiments.

In the above description, for ease of explanation, the pair of regions of the memory transistor are defined as the source region and the drain region. However, the memory in which the source and the drain are determined by the value of the applied voltage. In the transistor, the present invention can be applied by replacing the above-mentioned source region and drain region with one region (node) and the other region (node).

Various specific embodiments of the memory array and its peripheral circuits constituting the EEPROM can be adopted. Furthermore, EEPROM etc.
It may be built in a digital semiconductor integrated circuit device such as a microcomputer. INDUSTRIAL APPLICABILITY The present invention can be widely used for a non-volatile memory device using a storage transistor having a stacked gate structure such as used in EPROM and a FLOTOX type memory transistor, and an information processing system using the same.

[0066]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in the flash EEPROM, a latch circuit for holding write data consisting of an integral multiple of the read bit is provided, and a plurality of redundancy data are assigned to each redundancy latch circuit provided corresponding to this write data. The line can be provided to simplify the circuit. When a relief address is selected and a write operation is performed, a write signal is supplied to the normal circuit and the redundant data line, and when a relief address is selected and a read operation is performed, the read switch on the normal circuit side is turned off. The switching can be simplified. In the write verify, the latch circuit corresponding to the bit for which the desired write amount is set is reset, and for the bit for which the write amount is insufficient, the data in the latch circuit can be rewritten and the write amount can be made uniform.

[Brief description of drawings]

FIG. 1 is a block diagram of a peripheral circuit of a memory array section and a column system showing an embodiment of a batch erase type EEPROM according to the present invention.

FIG. 2 is a schematic block diagram showing an embodiment of the whole batch erase type EEPROM according to the present invention.

FIG. 3 is a flowchart showing an example of an erasing algorithm according to the present invention.

FIG. 4 is a structural cross-sectional view for explaining an example of a conventional memory cell.

[Explanation of symbols]

FF ... Latch circuit, FUSE ... Fuse circuit, Q1-Q
17 ... MOSFET, XADB, YADB ... Address buffer, XDCR, YDCR ... Address decoder, M-
ARY ... Memory array, SA, SA-0 to SA-7 ... Sense amplifier, DIB, DIB-0 to DIB-7 ... Data input buffer, DOB, DOB-0 to DOB-7 ... Data output buffer, CNTR ... Timing control Circuit, RX
... Redundancy selection circuit, SVC ... Source potential control circuit, LOG
C ... Erase control circuit, 3 ... Drain, 4 ... Floating gate, 5 ... Source, 6 ... Control gate, 7 ... Thin oxide film, 8 ... P-type silicon substrate, 9 ... N-type diffusion layer, 1
0 ... Low concentration N-type diffusion layer, 11 ... P-type diffusion layer.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 27/115 29/788 29/792 H01L 29/78 371 (72) Inventor Kenji Kosakai Kodaira, Tokyo 5-20-1 Joumizuhonmachi, Ichi, Ltd. Within the Semiconductor Business Division, Hitachi, Ltd. (72) Inventor Yuji Uji 5-20-1 Joumizuhoncho, Kodaira-shi, Tokyo Hitate Cho-LS Engineering Co., Ltd. Within

Claims (3)

[Claims] 1. The relative potential relationship between a control gate connected to a word line and a data line connected to a drain causes charges to be injected into a floating gate for writing, and a control gate and a source or a drain can be moved relative to each other. A memory array in which non-volatile memory cells are arranged in a matrix so that erase is performed by discharging charges from a floating gate according to a potential relationship, a latch circuit that holds write data that is an integer multiple of a read bit, A nonvolatile memory device comprising: a redundant latch circuit provided corresponding to the write data; and a redundant data line assigned to a plurality of redundant latch circuits. 2. The charge is injected into the floating gate for writing by the relative potential relationship between the control gate connected to the word line and the data line connected to the drain, and the control gate is relative to the source or drain. A memory array in which nonvolatile memory cells are arranged in a matrix so that erase is performed by discharging charges from a floating gate according to a potential relationship, and a column switch for selecting a data line of the memory array is connected in series. And a read switch,
A redundant data line, a write signal is supplied to the normal circuit and the redundant data line when a repair address is selected and a write operation is performed, and a write signal is supplied to the normal circuit side when a repair address is selected and a read operation is performed. A nonvolatile memory device characterized in that a read switch is turned off. 3. A charge is injected into the floating gate for writing by the relative potential relationship between the control gate connected to the word line and the data line connected to the drain, and the control gate is relative to the source or drain. A memory array in which non-volatile memory cells are arranged in a matrix so that erase is performed by discharging charges from a floating gate according to a potential relationship, and a latch circuit that holds write data that is an integer multiple of a read bit are provided. In the write verify, the latch circuit corresponding to the bit set to the desired write amount is reset, and the bit of which the write amount is insufficient is rewritten while leaving the data of the latch circuit as it is. Non-volatile storage device.