JPH0775222B2 - Method for manufacturing InP semiconductor thin film - Google Patents
Method for manufacturing InP semiconductor thin filmInfo
- Publication number
- JPH0775222B2 JPH0775222B2 JP62275684A JP27568487A JPH0775222B2 JP H0775222 B2 JPH0775222 B2 JP H0775222B2 JP 62275684 A JP62275684 A JP 62275684A JP 27568487 A JP27568487 A JP 27568487A JP H0775222 B2 JPH0775222 B2 JP H0775222B2
- Authority
- JP
- Japan
- Prior art keywords
- inp
- gaas
- single crystal
- layer
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
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- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明はInP半導体薄膜の製造方法、更に詳細には、Si
基板上にInP単結晶層をGaAs層等を介して設けたInP半導
体薄膜の製造方法に関する。The present invention relates to a method for manufacturing an InP semiconductor thin film, more specifically, Si
The present invention relates to a method for manufacturing an InP semiconductor thin film in which an InP single crystal layer is provided on a substrate via a GaAs layer or the like.
（従来の技術） Si基板上にInP単結晶層を設けた半導体薄膜（本明細書
においてInP半導体薄膜という）は、InP素子の集積化を
図る上で重要なものである。(Prior Art) A semiconductor thin film in which an InP single crystal layer is provided on a Si substrate (referred to as an InP semiconductor thin film in this specification) is important for the integration of InP elements.
第２図は、従来のInP半導体薄膜の製造説明断面図であ
って、図中、１は（100）表面をもつSi基板、２はInP単
結晶層を示す。このInP半導体薄膜は、減圧MOCVD法（Me
tal Organic Chemical Vapor Deposition:有機金属化学
蒸着法）を用い、かつ、原料としてトリエチルインジウ
ム（TEI）及びホスフィン（PH3）を用いて、Si基板１の
上にInP単結晶層２を直接結晶成長させることにより得
ることができる［応用物理学会予稿集 1986年（春），
第723頁,No.4p−Ｗ−２］。FIG. 2 is a cross-sectional view for explaining the production of a conventional InP semiconductor thin film, in which 1 indicates a Si substrate having a (100) surface and 2 indicates an InP single crystal layer. This InP semiconductor thin film is a low pressure MOCVD method (Me
tal organic chemical vapor deposition (organic metal chemical vapor deposition), and using triethylindium (TEI) and phosphine (PH 3 ) as raw materials, the InP single crystal layer 2 is directly grown on the Si substrate 1. Can be obtained by [Proceedings of the Japan Society of Applied Physics 1986 (Spring),
Page 723, No. 4p-W-2].
（発明が解決しようとする問題点） しかしながら、従来のInP半導体薄膜は、上記の如く、
格子定数が基板であるSiと比べて約８％大きいInPをSi
基板上に直接結晶成長させて作成されていたため、この
格子不整合に起因する結晶欠陥が得られたInP層中に多
く存在し、その結果、InP単結晶層の表面が平坦、か
つ、鏡面でない等、実用上満足のゆくものとは云えなか
った。(Problems to be Solved by the Invention) However, the conventional InP semiconductor thin film has the following problems.
InP has a lattice constant that is about 8% larger than that of Si, which is the substrate.
Since it was created by growing the crystal directly on the substrate, there are many crystal defects due to this lattice mismatch in the InP layer, and as a result, the surface of the InP single crystal layer is flat and not a mirror surface. And so on, I couldn't say that it was practically satisfactory.
（問題点を解決するための手段） 本発明者は、かかる従来のInP半導体薄膜における格子
不整合に起因する結晶欠陥及び表面荒れの問題点を解決
し、InP層の結晶性が更に良好なInP半導体薄膜を提供す
べく種々検討の結果、本発明を完成した。(Means for Solving Problems) The present inventor has solved the problems of crystal defects and surface roughness due to the lattice mismatch in such conventional InP semiconductor thin films, and InP having better InP layer crystallinity. As a result of various studies to provide a semiconductor thin film, the present invention has been completed.
即ち本発明は、Si基板上に第1GaAsバッファ層及びGaAs
単結晶層とが順次積層されてなるもの、の上にInP単結
晶層を成長させるようにした、InP半導体薄膜の製造方
法において、GaAs単結晶層上に第2GaAsバッファ層を450
℃以下の低温で成長させ、当該第2GaAsバッファ層上にI
nPバッファ層及びInP単結晶層を順次成長させるように
したものである。That is, the present invention relates to the first GaAs buffer layer and the GaAs on the Si substrate.
In a method of manufacturing an InP semiconductor thin film, in which a single crystal layer is sequentially laminated, an InP single crystal layer is grown on the second GaAs buffer layer on the GaAs single crystal layer.
It is grown at a low temperature of ℃ or less and I is formed on the second GaAs buffer layer.
The nP buffer layer and the InP single crystal layer are sequentially grown.
（作用） 本発明のInP半導体薄膜に使用されるGaAsは、基板に使
用されるSiと表層となるInPの中間の格子定数を有す
る。従って、GaAsは、Si基板上に直接InP単結晶を成長
させた場合の格子不整合を緩和する作用を有する。(Operation) GaAs used for the InP semiconductor thin film of the present invention has a lattice constant intermediate between that of Si used for the substrate and InP used as the surface layer. Therefore, GaAs has a function of alleviating the lattice mismatch when the InP single crystal is directly grown on the Si substrate.
更に、かかる作用は、Si基板とGaAs単結晶層、及びGaAs
単結晶層とInP単結晶層間に形成されるバッファ層によ
って増長される。Furthermore, such an action is achieved by the Si substrate, the GaAs single crystal layer, and the GaAs.
It is grown by a buffer layer formed between the single crystal layer and the InP single crystal layer.
（実施例） 以上、本発明を実施例を示す図面と共に説明する。(Example) The present invention will now be described with reference to the drawings showing an example.
第１図は、本発明にかかるInP半導体薄膜の構造説明断
面図を示すものであって、図中、１は（100）表面をも
つSi基板、２は第1GaAsバッファ層、３はGaAs単結晶
層、４は第2GaAsバッファ層、５はInPバッファ層、そし
て６はInP単結晶層を示す。FIG. 1 is a sectional view showing the structure of an InP semiconductor thin film according to the present invention, in which 1 is a Si substrate having a (100) surface, 2 is a first GaAs buffer layer, and 3 is a GaAs single crystal. Layer 4 is a second GaAs buffer layer, 5 is an InP buffer layer, and 6 is an InP single crystal layer.
次に、このInP半導体薄膜の製造方法について説明す
る。Next, a method of manufacturing this InP semiconductor thin film will be described.
まず、（100）を表面にもつSi基板１上に第1GaAsバッフ
ァ層、GaAs単結晶層をこの順に重ねて結晶成長させる。
結晶成長は、例えば文献記載の方法に従って行なうこと
ができる［Journal of CryStal Growth,第７巻，第490
〜497頁（1986年）］。First, a first GaAs buffer layer and a GaAs single crystal layer are superposed in this order on a Si substrate 1 having (100) on its surface to grow crystals.
Crystal growth can be performed, for example, according to the method described in the literature [Journal of CryStal Growth, Vol. 7, 490.
~ 497 (1986)].
Si基板１をフッ酸による化学エッチングにより表面酸化
膜を除去した後、結晶成長装置に導入し、アルシンガス
（AsH3）と水素混合ガス中で90℃以上の温度で加熱処理
する。次に、アルシンガス及びトリメチルガリウム（TM
G）を原料として450℃以下の低温で第1GaAsバッファ層
２を膜厚200Å以下に成膜する。次いで、温度を700〜75
0℃に上昇させた以外は前記第1GaAsバッファ層の場合と
同様にして、GaAs単結晶層３を膜厚約１μｍ厚さに結晶
成長させる。尚、Ga源としては、前記TMGの代わりにト
リエチルガルウム（TEG）を用いることができる。かく
して、Si基板１の上に結晶性のよいGaAsの単結晶層を成
長させることができる。After removing the surface oxide film of the Si substrate 1 by chemical etching with hydrofluoric acid, the Si substrate 1 is introduced into a crystal growth apparatus and heat-treated at a temperature of 90 ° C. or higher in a mixed gas of arsine gas (AsH 3 ) and hydrogen. Next, arsine gas and trimethylgallium (TM
The first GaAs buffer layer 2 is formed to a film thickness of 200 Å or less at a low temperature of 450 ° C. or less using G) as a raw material. Then the temperature is 700-75
The GaAs single crystal layer 3 is grown to have a thickness of about 1 μm in the same manner as in the case of the first GaAs buffer layer except that the temperature is raised to 0 ° C. As the Ga source, triethylgalium (TEG) can be used instead of TMG. Thus, a single crystal layer of GaAs having good crystallinity can be grown on the Si substrate 1.
次いで、前記で得られたGaAs単結晶層３の上に第2GaAs
バッファ層４、InPバッファ層５、InP単結晶層６をこの
順に重ねて結晶成長させる。結晶成長は、常法に従って
行なうことができ、前記GaAs単結晶層３の形成後、更に
連続的に上層４〜６を結晶成長させることができるが、
また一度結晶成長装置から結晶を取り出した後再度結晶
成長を行なうことも可能である。次に後者の方法につい
て説明する。Then, a second GaAs is formed on the GaAs single crystal layer 3 obtained above.
The buffer layer 4, the InP buffer layer 5, and the InP single crystal layer 6 are stacked in this order to grow crystals. Crystal growth can be carried out according to a conventional method, and after the GaAs single crystal layer 3 is formed, the upper layers 4 to 6 can be further continuously grown by crystal growth.
It is also possible to take out the crystal from the crystal growth apparatus once and then grow the crystal again. Next, the latter method will be described.
まず、GaAs単結晶層３をアルシンガスと水素混合ガス中
で650℃で約５分間加熱して、その表面の酸化物を除去
する。次に、温度を450℃に下げ、アルシンガス及びTMG
若しくはTEGを原料として第2GaAsバッファ層４を膜厚約
250Åとなるように成膜する。次いで、ホスフィン及び
トリメチルインジウム（TMI）若しくはトリエチルイン
ジウム（TEI）を原料として500℃でInPバッファ層５を
膜厚約200Åに成膜する。続いて、InPバッファ層５を成
膜する場合と比べ、原料としてホスフィン及びTMI若し
くはTEIを使用する点では同じであるが、次に示す如く
組成比の異なる原料を用いて、通常のInPの結晶成長に
使用される温度、即ち600〜650℃でInP単結晶層６を所
定の厚さに成長させる。原料中のホスフィンとTMIのモ
ル比（PH3/TMI）は、InPバッファ層５の成長において
は、約500と非常に大きくとる必要があるのに対し、通
常のInP結晶成長においては、約100となるようにする。First, the GaAs single crystal layer 3 is heated in a mixed gas of arsine and hydrogen at 650 ° C. for about 5 minutes to remove the oxide on the surface. Next, the temperature is lowered to 450 ° C and arsine gas and TMG are added.
Alternatively, the film thickness of the second GaAs buffer layer 4 is made from TEG as a raw material.
The film is formed so that it becomes 250Å. Then, an InP buffer layer 5 is formed to a thickness of about 200Å at 500 ° C. using phosphine and trimethylindium (TMI) or triethylindium (TEI) as raw materials. Subsequently, compared with the case of forming the InP buffer layer 5, the same point is used in that phosphine and TMI or TEI are used as the raw material, but as shown below, a normal InP crystal is formed by using the raw materials having different composition ratios. The InP single crystal layer 6 is grown to a predetermined thickness at the temperature used for growth, that is, 600 to 650 ° C. The molar ratio (PH 3 / TMI) of phosphine and TMI in the raw material needs to be very large, about 500, in the growth of the InP buffer layer 5, whereas it is about 100 in the normal InP crystal growth. So that
この実施例のように、450℃成長の200Å厚のGaAsバッフ
ァ層と500℃成長の250Å厚のInPバッファ層との２層バ
ッファによった場合、結晶の良さを示す、Ｘ線回折にお
けるInP結晶からのピークの半値幅（強度が半分の所の
線幅：角度）が、InPの１層バッファの場合には680アー
クセカンド（arc secant）程度であるのに対し、550arc
secant程度まで向上する。As in this example, the InP crystal in X-ray diffraction showing the goodness of the crystal is shown when a two-layer buffer consisting of a 200 Å thick GaAs buffer layer grown at 450 ° C. and a 250 Å thick InP buffer layer grown at 500 ° C. is used. The peak width at half maximum (line width at half strength: angle) is about 680 arc seconds in the case of InP single-layer buffer, whereas it is 550 arc.
Improves to about secant.
（発明の効果） 本発明のInP半導体薄膜は、叙上の如く、Si基板上にま
ず結晶性がよく格子定数InPとSiの中間にあるGaAs層を
成長させ、その上にInP層を成長させてなるものである
ため、本発明によればSi基板上に直接InP単結晶層を成
長させた従来InP半導体薄膜に比べ、格子不整合を緩和
し、結晶欠陥の発生を低減することができる。又、GaAs
単結晶層上にGaAsバッファ層、InPバッファ層を重ねた
上にInP単結晶層を結晶成長させて得られる本発明のInP
半導体薄膜は、GaAs結晶とInP結晶の格子不整合による
歪みが極めて緩和されたもので、InP単結晶層の結晶性
の極めて良好なものである。(Effects of the Invention) As described above, the InP semiconductor thin film of the present invention is obtained by growing a GaAs layer having good crystallinity on the Si substrate and having an intermediate lattice constant of InP and Si, and then growing the InP layer on the SiP substrate. Therefore, according to the present invention, the lattice mismatch can be relaxed and the occurrence of crystal defects can be reduced as compared with the conventional InP semiconductor thin film in which the InP single crystal layer is directly grown on the Si substrate. Also, GaAs
InP of the present invention obtained by crystal-growing an InP single crystal layer on a GaAs buffer layer and an InP buffer layer stacked on the single crystal layer.
The semiconductor thin film is one in which the strain due to the lattice mismatch between the GaAs crystal and the InP crystal is extremely relaxed, and the crystallinity of the InP single crystal layer is extremely good.
第１図は本発明の一実施例を説明するためのInP半導体
薄膜の断面図、第２図は従来のInP半導体薄膜の構造説
明断面図を示す。 １……Si基板、２……第1GaAsバッファ層、 ３……GaAs単結晶層、 ４……第2GaAsバッファ層、 ５……InPバッファ層、６……InP単結晶層。FIG. 1 is a sectional view of an InP semiconductor thin film for explaining an embodiment of the present invention, and FIG. 2 is a structural explanatory sectional view of a conventional InP semiconductor thin film. 1 ... Si substrate, 2 ... first GaAs buffer layer, 3 ... GaAs single crystal layer, 4 ... second GaAs buffer layer, 5 ... InP buffer layer, 6 ... InP single crystal layer.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 和田 浩 東京都港区虎ノ門１丁目７番12号 沖電気 工業株式会社内 (56)参考文献 特開 昭64−53407（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroshi Wada 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (56) Reference JP-A-64-53407 (JP, A)
Claims (1)
結晶層とが順次積層されてなるもの、の上にInP単結晶
層を成長させるようにした、InP半導体薄膜の製造方法
において、 前記GaAs単結晶層上に第2GaAsバッファ層を450℃以下の
低温で成長させ、 当該第2GaAsバッファ層上に、InPバッファ層及びInP単
結晶層を順次成長させる、 ことを特徴としたInP半導体薄膜の製造方法。1. A method for manufacturing an InP semiconductor thin film, comprising: a first GaAs buffer layer and a GaAs single crystal layer sequentially stacked on a Si substrate; and an InP single crystal layer grown on the Si substrate. A second GaAs buffer layer is grown on a GaAs single crystal layer at a low temperature of 450 ° C. or lower, and an InP buffer layer and an InP single crystal layer are sequentially grown on the second GaAs buffer layer. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62275684A JPH0775222B2 (en) | 1987-11-02 | 1987-11-02 | Method for manufacturing InP semiconductor thin film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62275684A JPH0775222B2 (en) | 1987-11-02 | 1987-11-02 | Method for manufacturing InP semiconductor thin film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01120011A JPH01120011A (en) | 1989-05-12 |
| JPH0775222B2 true JPH0775222B2 (en) | 1995-08-09 |
Family
ID=17558910
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62275684A Expired - Fee Related JPH0775222B2 (en) | 1987-11-02 | 1987-11-02 | Method for manufacturing InP semiconductor thin film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0775222B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01189909A (en) * | 1988-01-26 | 1989-07-31 | Nippon Telegr & Teleph Corp <Ntt> | Composite semiconductor substrate |
| US10096473B2 (en) * | 2016-04-07 | 2018-10-09 | Aixtron Se | Formation of a layer on a semiconductor substrate |
| CN111668090B (en) * | 2020-07-31 | 2023-03-14 | 广东省大湾区集成电路与系统应用研究院 | Semiconductor structure and manufacturing method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0760790B2 (en) * | 1987-05-13 | 1995-06-28 | シャープ株式会社 | Compound semiconductor substrate |
-
1987
- 1987-11-02 JP JP62275684A patent/JPH0775222B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01120011A (en) | 1989-05-12 |
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