JPH0773094A - Memory initialization controller - Google Patents

Abstract

PURPOSE:To provide a memory initialization controller where memory real capacity initialized by means of adopting constitution for simultaneously writing data into plural memories by changing memory arrangement is reduced and the time required for initialization is reduced. CONSTITUTION:Memory arrangement is freely controlled by dynamically changing a memory start address by an address register 26. The memory loaded on a system is divided into the units of slots 22, capacity is made known through a register 25, memory arrangement is changed and data is simultaneously written into the plural memories. Thus, real capacity clearing the memory is reduced and clearing time is speeded up.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory initialization control device in which the memory allocation is variable to reduce the actual capacity for clearing the memory and to speed up the initialization process.

[0002]

2. Description of the Related Art Initialization (clearing) of a memory is essential for creating parity and initializing memory contents at system startup. However, the time required to execute the memory clear increases in proportion to the installed capacity of the memory.

FIG. 4 shows the basic configuration of a computer system.
In the figure, reference numeral 41 is an arithmetic and control unit (CPU), which executes instructions and controls the system. Reference numeral 42 is a main memory (MMU), which is a storage device for temporarily storing data and instructions. Reference numeral 43 is a bus controller (BCU)
It controls the bus and the main memory (MMU) 42. Reference numeral 44 is a bus, and data is transferred through this bus.

In the computer system including the CPU 41 which controls the arithmetic operation, the BCU 42 which controls the memory and the system bus, and the MMU 43 which stores the data and the instruction, the parity generation and the initial data at the time of starting the system are performed. For setting, it is necessary to write initial values to all the memories in the MMU 43 at system startup.

In the conventional memory clear, the entire memory capacity installed is detected, and initial data is sequentially written to each of them by 1 byte. Therefore, as the memory capacity increases, the time required for the memory clear processing increases.

[0006]

The memory configuration of today's computer systems is increasing every day. Therefore, the processing time for memory clear at the time of initial setting tends to increase in proportion to the memory configuration. In the above-mentioned conventional memory clearing means, if the memory is doubled, the processing time for clearing the memory will be doubled. Therefore, it is necessary to shorten the processing time.

The present invention has been made in view of the above circumstances. By adopting a configuration in which the memory arrangement is changed and a plurality of memories are simultaneously written, the actual memory capacity to be initialized is reduced and the initialization is required. It is an object of the present invention to provide a memory initialization control device that reduces time.

[0008]

The memory initialization control device of the present invention divides the memory mounted in the system into predetermined units, checks the capacity of each unit, and determines the area amount required for initialization. The calculation means to be obtained, the address setting means which is provided for each of the above units, and which sets the same start address for memory access, and the area amount which requires the above initialization from the address given by the address setting means. Data writing means for simultaneously writing initial data is provided. As a result, instead of the process of sequentially writing the initialization data to the memory one byte at a time, the start addresses of the plurality of memories are made to be the same, so that one byte is simultaneously written to the plurality of memories. By doing so, it is possible to reduce the total amount of writing in the memory. Since the total write amount is reduced, the processing time is shortened by the reduced amount.

[0009]

In the prior art, as shown in FIG. 1A, the memories are arranged in series at the time of initializing the memory. For this reason, if the memory is expanded, there is a drawback that the area that must be initialized increases by the amount of the expansion and therefore the processing time increases. Therefore, in the present invention, as shown in FIG. 1 (b), at the time of memory initialization, the entire memory is divided into several parts (the divided one unit is called a slot), and the memory of the slot has the same address. Place them in parallel as shown. Then the slot set to the same address will be
Since it seems that there are multiple memories at the same address, only the divided memory can be written simultaneously. Therefore, the area of the parallelized portion can be reduced. Further, if the division unit is less than or equal to the expansion capacity, all the expansion memories are parallelized, so that the time required for memory initialization does not change even if the expansion is expanded. Further, at the time of the original work, if the memories are arranged in parallel, the contents of the memory cannot be read normally, so that they are rearranged in series as shown in FIG. 1B. This speeds up memory clear, which often occupies the CPU self-diagnosis time, and speeds up system startup.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram quoted to facilitate understanding of the present invention, and is a diagram showing an example of a memory arrangement in comparison between a conventional example (a) and the present invention (b).

FIG. 2 is a block diagram showing an embodiment of the present invention. The basic configuration is the same as the conventional example shown in FIG.
The internal structure of the MU and BCU has changed slightly, and the concept is shown.

In the figure, reference numeral 21 is an address bus, and address information indicating which part of the memory 22 (hereinafter referred to as a slot for convenience) to be used is transferred from a CPU (not shown).

Reference numeral 22 is a slot which is a unit of memory division, and instructions and data are stored in this unit. Reference numeral 23 is a line to which an access permission signal is transferred, and is a signal which is set when the address register 26 permits. Reference numeral 24 is a data bus, and the slot 22
Is a bus line used for transferring the contents of the data and the data set in the register 25.

Reference numeral 25 is a register (size register) in which the memory capacity is set, and the memory capacity of each slot 22 is transmitted to the CPU via the data bus 24. Reference numeral 26 is an address register, which compares the address information transferred via the address bus 21 with the slot 22.
A register used to determine which part of the to access.

FIG. 3 is a flow chart showing the operation of the embodiment of the present invention. Hereinafter, the operation according to the embodiment of the present invention will be described with reference to FIGS. Immediately before the memory is cleared, as shown in FIG. 1A, the memories are arranged in series in a serial form. When clearing the memory, the memories are rearranged in parallel as shown in FIG. In the embodiment of the present invention, an example in which all the memories are composed of 4 slots is shown. First, in order to obtain the amount of area (clear account) that actually needs to be initialized when parallelized, the memory capacity of each slot 26 is read by the register 24, the slot showing the maximum capacity is obtained, and this is cleared. And At the same time, in order to match the start address of each slot 22, the address register 1
Set the same value to 6. As an example, all slots 2
In order to set the start address of 2 to "0", "0" is set in the address register 26. If this is done for all slots 22, the address register 2
Since the address of slot 22 is determined by 6,
The address registers 26 match, which enables parallelization.

Next, there is a method of writing the initial data in the slot 22, but if the area for the clear account obtained at the time of parallel arrangement is cleared, the address register 26
Since the enable signal (line 23) is set in each slot 22, the initial data is set in each slot 22 (four parallelized memories in the embodiment of the present invention) at one time. Therefore, the area can be reduced with respect to the serial arrangement.

Although the embodiment of the present invention has been described on the premise of self-diagnosis of the CPU, the present invention is not limited to this, and can be similarly used at the time of initial setting of the input / output module.

[0018]

As described above, according to the present invention, CP
Since the memory clear, which often occupies the U self-diagnosis time, becomes faster, the system starts up faster.

[Brief description of drawings]

FIG. 1 is a diagram quoted to facilitate understanding of the present invention, showing a conventional example (a) and the present invention (b) as examples of memory allocation.
The figure which contrasted and was shown.

FIG. 2 is a block diagram showing an embodiment of the present invention.

FIG. 3 is a flowchart showing the operation of the above embodiment.

FIG. 4 is a block diagram showing a basic configuration of a conventional computer system.

[Explanation of symbols]

21 ... Address bus, 22 ... Slot, 23 ... Access permission signal line, 24 ... Data bus, 25 ... Memory capacity setting register (size register), 26 ... Address register.

Claims (1)

[Claims] 1. A memory unit installed in a system is divided into predetermined units, an arithmetic means for checking a capacity of each unit to obtain an area amount requiring initialization, and a memory provided for each unit, An address setting means for setting the same start address for access; and a data writing means for simultaneously writing initial data by the amount of the area required to be initialized from the address given by the address setting means. A characteristic memory initialization control device.