JPH0766214A - Manufacture of bi-polar semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To solve the problem that a minimum size of photolithography technology has not been made and to make the device higher in performance by forming an element region centered on a base region between element isolation films by photolithography technology with a mask alignment margin taken large enough in its size, CONSTITUTION:Inactive base regions (external bases) 116a, b are formed in self-alignment to a necessary minimum size only around an active base region (internal base) 116. For this purpose, the part on the semiconductor substrate which corresponds to the formation of inactive base regions 16a, b forms an overhanging polycrystalline silicon oxide filth 107, an impurity-containing polycrystalline silicon 108a under the overhang, and inactive base regions 116a, b only around the active base region 115 by diffusion from the polycrystalline silicon 108a by heat treatment.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a bipolar semiconductor integrated circuit device capable of high integration and high speed operation.

[0002]

2. Description of the Related Art As an application of a semiconductor integrated circuit device, especially in a field requiring high speed operation, ECL / CML is generally used.
System bipolar semiconductor circuit device is used.

When the logic amplitude is constant in the ECL / CML system circuit, the operating speed of the circuit is determined by the parasitic capacitance of the elements and wirings forming the circuit, the base resistance of the transistor, and the current gain bandwidth product. Although it is necessary to reduce the parasitic capacitance, in order to reduce the base-collector junction capacitance that makes a large contribution to the operating speed, the base electrode is drawn out of the element region using polycrystalline silicon. There is a method to reduce the base area. Further, a method of forming a polycrystalline silicon resistor and a metal wiring on a thick isolation oxide film to reduce the wiring capacitance is generally adopted.

On the other hand, it is necessary to reduce the base resistance.
To this end, it is conceivable to reduce the resistance of the inactive base layer, bring it closer to the emitter region as much as possible, and reduce the emitter width to reduce the resistance of the active base layer immediately below the emitter.

Further, it is necessary to increase the current gain bandwidth product. It is effective to make the emitter junction and the base junction shallow and thin the epitaxial layer of the collector.

As a conventional technique proposed for realizing these matters, Japanese Patent Laid-Open No. 63-107167 has been proposed.
There is a manufacturing method disclosed in U.S.A., which is shown in FIG. 4 and described below.

First, as shown in FIG. 4A, 200 is formed on the silicon substrate 1 on which the N ⁺ region 5 is formed after the element isolation process.
Polycrystalline silicon 6 having a thickness of 0 to 3000 Å is formed, and a nitride film 7 having a thickness of 1000 to 2000 Å is selectively formed on a portion where a base electrode is to be formed. Next, the polycrystalline silicon 6 is selectively oxidized to produce polycrystalline silicon 6a and 6c as shown in FIG.
Are separated by the polycrystalline silicon oxide film 9 formed by the selective oxidation, and 10 ¹⁵ to 10 ¹⁶ cm ⁻² of boron is ion-implanted into the polycrystalline silicon 6a and 6c through the nitride film 7. Next, as shown in FIG. 4 (C), the oxide film 9 is selectively removed, and the silicon substrate 1 serving as an emitter and a collector is formed.
The surface of (the N ⁺ region 5 and the like are formed) is exposed. Next, the surface and the exposed surfaces of the polycrystalline silicons 6a and 6c are thermally oxidized to form an oxide film 14 of about 1000 Å.
At this time, at the same time, boron is diffused from the polycrystalline silicons 6a and 6c, and a high-concentration inert base (external base) 10 is formed. Next, 1 to 5 × 10 of boron is added through the oxide film 14.
¹³ cm ⁻² ions are implanted and annealed to form an active base (internal base) 11 extending to the inactive base 10 as shown in FIG. 4D, and a CVD film (vapor phase growth film) 15
To the entire surface. Next, the CVD film 15 is etched using reactive ion etching. Subsequently, the oxide film 14 is etched using the CVD film 15 remaining on the side wall of the emitter formation portion as a mask to form an emitter opening. At the same time, the collector electrode extraction portion is also opened, resulting in the structure shown in FIG. Next, as shown in FIG. 4 (F), arsenic-doped polycrystalline silicon 16 is formed to a thickness of 2000 to 4000 Å, an oxide film 17 is formed by thermal oxidation, and at the same time, an emitter 12 is diffused. Finally, contact hole openings and metal electrodes 13a to 13d are formed.

By the above method, the shallow junction of the active base and the emitter and the miniaturization of the emitter width have been realized.
Also, the base-collector junction capacitance can be significantly reduced, and the high-speed operation performance of the transistor can be improved.

[0009]

However, the device obtained by using the above manufacturing method has the following problems.

In the above manufacturing method, after the polycrystalline silicon is formed on the substrate where the element isolation is completed, the pattern of the silicon nitride film is formed by using the photolithography technique.
The pattern of the silicon nitride film basically determines the position of the emitter region with respect to the isolation region. In order to improve the high speed performance of the bipolar transistor, it is preferable that the base resistance is small, and a structure in which the base (external base) is drawn from both sides of the emitter region is often used as shown in FIG. For this reason, the external base is generally in contact with the element isolation film, and the pattern of the silicon nitride film for forming the region is preferably symmetrical with respect to the center of the isolated region. Since the lithographic technique is used, it may be impossible to pull out the base on one side in an extreme case where misalignment occurs. Therefore, this photolithography process significantly changes the performance of the bipolar transistor. Therefore, when forming the isolation region, it is necessary to secure a sufficient mask alignment margin in advance for forming the silicon nitride film pattern, and the base / collector junction area must be increased more than necessary for device operation. There was a flaw.

Further, with the above manufacturing method, it has been impossible to miniaturize the inside of the element-isolated region to the minimum dimension of the photolithography technique.

As described above, according to the present invention, in the conventional manufacturing method, a fine pattern must be formed inside the element-isolated region by using the photolithography technique. The problem that the minimum dimension of the lithography technology cannot be achieved, which hinders the high performance of the bipolar transistor, is that the inactive base region (external base) is changed to the active base region (internal base).
It is an object of the present invention to provide a manufacturing method for realizing a higher performance device by solving the problem by forming the device only in the periphery in a self-aligned manner.

[0013]

To achieve the above object, the present invention provides a method for manufacturing a bipolar semiconductor integrated circuit device, wherein an inactive base region (external base) is provided only around an active base region (internal base). In other words, the minimum necessary size of the inactive base region is formed in a self-aligned manner so as not to come into contact with the element isolation oxide film. As a method for forming the polycrystalline silicon oxide film, a portion corresponding to the formation of the inactive base region on the semiconductor substrate forms an eaves-shaped polycrystalline silicon oxide film, and polycrystalline silicon containing impurities is formed under the eaves. The inactive base region is formed only around the active base region by diffusion from crystalline silicon.

[0014]

As described above, according to the present invention, the inactive base region is formed around the active base region in the minimum necessary size in a self-aligned manner. Need not be secured as in the prior art, the parasitic capacitance can be reduced, and the high-speed operation of the transistor can be improved.

[0015]

Embodiments of the present invention will be described in detail below with reference to the drawings.

1 to 3 (A) to 3 (M) are sectional structural views showing a manufacturing process of an embodiment of the present invention.

As shown in FIG. 1A, as in the prior art, an N ⁺ buried diffusion layer 102 of antimony or the like is formed on a p-type substrate 101, and a single crystal silicon 103 containing phosphorus at a concentration of about 10 ¹⁶ / cm is formed thereon. After epitaxial growth of 8 μm, the device isolation film 1
This is a structure in which 04 is formed.

Then, as shown in FIG.
First polycrystalline silicon film 10 which is a conductive film having a thickness of 3 μm
5 is formed by a CVD (Chemical Vapor Deposition) method, and then silicon nitride, which is an oxidation resistant film of about 0.15 μm, is formed on a region where a future device region is formed by using a photolithography technique and an etching technique. The films 106a and 106b are selectively formed.

At this time, although not shown, an oxide film as an insulating film may be formed under the polycrystalline silicon film 105. This is a post-process shown in FIG.
The epitaxial layer 1 serves as a stopper when etching the polycrystalline silicon 108a in the collector extraction region.
This is because etching damage is not given to 03.

Further, at this time, the minimum dimension of the photolithography technique is 1 for a transistor requiring high speed performance.
It is desirable to form 06a and 106b.

Subsequently, as shown in FIG. 1C, selective oxidation is performed using the silicon nitride films 106a and 106b as masks to obtain a polycrystalline silicon oxide film 107. At this time,
When a so-called bird's beak is formed by advancing lateral oxidation along the bottom surfaces of the silicon nitride films 106a and 106b, an inclined shape is formed in the first polycrystalline silicon film 105. Here, the first polycrystalline silicon 108a below the silicon nitride films 106a and 106b not selectively oxidized is
108b. (At this time, the polycrystalline silicon oxide film 107 has a thickness of about 6000 Å).
As shown in (D), the silicon nitride films 106a and 106a
b is removed, and 20-40 keV is used by the ion implantation method.
With a accelerating energy of 10 ¹⁵ to 10 ¹⁶ cm ^-2 of boron to form a conductive film on the entire surface, and then 900 ° C. to 1
Boron is diffused in the polycrystalline silicons 108a and 108b by performing heat treatment at 000 ° C. for about 40 minutes.

Next, as shown in FIG. 2E, anisotropic etching is performed to etch the polycrystalline silicons 108a and 108b in the emitter / collector extraction regions.
At this time, as described above, the polycrystalline silicon film 105
If there is an oxide film underneath (partially becoming the polycrystalline silicon oxide film 107 in this step), it serves as a stopper for the etching, but thereafter the exposed oxide film is removed. And
The N ⁻ type epitaxial layer 103 is exposed. At this time,
Under the eaves of the polycrystalline silicon oxide film 107, the polycrystalline silicons 108a and 108b remain. After that, using the resist pattern, the polycrystalline silicon 108b on the collector region side (right side in the drawing) is removed (the emitter side (left side in the drawing) is left), and then the resist is removed.

Subsequently, as shown in FIG. 2F, the polycrystalline silicon oxide film 107 is removed to about 4000 by using a buffered hydrofluoric acid solution.
Å About etching. At this time, the polycrystalline silicon 108
The inclined portion of a is exposed. Further, if an oxide film is formed under the polycrystalline silicon film 105 described above by the etching, the exposed oxide film is completely removed here.

Next, as shown in FIG. 2G, a second polycrystalline silicon film 109 of about 3000 Å is formed on the entire surface by the CVD method. After that, the step portion (the recesses on the emitter side and the collector side formed up to the above step) is buried using the resist 110, and then boron is ion-implanted at an acceleration energy of about 15 to 20 keV and a dose amount of 3 to. ^Implant 5 × 10 ¹⁶ cm ^-2 , about 900 ℃,
By performing heat treatment for about 30 to 40 minutes, it is diffused in the second polycrystalline silicon 109 (boron is not diffused in the illustrated polycrystalline silicon 111 portion).

Next, as shown in FIG. 2H, the polycrystalline silicon 109 is etched using an alkaline etching solution such as KOH. Then, the resist 110
Part of the N ⁻ -type epitaxial layer 1 is not etched because the high concentration of boron is not etched, and the polycrystalline silicon 111 in which boron is not diffused is etched as shown in the figure.
03 is exposed.

Then, as shown in FIG. 3 (I), CV
The third polycrystalline silicon film 113 is formed by using the D method. Next, after burying a resist in the recess 112, boron of a dose amount of 10 ¹⁵ to 10 ¹⁶ cm ^-2 is added to the polycrystalline silicon 1 with an acceleration energy of 20 to 40 keV by using an ion implantation method.
13 to remove the resist in the recess 112,
The polycrystalline silicon 113 formed on the entire surface including the bottom of the recess 112 by thermal oxidation at 800 to 900 ° C. is used as a silicon oxide film 114 as shown in FIG.

At this time, since there is no resist, the polycrystalline silicon region other than the recess 112, which is heavily doped with boron, has a higher oxidation rate than the polycrystalline silicon region at the bottom of the recess 112, which is 2-3 times higher. Thickness of silicon oxide film 1
14 will be formed.

Next, as shown in FIG. 3K, the silicon oxide film 114 is anisotropically etched to expose the N ^-- type epitaxial layer 103. At this time, the silicon oxide film 114 on the second polycrystalline silicon 109 remains because of the film thickness difference.

Subsequently, the N ^-- type epitaxial layer 103 is thinly oxidized to form a silicon oxide film (not shown) of about 50 to 100 Å, and then a resist pattern is used to selectively ion-inject only the internal base region 115. Then, boron is implanted (acceleration energy is 10 to 30 keV, dose is about 10 ¹³ cm ^-2 ) and the resist is removed after the base region 115 is formed.

Next, annealing is performed to connect the internal base region (active base) 115 and the external base regions (inactive base) 116a and 116b formed by diffusion of boron from the polycrystalline silicon 108a to the internal base 115. To do. At this time, the external bases 116a, 116
Since b is diffused, the portion opposite to the internal base 115 comes into contact with the polycrystalline silicon oxide film 107 which is a conductive film.

That is, the external base regions 116a, 116
b is formed around the internal base region 115 in a self-aligned manner.

Next, as shown in FIG. 3L, after removing the thin silicon oxide film (not shown) on the N ^-- type epitaxial layer 103, polycrystalline silicon is formed and ion implantation is used. Arsenic is implanted into this polycrystalline silicon (acceleration energy is 40 keV, dose is about 10 ¹⁶ cm ^-2 ) to form an emitter polycrystalline silicon electrode 117a and a collector polycrystalline silicon electrode 117b.

Arsenic-doped polycrystalline silicon 11
7a and 117b are covered with silicon oxide film 118, and then annealed to diffuse arsenic from polycrystalline silicon 117a and 117b to form emitter region 119.

At this time, arsenic is also diffused in the collector lead-out portion 120 to lower the collector resistance. After this,
As shown in FIG. 3M, the contact holes of the emitter / base collector are opened, and the metal electrodes 121a,
121b and 121c are formed.

[0035]

As described in detail above, according to the present invention, the inactive base region in the bipolar semiconductor integrated circuit device is formed in a self-aligned manner only around the active base region.・ It has become possible to significantly reduce the junction capacitance between collectors. That is,
Conventionally, it was necessary to form the inactive base region in a wide region up to the edge of the isolation oxide film including the mask alignment margin between the active base region and the element isolation oxide film region. Despite the mask alignment margin of the nitride film pattern, the minimum necessary inactive base region can be formed without contacting the element isolation film only around the active base region, and the parasitic capacitance can be reduced. High-speed operation has become possible. Further, it is not necessary to secure a large margin for mask alignment at the time of forming a nitride film pattern as in the conventional case, which greatly contributes to miniaturization.

[Brief description of drawings]

FIG. 1 is a process sectional view of an embodiment of the present invention (No. 1)

FIG. 2 is a process sectional view of the embodiment of the present invention (No. 2)

FIG. 3 is a process sectional view of the embodiment of the present invention (No. 3)

FIG. 4 is a process sectional view of a conventional example.

[Explanation of symbols]

 101 substrate (p-type) 103 epitaxial layer (n-type) 104 element isolation film 105 first polycrystalline silicon film 106a, b silicon nitride film 107 polycrystalline silicon oxide film 108a, b polycrystalline silicon film 109, 111 second Polycrystalline silicon film 110, 112 Resist 113 Third polycrystalline silicon film 114, 118 Silicon oxide film 115 Internal base region (active base) 116a, b External base region (inactive base) 117a Emitter electrode 117b Collector electrode 119 Emitter region

Claims (2)

[Claims] 1. A step of: (a) forming a first conductive film on a semiconductor substrate, and forming an oxidation resistant film on the first conductive film at a predetermined position corresponding to at least a portion to be an emitter / base region of a transistor. (B) The first conductive film is oxidized by using the oxidation resistant film as a mask, and the first conductive film is oxidized to form a bird's beak under the oxidation resistant film,
Then, the oxidation resistant film is removed, impurities are introduced, and the oxidized first conductive film and the unoxidized first conductive film are conductive due to the mask of the oxidation resistant film. Forming a conductive film, (c) removing the first conductive film under the oxidation resistant film so that the first conductive film remains under the eaves shape by the bird's beak, d) A second conductive film is formed on the entire surface, and at least the recess corresponding to the emitter formation region of the structure formed up to this point is filled with a resist to introduce impurities so that the impurities are not diffused to the bottom of the recess. And (e) a step of forming an opening in at least a portion corresponding to the emitter formation region of the second conductive film, (f) a third conductive film formed over the entire surface, and a structure formed thereby. At least the recess corresponding to the emitter formation region A step of burying a resist in the step of introducing impurities to prevent the impurities from diffusing into the bottom surface of the recess, (g) removing the resist, converting the third conductive film into an insulating film, and at least corresponding to the emitter formation region A step of forming an opening in the portion of (c), (h) an impurity is introduced into the semiconductor substrate on the bottom surface of the opening to form an active base region, and the first impurity-containing first step is added. And a step of forming an inactive base region by diffusing impurities from the conductive film to a semiconductor substrate thereunder, the method for manufacturing a bipolar semiconductor integrated circuit device, comprising: 2. An insulating film is formed under the first conductive film in the step (a), and the first conductive film under the oxidation resistant film in the step (c) is removed. 2. The method for manufacturing a bipolar semiconductor integrated circuit device according to claim 1, further comprising a step of removing at least the insulating film in a portion corresponding to the emitter formation region.