JPH0766406A - Self-aligned silicide mosfet and its manufacture - Google Patents
Self-aligned silicide mosfet and its manufactureInfo
- Publication number
- JPH0766406A JPH0766406A JP21058493A JP21058493A JPH0766406A JP H0766406 A JPH0766406 A JP H0766406A JP 21058493 A JP21058493 A JP 21058493A JP 21058493 A JP21058493 A JP 21058493A JP H0766406 A JPH0766406 A JP H0766406A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- refractory metal
- film
- gate
- entire surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 16
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000003870 refractory metal Substances 0.000 claims description 29
- 238000005530 etching Methods 0.000 claims description 21
- 150000004767 nitrides Chemical class 0.000 claims description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 11
- 230000008018 melting Effects 0.000 abstract description 2
- 238000002844 melting Methods 0.000 abstract description 2
- 239000002184 metal Substances 0.000 abstract description 2
- 229910052751 metal Inorganic materials 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 6
- 239000010936 titanium Substances 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、サリサイド型ＭＯＳＦ
ＥＴの構造及びその製造方法に関するものである。FIELD OF THE INVENTION The present invention relates to a salicide type MOSF.
The present invention relates to a structure of ET and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】ＭＯＳＦＥＴ（Ｍｅｔａｌ Ｏｘｉｄｅ
Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｆｉｅｌｄ Ｅｆｆｅ
ｃｔ Ｔｒａｎｓｉｓｔｏｒ）が縮小化されるにしたが
い、そのゲート長が短くなり、また、短チャネル効果を
抑制するため、ソース・ドレイン領域の接合深さＸｆ
は、浅くせざるを得ない。ゲート長が短くなり、ＭＯＳ
ＦＥＴのオン抵抗は下がり、一方でＸｊが浅くなるた
め、ソース・ドレインのシート抵抗は増大する。2. Description of the Related Art MOSFET (Metal Oxide)
Semiconductor Field Effe
As the ct Transistor) becomes smaller, its gate length becomes shorter, and in order to suppress the short channel effect, the junction depth Xf of the source / drain region is reduced.
I cannot help making it shallow. Gate length is shortened, MOS
The on-resistance of the FET decreases, while Xj becomes shallow, so that the sheet resistance of the source / drain increases.
【０００３】したがって、ゲート長がサブミクロン領域
のＭＯＳＦＥＴでは、ソース・ドレインのシート抵抗
が、ＭＯＳＦＥＴのオン抵抗に対して無視し得なくな
り、ＭＯＳＦＥＴの駆動力がソース・ドレイン領域の寄
生抵抗により低下する問題が顕著となる。このような問
題に対して、ソース・ドレイン及びゲートをセルフ・ア
ライメントにシリサイド化し、シート抵抗を下げるサリ
サイド・プロセスがある。Therefore, in a MOSFET with a gate length in the submicron region, the sheet resistance of the source / drain cannot be ignored with respect to the on-resistance of the MOSFET, and the driving force of the MOSFET is reduced by the parasitic resistance of the source / drain region. The problem becomes noticeable. For such a problem, there is a salicide process in which the source / drain and the gate are silicided by self-alignment to reduce the sheet resistance.
【０００４】図２に、従来より使われてきたサリサイド
型ＭＯＳＦＥＴ・プロセスをチタン・サリサイドを例に
示す。 （１）まず、図２（ａ）に示すように、通常製造工程に
したがって、半導体基板１上にフィールド酸化膜２を形
成後、ゲート電極３、サイドウォール４、ソース・ドレ
イン層５を形成する。FIG. 2 shows a salicide type MOSFET process which has been conventionally used, taking titanium salicide as an example. (1) First, as shown in FIG. 2A, a field oxide film 2 is formed on a semiconductor substrate 1 and then a gate electrode 3, sidewalls 4, and source / drain layers 5 are formed according to a normal manufacturing process. .
【０００５】（２）次に、図２（ｂ）に示すように、全
面にＴｉ膜６を堆積する。 （３）次に、図２（ｃ）に示すように、７００℃で１０
秒程度のアニールにより、ソース・ドレイン及びゲート
のシリコン層とＴｉ膜６が接しているところで、シリサ
イド７化を起こさせる。その後、フィールド酸化膜２
上、サイドウォール４上の未反応Ｔｉを選択エッチング
により除去する。その後、９００℃で１０秒程度のシリ
サイド低抵抗化アニールを行なう。(2) Next, as shown in FIG. 2B, a Ti film 6 is deposited on the entire surface. (3) Next, as shown in FIG.
By annealing for about a second, silicide 7 is formed where the silicon layers of the source / drain and the gate are in contact with the Ti film 6. After that, the field oxide film 2
Unreacted Ti on the upper and sidewalls 4 is removed by selective etching. Then, silicide low resistance annealing is performed at 900 ° C. for about 10 seconds.
【０００６】（４）その後、通常プロセスにしたがっ
て、図２（ｄ）に示すように、中間膜８を堆積し、コン
タクトホール９を開口し、配線層１０を形成し、最後に
保護膜１１を形成する。(4) Then, according to a normal process, as shown in FIG. 2D, an intermediate film 8 is deposited, contact holes 9 are opened, a wiring layer 10 is formed, and finally a protective film 11 is formed. Form.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、以上述
べた従来のサリサイド型ＭＯＳＦＥＴにおいても、今後
ゲート長がさらに短くなるにしたがい、以下の問題があ
る。まず、ゲート長が０．３μｍ，０．２μｍ，０．１
μｍと短くなるにしたがい、シリサイド化されたゲート
においても、そのゲートの抵抗が回路の高速動作を阻害
するようになる。すなわち、ゲート長０．２μｍ，ゲー
ト幅２０μｍ，通常シリサイドのシート抵抗を５Ω／□
とすると、２０μｍ幅のゲートのみで５００Ωの抵抗と
なり、０．２μｍ時代のＭＯＳＦＥＴのオン抵抗（２０
μｍ幅，０．６ｍＡ／μｍとすると１７０Ω）より十分
大きくなり、回路の高速動作の劣化要因となる。However, the conventional salicide type MOSFET described above also has the following problems as the gate length is further shortened in the future. First, the gate length is 0.3 μm, 0.2 μm, 0.1
As the gate length becomes as short as μm, the resistance of the gate also hinders the high-speed operation of the circuit even in the silicided gate. That is, the gate length is 0.2 μm, the gate width is 20 μm, and the sheet resistance of normal silicide is 5 Ω / □.
Then, the resistance of 500Ω becomes only with the 20 μm wide gate, and the on-resistance (20
If the width is μm and 0.6 mA / μm, it becomes sufficiently larger than 170Ω), which becomes a cause of deterioration of high-speed operation of the circuit.
【０００８】また、サイドウォール下のサリサイド化さ
れていないソース・ドレイン領域のシート抵抗が無視し
得なくなり、これがサリサイド型ＭＯＳＦＥＴであって
も、電流駆動力を下げる原因となる。本発明は、以上述
べたゲート寸法が縮小化されるに伴うゲート抵抗の増大
をなくし、回路の高速動作を図り得るサリサイド型ＭＯ
ＳＦＥＴ及びその製造方法を提供することを目的とす
る。Further, the sheet resistance of the non-salicided source / drain regions under the side wall cannot be ignored, and this causes a reduction in current driving force even in a salicide type MOSFET. The present invention eliminates the increase in the gate resistance accompanying the reduction in the gate size described above, and enables a high-speed operation of the circuit.
It is an object to provide an SFET and a manufacturing method thereof.
【０００９】[0009]
【課題を解決するための手段】本発明は、上記目的を達
成するために、 （Ａ）サリサイド型ＭＯＳＦＥＴにおいて、ゲート電極
の両側面の少なくとも一部に形成される高融点金属シリ
サイドを設けるようにしたものである。また、更に、前
記ゲート電極のサイドウォール絶縁膜の下方の少なくと
も一部に形成される高融点金属シリサイドを設けるよう
にしたものである。In order to achieve the above object, the present invention provides (A) a salicide type MOSFET with a refractory metal silicide formed on at least a part of both side surfaces of a gate electrode. It was done. Further, a refractory metal silicide formed on at least a part of the side wall insulating film of the gate electrode is provided.
【００１０】（Ｂ）また、サリサイド型ＭＯＳＦＥＴの
製造方法において、ゲート電極形成後、全面に酸化膜を
堆積する工程と、全面に窒化膜を堆積し、異方性エッチ
ングにより窒化膜サイドウォールを形成する工程と、前
記酸化膜を前記ゲート電極の両側面が一部露出し、窒化
膜サイドウォール下のシリコン基板が一部露出するよう
にエッチングする工程と、全面に高融点金属を堆積する
工程と、シリサイド化反応を行い、未反応高融点金属を
除去する工程とを施すようにしたものである。(B) In the method of manufacturing a salicide type MOSFET, a step of depositing an oxide film on the entire surface after forming the gate electrode and a step of depositing a nitride film on the entire surface and forming a nitride film sidewall by anisotropic etching. And a step of etching the oxide film so that both side surfaces of the gate electrode are partially exposed and a silicon substrate under the nitride film side wall is partially exposed, and a step of depositing a refractory metal on the entire surface. , A step of performing a silicidation reaction and removing unreacted refractory metal.
【００１１】（Ｃ）更に、サリサイド型ＭＯＳＦＥＴの
製造方法において、ゲート電極形成後、全面に絶縁膜を
堆積する工程と、異方性エッチングによりゲート電極両
側面の一部分が露出するまでエッチングを行う工程と、
全面に高融点金属を堆積する工程と、シリサイド化反応
を行い、未反応高融点金属を除去する工程とを施すよう
にしたものである。(C) Further, in the method of manufacturing a salicide type MOSFET, after the gate electrode is formed, a step of depositing an insulating film on the entire surface and a step of performing anisotropic etching until a part of both side surfaces of the gate electrode are exposed. When,
A process of depositing a refractory metal on the entire surface and a process of performing a silicidation reaction to remove unreacted refractory metal are performed.
【００１２】[0012]
【作用】本発明によれば、上記したように、高集積化に
伴いゲート寸法が縮小化される場合でも、ゲート電極の
少なくとも両側面の一部がシリサイド化されるため、ゲ
ート電極の低抵抗化を図ることができる。また、サイド
ウォールを一部除去して、ソース・ドレイン上のシリサ
イド化をゲート近傍まで近づけるようにしたので、サイ
ドウォール下の寄生抵抗を低減することができる。According to the present invention, as described above, even when the gate size is reduced due to high integration, since at least a part of both side surfaces of the gate electrode is silicidized, the low resistance of the gate electrode is obtained. Can be realized. Further, since the sidewalls are partially removed so that the silicidation on the source / drain is brought close to the vicinity of the gate, the parasitic resistance under the sidewall can be reduced.
【００１３】しかも、上記（Ｂ）において、窒化膜下
は、スパッタリング時の回り込みにより、高融点金属を
堆積するようにしているため、奥に行くほど、つまりゲ
ート電極側に行くほど、高融点金属は薄くなり、ソース
・ドレインの接合深さ、及び不純物濃度もゲート電極側
に近づくほど浅くなるため、接合リーク電流を低減でき
る。In addition, in (B) above, since the refractory metal is deposited under the nitride film due to the wraparound during sputtering, the refractory metal becomes deeper toward the back, that is, toward the gate electrode side. Becomes thinner, and the junction depth of the source / drain and the impurity concentration become shallower toward the gate electrode side, so that the junction leak current can be reduced.
【００１４】また、上記（Ｂ）において、窒化膜サイド
ウォールとゲート電極の間、及び窒化膜サイドウォール
とシリコン基板の間を１０００Å程度エッチングする間
に、ゲート電極表面、ソース・ドレインとなるシリコン
基板表面の酸化膜を確実にエッチング除去できるため、
安定したシリサイド形成が可能となる。Further, in the above (B), the silicon substrate to be the surface of the gate electrode and the source / drain is etched while etching between the nitride film side wall and the gate electrode and between the nitride film side wall and the silicon substrate by about 1000Å. Since the oxide film on the surface can be reliably removed by etching,
Stable silicide formation is possible.
【００１５】[0015]
【実施例】以下、本発明の実施例について図を参照しな
がら詳細に説明する。図１は本発明の第１の実施例を示
すサリサイド型ＭＯＳＦＥＴの製造工程断面図である。
ここでは、ＮチャネルＭＯＳＦＥＴの例で示す。 （１）まず、図１（ａ）に示すように、Ｐ型シリコン基
板２１上にフィールド酸化膜２２（約４０００Å）を通
常のＬＯＣＯＳ法で形成する。その後、ゲート酸化膜２
３（約１００Å）を形成し、更に、ＬＰＣＶＤにより、
ゲート電極となる多結晶シリコン膜２４を約３０００Å
堆積する。通常のホトリソエッチングにより、ゲート電
極のパターン形成を行なう。２５はＬＤＤ層である。Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a sectional view of a salicide type MOSFET manufacturing process showing a first embodiment of the present invention.
Here, an example of an N-channel MOSFET is shown. (1) First, as shown in FIG. 1A, a field oxide film 22 (about 4000 Å) is formed on a P-type silicon substrate 21 by a normal LOCOS method. After that, the gate oxide film 2
3 (about 100 Å) is formed, and further by LPCVD,
Approximately 3000 Å of the polycrystalline silicon film 24 to be the gate electrode
accumulate. The gate electrode pattern is formed by ordinary photolithographic etching. Reference numeral 25 is an LDD layer.
【００１６】（２）次に、図１（ｂ）に示すように、全
面にＬＰＣＶＤにより、酸化膜２６を３００Å〜７００
Å程度堆積する。この場合、成膜条件として、温度を下
げる等により粗な膜として、後の工程（４）〔図１
（ｄ）参照〕における酸化膜ウェットエッチング時にフ
ィールド酸化膜２２より十分速くエッチングが進む膜質
とする。その後、プラズマＣＶＤにより、１５００Å程
度の窒化膜２７を堆積する。この場合、膜質としては、
ＲＦパワーを下げる等により、低ストレスな膜質とし、
シリコン中に欠陥が入るのを防止する必要がある。(2) Next, as shown in FIG. 1 (b), an oxide film 26 is formed on the entire surface by LPCVD to a thickness of 300Å to 700.
Å Deposit about. In this case, as a film forming condition, a rough film is formed by lowering the temperature, and the subsequent step (4) [FIG.
(See (d)) When the oxide film is wet-etched, the film quality is such that the etching progresses sufficiently faster than the field oxide film 22. After that, a nitride film 27 of about 1500 Å is deposited by plasma CVD. In this case, as film quality,
By reducing the RF power, etc., a low-stress film quality is obtained,
It is necessary to prevent defects from being introduced into silicon.
【００１７】（３）次に、図１（ｃ）に示すように、異
方性エッチングにより、窒化膜２７をエッチングし、１
５００Å程度の幅を持つサイドウォール２８を形成す
る。その後、サイドウォール２８をマスクにしてシリコ
ン中へソース・ドレイン形成用不純物注入を行い、ソー
ス・ドレイン層２９を形成する。 （４）次に、図１（ｄ）に示すように、フッ酸系のエッ
チャントにより、前記工程（２）〔図１（ｂ）参照〕で
堆積した酸化膜２６をエッチング除去し、さらに窒化膜
サイドウォール２８の下、及びゲート電極を構成する多
結晶シリコン膜２４と挟まれた部分の酸化膜をも１００
０Å程度エッチング除去する。引き続き、Ｔｉ等の高融
点金属膜３０を全面にスパッタリングにより、３００〜
４００Å程度堆積する。この場合、例えば、ＥＣＲ共鳴
周波数の高い８７５ＭＨｚ×２倍等のスパッタリングに
より、ゲート両側面及び窒化膜サイドウォール２８下に
も十分高融点金属膜３０が堆積されるようにする。(3) Next, as shown in FIG. 1C, the nitride film 27 is etched by anisotropic etching to
A sidewall 28 having a width of about 500Å is formed. After that, source / drain forming impurities are implanted into silicon using the sidewalls 28 as a mask to form source / drain layers 29. (4) Next, as shown in FIG. 1D, the oxide film 26 deposited in the step (2) [see FIG. 1B] is removed by etching with a hydrofluoric acid-based etchant, and a nitride film is further formed. The oxide film under the side wall 28 and also in the portion sandwiched by the polycrystalline silicon film 24 forming the gate electrode is 100
Etch away about 0Å. Subsequently, a refractory metal film 30 made of Ti or the like is sputtered on the entire surface by
Deposit about 400Å. In this case, the refractory metal film 30 is sufficiently deposited also on both side surfaces of the gate and under the nitride film sidewalls 28 by, for example, sputtering of 875 MHz × 2 times having a high ECR resonance frequency.
【００１８】（５）次に、図１（ｅ）に示すように、ア
ニールにより、高融点金属膜３０、Ｐ型シリコン基板２
１及び多結晶シリコン膜２４の接触した部分でシリサイ
ド化を起こさせ、高融点金属シリサイド３１とする。更
に、酸化膜２６上及び窒化膜２７上の未反応高融点金属
をエッチングにより選択的に除去する。その後、高融点
金属シリサイド３１の低抵抗化アニールを行なう。(5) Next, as shown in FIG. 1E, the refractory metal film 30 and the P-type silicon substrate 2 are annealed.
The silicidation is caused in the contact portion between the 1 and the polycrystalline silicon film 24 to form the refractory metal silicide 31. Further, the unreacted refractory metal on the oxide film 26 and the nitride film 27 is selectively removed by etching. After that, the high melting point metal silicide 31 is annealed to reduce its resistance.
【００１９】（６）次に、図１（ｆ）に示すように、通
常の方法に従い、中間膜３２を堆積し、配線とのコンタ
クトホール３３を開け、そこに配線層３４をパターニン
グする。図３は本発明の第２の実施例を示すサリサイド
型ＭＯＳＦＥＴの製造工程断面図である。(6) Next, as shown in FIG. 1 (f), an intermediate film 32 is deposited, a contact hole 33 for a wiring is opened, and a wiring layer 34 is patterned therein in accordance with a usual method. FIG. 3 is a cross-sectional view of a salicide type MOSFET manufacturing process showing a second embodiment of the present invention.
【００２０】（１）まず、図３（ａ）に示すように、図
１（ａ）と同様、ゲートパターニングまで完了する。つ
まり、Ｐ型シリコン基板４１上にフィールド酸化膜４２
（約４０００Å）を通常のＬＯＣＯＳ法で形成する。そ
の後、ゲート酸化膜４３（約１００Å）を形成し、更
に、ＬＰＣＶＤにより、ゲート電極となる多結晶シリコ
ン膜４４を約３０００Å堆積する。通常のホトリソエッ
チングにより、ゲート電極のパターン形成を行なう。４
５はＬＤＤ層である。(1) First, as shown in FIG. 3A, gate patterning is completed as in FIG. 1A. That is, the field oxide film 42 is formed on the P-type silicon substrate 41.
(About 4000 Å) is formed by a normal LOCOS method. After that, a gate oxide film 43 (about 100 Å) is formed, and further, a polycrystalline silicon film 44 to be a gate electrode is deposited by about 3000 Å by LPCVD. The gate electrode pattern is formed by ordinary photolithographic etching. Four
Reference numeral 5 is an LDD layer.
【００２１】（２）次に、図３（ｂ）に示すように、全
面にＬＰＣＶＤにより、酸化膜４６を１０００Å程度堆
積する。この場合、成膜条件として、温度を下げる等に
より粗な膜として、後の工程（３）〔図１（ｃ）参照〕
における酸化膜異方性エッチング時にフィールド酸化膜
４２より十分速くエッチングが進む膜質とする。 （３）次いで、図３（ｃ）に示すように、異方性エッチ
ングによりその酸化膜４６をエッチングし、さらにゲー
トの両側面に酸化膜４７が１０００Å程度出るまでエッ
チングを進める。(2) Next, as shown in FIG. 3B, an oxide film 46 is deposited on the entire surface by LPCVD to a thickness of about 1000Å. In this case, as a film forming condition, a rough film is formed by lowering the temperature, and the subsequent step (3) [see FIG. 1 (c)].
The film quality is such that the etching progresses sufficiently faster than the field oxide film 42 during the anisotropic etching of the oxide film. (3) Next, as shown in FIG. 3C, the oxide film 46 is etched by anisotropic etching, and the etching is further advanced until the oxide film 47 is exposed to about 1000 Å on both side surfaces of the gate.
【００２２】（４）次いで、図３（ｄ）に示すように、
全面に高融点金属４８を堆積する。この場合、第１の実
施例と同様、ゲートの両側面に十分高融点金属４８が堆
積するスパッタリング技術を使用する。 （５）次に、図３（ｅ）に示すように、図１（ｅ）と同
様に、シリサイド化反応、未反応高融点金属除去、低抵
抗化アニールを行なう。すなわち、このアニールによ
り、高融点金属膜４８、Ｐ型シリコン基板４１及びゲー
ト電極である多結晶シリコン膜４４と接触した部分でシ
リサイド化を起こさせ、高融点金属シリサイド４９とす
る。(4) Next, as shown in FIG.
A refractory metal 48 is deposited on the entire surface. In this case, as in the first embodiment, a sputtering technique is used in which the refractory metal 48 is sufficiently deposited on both side surfaces of the gate. (5) Next, as shown in FIG. 3E, silicidation reaction, unreacted refractory metal removal, and low resistance annealing are performed as in FIG. 1E. That is, by this annealing, silicidation is caused in the portion in contact with the refractory metal film 48, the P-type silicon substrate 41 and the polycrystalline silicon film 44 which is the gate electrode, and the refractory metal silicide 49 is obtained.
【００２３】以下は、図１（ｆ）の工程に従う。なお、
前記高融点金属の堆積は、共鳴周波数（高い周波数を用
いる）、ＥＣＲスパッタリング技術などのステップカバ
レージの良いスパッタリング技術で行なうことが望まし
い。また、本発明は上記実施例に限定されるものではな
く、本発明の趣旨に基づいて種々の変形が可能であり、
これらを本発明の範囲から排除するものではない。The following follows the process of FIG. 1 (f). In addition,
The deposition of the refractory metal is preferably performed by a sputtering technique having good step coverage such as a resonance frequency (using a high frequency) or an ECR sputtering technique. Further, the present invention is not limited to the above embodiments, various modifications are possible based on the gist of the present invention,
They are not excluded from the scope of the present invention.
【００２４】[0024]
【発明の効果】以上、詳細に説明したように、本発明に
よれば、高集積化に伴いゲート寸法が縮小化される場合
でも、ゲート電極両側面の少なくとも一部がシリサイド
化されるため、ゲート電極の低抵抗化を図ることができ
る。更に、窒化膜サイドウォール下も一部シリサイド化
することができ、サイドウォール下の寄生抵抗を低減す
ることができる。しかも、窒化膜サイドウォール下は、
スパッタリング時の回り込みにより、高融点金属を堆積
しているため、奥に行くほど、つまりゲート電極側に近
づくほど、高融点金属は薄くなり、ソース・ドレインの
接合深さ、及び不純物濃度もゲート電極側に近づくほど
浅くなるため、接合リーク電流を低減できる。As described above in detail, according to the present invention, at least a part of both side surfaces of the gate electrode is silicidized even when the gate size is reduced due to high integration. It is possible to reduce the resistance of the gate electrode. Further, a part of the portion under the side wall of the nitride film can be silicidized, and the parasitic resistance under the side wall can be reduced. Moreover, under the nitride film side wall,
Since the refractory metal is deposited due to the wraparound during sputtering, the refractory metal becomes thinner as it goes deeper, that is, closer to the gate electrode side, and the source / drain junction depth and impurity concentration are Since it becomes shallower as it gets closer to the side, the junction leakage current can be reduced.
【００２５】また、窒化膜サイドウォールとゲート電極
の間、及び窒化膜サイドウォールとシリコン基板の間を
１０００Å程度エッチングする間に、ゲート電極表面、
ソース・ドレインとなるシリコン基板表面の酸化膜を確
実にエッチング除去できるため、安定したシリサイド形
成が可能となる。更に、第３図における製造方法におい
ては、簡単な工程でもって、ゲート電極両側面の少なく
とも一部がシリサイド化されるため、ゲート電極の低抵
抗化を図ることができる。The surface of the gate electrode, while etching about 1000Å between the side wall of the nitride film and the gate electrode and between the side wall of the nitride film and the silicon substrate,
Since the oxide film on the surface of the silicon substrate to be the source / drain can be reliably removed by etching, stable silicide formation is possible. Further, in the manufacturing method shown in FIG. 3, at least a part of both side surfaces of the gate electrode is silicided by a simple process, so that the resistance of the gate electrode can be reduced.
【図１】本発明の第１の実施例を示すサリサイド型ＭＯ
ＳＦＥＴの製造工程断面図である。FIG. 1 is a salicide type MO showing a first embodiment of the present invention.
It is a manufacturing-process sectional drawing of SFET.
【図２】従来のサリサイド型ＭＯＳＦＥＴの製造工程断
面図である。FIG. 2 is a sectional view of a conventional salicide-type MOSFET manufacturing process.
【図３】本発明の第２の実施例を示すサリサイド型ＭＯ
ＳＦＥＴの製造工程断面図である。FIG. 3 is a salicide type MO showing a second embodiment of the present invention.
It is a manufacturing-process sectional drawing of SFET.
２１，４１ Ｐ型シリコン基板 ２２，４２ フィールド酸化膜 ２３，４３ ゲート酸化膜 ２４，４４ 多結晶シリコン膜（ゲート電極） ２５，４５ ＬＤＤ層 ２６，４６，４７ 酸化膜 ２７ 窒化膜 ２８ サイドウォール ２９ ソース・ドレイン層 ３０，４８ 高融点金属膜 ３１，４９ 高融点金属シリサイド ３２ 中間膜 ３３ コンタクトホール ３４ 配線層 21, 41 P-type silicon substrate 22, 42 Field oxide film 23, 43 Gate oxide film 24, 44 Polycrystalline silicon film (gate electrode) 25, 45 LDD layer 26, 46, 47 Oxide film 27 Nitride film 28 Sidewall 29 Source -Drain layer 30,48 Refractory metal film 31,49 Refractory metal silicide 32 Intermediate film 33 Contact hole 34 Wiring layer
Claims (4)
形成される高融点金属シリサイドを具備することを特徴
とするサリサイド型ＭＯＳＦＥＴ。1. A salicide-type MOSFET comprising a refractory metal silicide formed on at least a part of both side surfaces of a gate electrode.
の下方の少なくとも一部に形成される高融点金属シリサ
イドを具備することを特徴とする請求項１記載のサリサ
イド型ＭＯＳＦＥＴ。2. The salicide type MOSFET according to claim 1, further comprising a refractory metal silicide formed on at least a part of a side wall insulating film of the gate electrode.
堆積する工程と、 （ｂ）全面に窒化膜を堆積し、異方性エッチングにより
窒化膜サイドウォールを形成する工程と、 （ｃ）前記酸化膜を前記ゲート電極の両側面が一部露出
し、窒化膜サイドウォール下のシリコン基板が一部露出
するようにエッチングする工程と、 （ｄ）全面に高融点金属を堆積する工程と、 （ｅ）シリサイド化反応を行い、未反応高融点金属を除
去する工程とを施すことを特徴とするサリサイド型ＭＯ
ＳＦＥＴの製造方法。3. A step of: (a) depositing an oxide film on the entire surface after forming the gate electrode; and (b) depositing a nitride film on the entire surface and forming a nitride film sidewall by anisotropic etching. c) a step of etching the oxide film so that both side surfaces of the gate electrode are partially exposed and a silicon substrate under the nitride film side wall is partially exposed; and (d) a step of depositing a refractory metal on the entire surface. And (e) a step of performing a silicidation reaction to remove unreacted refractory metal.
Manufacturing method of SFET.
堆積する工程と、 （ｂ）異方性エッチングによりゲート電極両側面の一部
分が露出するまでエッチングを行う工程と、 （ｃ）全面に高融点金属を堆積する工程と、 （ｄ）シリサイド化反応を行い、未反応高融点金属を除
去する工程とを施すことを特徴とするサリサイド型ＭＯ
ＳＦＥＴの製造方法。4. A step of: (a) depositing an insulating film on the entire surface after forming the gate electrode; (b) performing anisotropic etching until a part of both side surfaces of the gate electrode is exposed; (c) A salicide type MO characterized by performing a step of depositing a refractory metal on the entire surface and a step of (d) performing a silicidation reaction to remove unreacted refractory metal.
Manufacturing method of SFET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21058493A JPH0766406A (en) | 1993-08-25 | 1993-08-25 | Self-aligned silicide mosfet and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21058493A JPH0766406A (en) | 1993-08-25 | 1993-08-25 | Self-aligned silicide mosfet and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0766406A true JPH0766406A (en) | 1995-03-10 |
Family
ID=16591742
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21058493A Pending JPH0766406A (en) | 1993-08-25 | 1993-08-25 | Self-aligned silicide mosfet and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0766406A (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07201775A (en) * | 1993-12-30 | 1995-08-04 | Nec Corp | Manufacture of semiconductor device |
| JPH11150271A (en) * | 1997-08-28 | 1999-06-02 | Lsi Logic Corp | Method of forming metal silicate contact and structure having metal silicate contact |
| KR20000043603A (en) * | 1998-12-29 | 2000-07-15 | 윤종용 | Mos transistor having metal silicide layer and fabrication method thereof |
| WO2001011669A1 (en) * | 1999-08-09 | 2001-02-15 | Koninklijke Philips Electronics N.V. | Salicide process for mosfet integrated circuit |
| KR100412194B1 (en) * | 2001-12-20 | 2003-12-24 | 주식회사 하이닉스반도체 | Method of manufacturing a semiconductor device |
| US6724057B2 (en) | 1999-12-14 | 2004-04-20 | Sanyo Electric Co., Ltd. | Semiconductor device with reduced short circuiting between gate electrode and source/drain region |
| US6979634B2 (en) | 2002-11-20 | 2005-12-27 | Oki Electric Industry Co., Ltd. | Manufacturing method for semiconductor device having a T-type gate electrode |
| JP2007518274A (en) * | 2004-01-12 | 2007-07-05 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Low stress sidewall spacers in integrated circuit technology. |
| JP2010010215A (en) * | 2008-06-24 | 2010-01-14 | Oki Semiconductor Co Ltd | Method of manufacturing semiconductor device |
| JP2010093446A (en) * | 2008-10-06 | 2010-04-22 | Serukurosu:Kk | Electromagnetic wave interface device and electromagnetic wave transmission system |
| JP2012218242A (en) * | 2011-04-06 | 2012-11-12 | Seiko Epson Corp | Method for manufacturing liquid ejecting head |
| JP2014195091A (en) * | 1998-11-13 | 2014-10-09 | Intel Corp | Method and device for improving salicide resistance on polycrystal silicon gate |
-
1993
- 1993-08-25 JP JP21058493A patent/JPH0766406A/en active Pending
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07201775A (en) * | 1993-12-30 | 1995-08-04 | Nec Corp | Manufacture of semiconductor device |
| JPH11150271A (en) * | 1997-08-28 | 1999-06-02 | Lsi Logic Corp | Method of forming metal silicate contact and structure having metal silicate contact |
| JP2014195091A (en) * | 1998-11-13 | 2014-10-09 | Intel Corp | Method and device for improving salicide resistance on polycrystal silicon gate |
| KR20000043603A (en) * | 1998-12-29 | 2000-07-15 | 윤종용 | Mos transistor having metal silicide layer and fabrication method thereof |
| WO2001011669A1 (en) * | 1999-08-09 | 2001-02-15 | Koninklijke Philips Electronics N.V. | Salicide process for mosfet integrated circuit |
| FR2797522A1 (en) * | 1999-08-09 | 2001-02-16 | St Microelectronics Sa | METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT HAVING IMPROVED SILICIURATION AND CORRESPONDING INTEGRATED CIRCUIT |
| US6724057B2 (en) | 1999-12-14 | 2004-04-20 | Sanyo Electric Co., Ltd. | Semiconductor device with reduced short circuiting between gate electrode and source/drain region |
| KR100412194B1 (en) * | 2001-12-20 | 2003-12-24 | 주식회사 하이닉스반도체 | Method of manufacturing a semiconductor device |
| US6979634B2 (en) | 2002-11-20 | 2005-12-27 | Oki Electric Industry Co., Ltd. | Manufacturing method for semiconductor device having a T-type gate electrode |
| US7247549B2 (en) | 2002-11-20 | 2007-07-24 | Oki Electric Industry Co., Ltd. | Manufacturing method for semiconductor device having a T type gate electrode |
| JP2007518274A (en) * | 2004-01-12 | 2007-07-05 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Low stress sidewall spacers in integrated circuit technology. |
| JP2010010215A (en) * | 2008-06-24 | 2010-01-14 | Oki Semiconductor Co Ltd | Method of manufacturing semiconductor device |
| JP2010093446A (en) * | 2008-10-06 | 2010-04-22 | Serukurosu:Kk | Electromagnetic wave interface device and electromagnetic wave transmission system |
| JP2012218242A (en) * | 2011-04-06 | 2012-11-12 | Seiko Epson Corp | Method for manufacturing liquid ejecting head |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6399451B1 (en) | Semiconductor device having gate spacer containing conductive layer and manufacturing method therefor | |
| US6190976B1 (en) | Fabrication method of semiconductor device using selective epitaxial growth | |
| JPH10173177A (en) | Manufacture of mis transistor | |
| JPH10178172A (en) | Semiconductor device and its manufacture | |
| US6245626B1 (en) | Method of fabricating a MOS device using a sacrificial layer and spacer | |
| JPH0766406A (en) | Self-aligned silicide mosfet and its manufacture | |
| KR100305308B1 (en) | Semiconductor device and method of manufacturing the same | |
| US6218690B1 (en) | Transistor having reverse self-aligned structure | |
| JP4411677B2 (en) | Manufacturing method of semiconductor device | |
| JPH10150188A (en) | Manufacture of semiconductor device | |
| KR100327422B1 (en) | Method of fabricating for semiconductor device | |
| US6255206B1 (en) | Method of forming gate electrode with titanium polycide structure | |
| US6995434B2 (en) | Semiconductor device and method of fabricating the same | |
| US7078347B2 (en) | Method for forming MOS transistors with improved sidewall structures | |
| JP3439652B2 (en) | Semiconductor device and manufacturing method thereof | |
| US6238958B1 (en) | Method for forming a transistor with reduced source/drain series resistance | |
| US20050170596A1 (en) | Semiconductor device and method for manufacturing the same | |
| JP2819918B2 (en) | Method for manufacturing semiconductor integrated circuit device | |
| JPH1098012A (en) | Manufacture of semiconductor device | |
| KR100451756B1 (en) | Method for fabricating semiconductor device the same | |
| KR100525446B1 (en) | Method for forming salicide layer of semiconductor device | |
| KR100348310B1 (en) | method for manufacturing of semiconductor device | |
| KR100380981B1 (en) | Method for forming salicide gate electrode | |
| JPH10125915A (en) | Semiconductor device and its manufacture | |
| KR20030079275A (en) | Method for forming salicide of a semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20010626 |