JPH076583A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce power consumption of a substrate generation circuit by switching between the operation with large current supply capability and the operation with small current supply capability by a charge pump circuit and reducing the current supply capability of the substrate generation circuit at the stand-by time of a DRAM. CONSTITUTION:When the interruption service, etc., of an external power source occurs, a voltage VINT is lowered from the voltage VEXT to VBT gradually. For instance, when the voltage becomes lower than VBC1, the fact that an operation condition becomes from a normal state to an information preservation state is informed by a circuit 100. By the circuit 2, the operation is switched to the information preservation state, and minimum power consumption required for the preservation of information is reduced. At this time, the voltage VINT is stopped at the time of arriving at the voltage VBT, and thereafter, the information preservation operation is performed by the voltage. Then, when the voltage VINT is raised and becomes higher than the voltage VBC2 by either the restoration of interruption service or the throw-in of the external power source, signals such as PHIBC, -PHIBC, etc., are restored to the normal operation condition. Thus, the circuit 2 is made to be the original normal state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvement of a semiconductor device, and more particularly to a semiconductor device suitable for battery backup operation.

[0002]

2. Description of the Related Art In a semiconductor device having a so-called information storage function represented by a memory, in an electronic device using this as a component, the above-mentioned information storage is performed in a so-called power failure state at the time of a failure of a power supply device for driving the semiconductor device. It is generally desired that the information stored in the functional unit does not disappear. For this purpose, in order to satisfy both the electrical characteristics of the normal operating state and the information retention characteristics during a power failure,
A so-called battery backup system is adopted in which a battery is provided in the electronic device and operating power is supplied by the battery during the power failure.

In the battery backup method described above, since the operation duration of the battery is extended, the semiconductor device consumes power in the information holding state (hereinafter simply referred to as the information holding state). It needs to be as small as possible. The low power consumption characteristic of this information holding state is not only in the case of the battery backup method at the time of the above power failure, but when it is necessary to stably store only information for a long period of time, or in a small electronic device that is easy to carry, It is also extremely convenient when carrying the apparatus while storing only necessary information with low power consumption and performing various processes based on the stored information at any place.

[0004]

The semiconductor device according to the prior art is not suitable for use in the battery backup method described above. In other words, almost no measures have been taken to reduce the power consumption during operation by this method, and even if there were any, it was insufficient.

Therefore, the object of the present invention is to have the same electric performance as the conventional one in the normal operation, and the power consumption becomes extremely small in the operation of simply holding the information such as the battery backup operation. It is to provide a semiconductor device.

[0006]

In the semiconductor device according to the present invention, a change in a physical quantity such as an external power supply voltage is detected by a detector provided in the semiconductor device, that is, in an LSI chip, or by an instruction from the outside. Recognizing that the information has been held, the power consumption is reduced to the minimum required to hold the information. More specifically, in the above information holding state, the power supply to the circuit unit that is not necessary for holding information is stopped.

Further, in the information holding state, it is not necessary to satisfy the performance required in the normal operating state such as the operating speed, so that the power consumption of the circuit necessary for holding the information is simply held. Limit the power consumption to the minimum required to satisfy only the function.

[0008]

In the above-mentioned information holding state, the power consumption of the entire semiconductor chip can be reduced by stopping the power supply to the circuit portion which is not necessary to hold the information.

Even in the circuit necessary for holding information, the power consumption of the entire LSI chip can be reduced by limiting the power consumption to the minimum power consumption required to satisfy only the function of holding information. .

[0010]

EXAMPLES The details of the present invention will be described below with reference to examples.

FIG. 1A shows an embodiment for explaining the basic concept of the present invention. In the figure, reference numeral 1 denotes an LSI chip, which generally indicates an LSI chip having an information storage function, such as dynamic or static random access memory (RAM) or read-only memory (ROM),
Furthermore, a logic LSI such as a microcomputer
Any type of LSI chip, such as Also,
The constituent element may be a bipolar transistor, a MOS transistor, a combination of these elements, or a GaAs transistor using a material other than Si. 2 shows a circuit part. _{Reference numeral} 3 indicates a power supply wiring, and V _INT indicates its voltage. Here, the external power supply voltage V _EXT is applied to 3. That is, V _INT = V _EXT . Here, for the sake of simplicity, the number of power sources is one, but a plurality of types of power sources may be applied from the outside. This also applies to the following examples. Reference numeral 4 is a signal input / output wiring. In the figure, 5 is a battery and V _BT is its voltage. In the information holding state, the entire chip operates using this battery as a power source. Reference numeral 6 is a diode for preventing reverse flow of 3 to 5 currents during normal operation. Here, in order to simplify the explanation, it is assumed that 6 is an ideal diode having a forward voltage of 0 V, a forward impedance of 0Ω, and a reverse impedance of ∞Ω (infinity). It should be noted that these exemplify a method of connecting an external power source and a battery in the battery backup method, and a method of providing a power failure detecting means in an electronic device and automatically connecting 3 and 5 by this is also conceivable. In the following examples, connection of these batteries is not shown for simplicity.

Reference numeral 100 is an operating state detecting means for detecting the transition from the normal operating state to the information holding state, and outputs the result to 101 as a signal "1" or "0". Although the detection means is provided inside the LSI chip here, an input terminal as shown by a broken line 7 in the figure is provided and the detection result by the power failure detection means of the electronic device described above is input as a signal. Good. This also applies to each embodiment described below.

Now, 100 detects the change of the voltage or current of 3 and recognizes that the normal operation state is changed to the information holding state. In each of the embodiments, the method of detecting a voltage change will be mainly described below. However, not only the current change but also another physical quantity change caused by the characteristics of the LSI chip, such as temperature, humidity, volume, light quantity, speed, acceleration, etc. May be detected. Further, it may be a means for detecting not the change in the physical quantity of the LSI chip itself but the operation state of the electronic device or the LSI chip affecting the operation of another device and the resulting change in the physical quantity. The velocities and accelerations mentioned above are generally examples. In any case, since each physical quantity is once converted into an electric quantity, the method for detecting a voltage change described below can be applied to any case.

The case where 100 detects a voltage change of 3 will be described below as an example.

100 is generally 3 if V _BT <V _EXT.
Voltage becomes low, when V _BT > V _EXT , the voltage at 3 becomes high, and when V _BT to V _EXT , noise (such as glitch noise) generated at 3 due to a power failure of the external power supply. And outputs a signal to 101. However, in order to reduce the power consumption in the information holding state which is the object of the present invention, it is desirable that V _EXT > V _BT .
In this case, the operation of the present embodiment will be described with reference to FIG. In this embodiment, it is not always necessary to satisfy the condition of V _EXT > V _BT , and this also applies to other embodiments described later.

As shown in FIG. 1B, for example, if a power failure of the external power source (power failure due to power source failure, power failure when the power source is intentionally turned off, etc.) occurs, a voltage of 3 V _INT
Gradually drops from V _EXT to the voltage of V _BT . This voltage is a predetermined constant reference voltage, for example, V
Becomes lower than the _BC1 (time t _1), the state detecting means 100
Outputs φ _BC (changes from “0” to “1”), φ _BC
Detects signals such as ￣ (change from “1” to “0”). In other words, 100 recognizes that the operating state has changed from the normal state to the information holding state. In response to the signal of 101, the circuit unit 2 switches the operation to the information holding state and reduces the power consumption to the minimum required to hold the information. Three
The voltage V _INT of V decreases from time t ₁ to t ₂ ,
_At the voltage of _BT, the diode 6 (assuming that the forward voltage is 0 V as described above) is turned on, that is, power is supplied from 5, and the decrease of the voltage V _INT of 3 is stopped at V _BT , and then this voltage is lowered. The information holding operation is continued with. On the other hand, when the voltage V _{INT of} 3 rises and becomes higher than the constant reference voltage V _BC2 due to the restoration of the power failure or the turning on of the external power source, φ _BC , φ
Restore signals such as _BC ￣ as in the original normal operating state. As a result, the circuit section 2 is returned to the original normal operation state.

According to the embodiment described above, it is possible to detect a change in the operating state and reduce the power consumption in the information holding operating state to the minimum amount necessary for the information holding operation. It is possible to lengthen the operation continuation time by the battery when carrying the portable battery device.

In this embodiment, the method of internally detecting the change of the operating state has been described, but as described above, the method of instructing the change of the state from the outside by a signal or the like can also obtain the same effect. To be Further, the state change may be detected by detecting a physical quantity other than the voltage change, such as a current change, as described above. In the voltage change detection, the detection reference voltage V _BC is set to V _BC1 and V _BC2 when the voltage drops and rises. However, this varies variously for the convenience of design, and in some cases V _BC = V _BC1 = V _BC2 May be Further, it is preferable that these values are set in consideration of the voltage fluctuations that can normally occur in V _EXT and V _BT . For example, V _EXT
When the central value of V is 5V, the fluctuation is ± 0.5V, the central value of V _BT is 3V, and the fluctuation is ± 0.3V, V _BC1 , V _BC2
By setting the value of V _BC such as 3.3 V <V _BC <4.5 V, there is no problem of erroneously detecting a change in V _EXT and V _BT that may occur as a change in operating state. be able to.

FIG. 2 shows another more specific embodiment. The same numbers as those in FIG. 1 indicate the same contents.
In FIG. 1, the circuit portion 2 is divided into 2a and 2b in FIG.
2a is a circuit section that is not related to information retention in an information retention state such as during a power failure, and 2b is a circuit section related to information retention. Specifically, for example, an L such as a microcomputer in which a logic circuit and a memory circuit are mixed.
The SI chip corresponds to the logic circuit 2a and the memory circuit corresponds to the 2b. Further, in this case, it goes without saying that a circuit that generates a signal or the like necessary for the operation of the memory circuit, which is not a direct memory circuit, is included in 2b.

Also in the present embodiment, the change in the operating state is detected by 100 and the result is output to 101 as in FIG. By this signal, the operation of the circuit section 2a which is not particularly related to information retention is stopped, and the power consumption is reduced. Power is supplied to the information retention 2b to retain information.

According to the present embodiment, the operation of the circuit section unrelated to information retention is stopped, so that the power consumption can be greatly reduced.

Incidentally, 2a and 2b in this embodiment are, as described above, in the information holding state at the time of power failure or the like.
Each of them refers to a circuit unit not related to information retention and a related circuit, and is not limited to the logic circuit (2a) and the memory circuit (2b) given as specific examples. For example, even in the same memory circuit, a memory portion which does not need to store the information especially at the time of power failure may be included in the portion 2a. Specific examples of such LSI chips, for example, as in the large computer memory system, BS (B uffer S torage) operating at high speed, is a low-speed large-capacity MS (M ain S torage) Like 2
It has various types (or more types) of memory and mainly stores information in the MS, but reads a small amount of information from the MS to a high-speed BS as necessary to increase the operating speed during normal operation. An LSI chip or the like that can be operated in such a manner can be given. In this case, BS may be 2a and MS may be 2. Generally, a high-speed memory such as BS is composed of a bipolar static memory, and a large-capacity memory such as MS is composed of a MOS dynamic memory. Its constituent elements and circuit system are as described above. Various other selections are possible. For example, both 2a and 2b are bipolar type and MOS type transistors,
A memory of each type such as a static type memory or a dynamic type memory in which a transistor of a GaAs type material other than Si is used as a constituent element can be arbitrarily selected.

FIG. 3 shows another more specific embodiment of the present invention, in which the same numbers as those in FIG. 2 indicate the same contents. In the figure, the circuit portion 2b is different in that it is divided into 2b1 and 2b2.

In FIG. 2, 2b1 is related to the operation of holding information in the information holding operation state such as at the time of power failure, but designed to have large power consumption for high performance in normal operation (for example, high speed operation). (The delay time and power consumption product have a substantially constant relationship, as is well known). That is, it is a circuit unit that has excessive performance and therefore consumes a large amount of power only for the information holding operation. 2b2
It is a circuit portion excluding 2b1 of b.

In the present embodiment, in the information holding operation state, the signal of the output 101 described in the embodiment of FIG. 2 stops the operation of the portion 2a unnecessary for the information holding operation to reduce the power consumption and at the same time the information holding. The circuit portion 2b1 having an excessive performance only for the operation is made to have a performance required for the information holding operation to reduce the power consumption of this circuit portion.

According to this embodiment, in addition to the embodiment described in FIG. 2, it is possible to further reduce the power consumption. In this embodiment, the power consumption is reduced by stopping the operation of 2a and
Although two low power consumptions are implemented by trade-off with the performance of b1, it is needless to say that the same effect can be obtained by implementing each independently.

FIG. 4 shows a structure in which a power supply voltage converting means 200 is provided in an LSI chip in addition to the embodiment shown in FIG.
2b3 operates on its output 201. 2b1 ', 2b2
′ Indicates a circuit portion obtained by removing the portion 2b3 from 2b1, 2b2 in FIG.

In the information holding state, the voltage converting means 200 outputs a voltage which is stepped down or stepped up from the operating voltage of the circuit section 2a other than 2b3. Here, the output voltage of 200 in the normal operation state is generally equal to the voltage of 3, but even in the normal operation state, the voltage itself is equal to that of Japanese Patent Application No.
It may be a value obtained by converting the voltage of 3 for other purposes as described in Japanese Patent Application No. 6-57143, Japanese Patent Application No. 56-168698 and the like.

Now, in the information holding state, the purpose of reducing the voltage is to lower the operating power supply voltage of 2b3, for example, to be lower than the power supply voltage V _BT (battery voltage) in the information holding state to achieve low power consumption. Is. That is,
This is also a concrete implementation of the method for reducing the power consumption of 2b1 in FIG. In addition, the purpose of boosting the voltage is, for example, when the operating voltage is too low with the power supply voltage V _BT in the information holding state and the circuit performance deteriorates and the operation becomes unstable, the voltage is boosted to operate. This is to stabilize the.

As described above, in the information holding state,
By operating a part of the circuit in the LSI chip at a voltage that is stepped down or stepped up compared to other circuits, low power consumption and stable operation can be achieved. In the present embodiment, the case of converting the power supply voltage has been described for the sake of simplicity, but in some cases, the amplitude voltage of the pulse signal or the like may be the conversion target.

The basic concept of the present invention has been described above with reference to FIGS. It is needless to say that the contents described in these embodiments can be implemented individually or in any combination, and the effects described in each embodiment can be directly obtained. Furthermore, in each of the embodiments, the operation state detecting means 100 has been described as an example of detecting two states of the normal operation state and the information holding state. However, more detailed operation state detection, for example, a plurality of V _BT values are prepared. It is also possible to detect a fine change in V _INT and generate a plurality of φ _BC in response to the change, thereby controlling a finer circuit. Alternatively, it is possible to operate by arbitrarily combining φ _BC generated in this way and the respective embodiments described in FIGS. 1 to 4. That is, phi _BC 4, generates the φ _BC1 ~φ _BC4, φ _BC1
It is also possible to control the operation of 2a, 2b1 'by φ _BC2 , 2b2' by V _BC3 , and 2b3 by φ _BC4 .

Further, in each of the embodiments, each circuit portion such as 100, 200, 2a, 2b ... Is shown clearly separated for simplification of description, but in general, each circuit is an LSI.
It goes without saying that they are intermingled with each other in terms of spatial arrangement in the chip, circuit connection, and so on.

Hereinafter, more specific examples of the above-mentioned examples will be described.

FIG. 5 shows a concrete example of the operating state detecting means 100. Here, an example in which a change in voltage is detected to detect a change in operating state will be described.

In the figure, reference numeral 110 discriminates whether the potential relationship between the inputs 111 and 112 is high or low, and if the 111 is higher, the output 1
13 is a discrimination circuit that outputs a low potential (information “0”) and a high potential (information “1”) when 111 is lower, which is a so-called Schmitt trigger circuit or a comparator circuit. Although there are various concrete construction methods of these circuits, generally, a differential amplifier, or I / E / E / Transaction on Circuits & Systems Vol. CAS-25, No.7, July 1
978, pp. 482-489 (IEEE Transact
ion on Circuits and Systems, Vol. CAS-25, N
O.7, July 1978, pp. 482-489).
Can be used.

120 is input to 121, for example, V
_This is a circuit for converting the _INT voltage into a value V _INT ′ suitable for the input of 110, and V _INT ′ = V _INT may be set in some cases. 130 is the reference voltage V _BC (V _BC1 ,
This is a circuit for generating V _BC2 ). 115 inverts the signal phi _BC 113, an inverter circuit that outputs phi _BC to 114.

According to this embodiment, when V _INT ′> V _BC , 113 is low potential (information “0”), 114 is high potential (information “1”), and when V _INT ′ <V _BC . , 113,
It is possible to output the signals opposite to the above to 114, respectively, so that it is possible to detect that the operating state has changed. Since the relationship between V _INT and V _INT ′ is previously determined by 120, the above detection can be performed with a fixed relationship between V _INT and V _BC .

According to the present embodiment, the detection level can be finely changed by changing the characteristics of 120 and 130, and the versatility and the design flexibility can be increased. Further, in this embodiment, the reference voltage V _BC is set to 1
Although the method of generating at 30 and inputting to the discrimination circuit 110 has been described, 110 itself has a certain reference threshold value, and this value is compared with the voltage of the input, and depending on the result, "1" or "0" is obtained. It may be a so-called threshold circuit that outputs ". In such a case, 120 V
_A desired characteristic can be obtained by converting _INT to an arbitrary V _INT ′ and inputting it. One of the concrete examples will be described later with reference to FIG.

FIG. 6 shows a voltage V of 3 as described in FIG.
_{This is} a specific embodiment in the case where the detection reference voltage when _INT drops and when _INT rises is different from V _BC1 and V _BC2 .

As shown in the figure, in this embodiment, the reference voltage generating circuit section is provided with a function of generating binary V _BC1 and V _BC2 , and these are switched to V _{BC by} switching the switches S131 and S132. Output and apply to 112. S131, S
132 is switched here by φ _BC (in some cases, φ _BC
When φ _BC is “0”, that is, in the normal operation state, S131 is turned on, S132 is turned off, V _BC = V _BC1, and φ _BC is “1”. At that time, that is, when S131 is turned off and S132 is turned on in the information holding state and V _BC = V _BC2 , as shown in FIG. 1, V _BC1 becomes the reference voltage when V _INT decreases and V _BC2 becomes the reference when V _INT increases. Become a voltage.

According to this embodiment, the reference voltage when V _INT drops and when V _INT rises can be independently designed to any value.

FIG. 7 shows a concrete example in which a plurality of values of V _BC are prepared and a plurality of φ _BC corresponding thereto are generated as described above.

In the figure, V _{BC1 to} V _BCn are reference voltages.
The output V _INT ′ of 120 is input to 111 as in FIG. 5, but there may be a case where V _INT ′ = V _INT .

In this embodiment, every time V _INT ′ becomes lower than V _{BC1 to} V _BCn , the corresponding φ _BC1 to φ _BCn become the information “1”. When V _INT 'conversely becomes higher than _{V BC1 ~V BCn, φ BC1 ~φ} BCn respectively become data "0". In this embodiment, the inverter 114 is not shown for simplification, but by adding 114 as before, φ
Inverted signal phi _BC in _BC also easily obtained. This also applies to the following examples.

[0045] According to this embodiment, phi _BC1 to [phi] can be easily output a number of reference values phi _BC1 to [phi] _BCn corresponding to the _BCn, by using this, detecting an operation state change of the LSI chip in more detail Therefore, the operation can be finely controlled.

Next, an embodiment relating to the circuit for generating the reference voltage V _BC will be described. An ordinary stabilized power supply circuit can be used as such a reference voltage generation circuit, but a circuit system that is easy to incorporate in an LSI chip is preferable.
An example of such a circuit is, for example, Japanese Patent Application No. 56-16869.
It is presented in No. 8.

FIG. 8 shows an example in which one of them is used to _form a circuit for generating a plurality of reference voltages φ _{BC1 to} φ BCn. In the figure, Q _{131 to} Q _13n are MOS transistors, and have threshold voltages of V _{T131 to} T _T13n , respectively. R ₁₃₃ is a resistance, which is set sufficiently higher than the equivalent on-resistance of Q _{131 to} Q _13n . V _P is a power supply voltage, and V _P > (V
_T131 + V _T132 + ... is set as T _13n). Therefore, if V _INT satisfies this condition, V _P = V _INT may be set. If V _INT cannot be satisfied, Japanese Patent Application No. 57-22
A voltage satisfying the above conditions may be generated by the method shown in FIG. 29 of No. 0083 and used as V _P.

According to this embodiment, the respective outputs 131 to 13n are

[0049]

[Equation 1]

The respective values of can be obtained.

According to this embodiment, an arbitrary V is selected by selecting the number of stages of MOS transistors or the threshold voltage.
It is possible to obtain the value of _BC . In addition, only the number of steps, V
_When adjusting the value of _BC , the threshold voltage is the minimum amount of change, so generally only discrete values can be obtained, but if you want to make continuous adjustments, control the threshold voltage itself. Besides, an embodiment as shown in FIG. 9 can be considered.

That is, as shown in FIG. 9, for example, V _BCn obtained in FIG. 8 may be divided by the resistances of R ₁₃₁ ′ to R _13n ′. By appropriately selecting R ₁₃₁ ′ to R _13n ′, it is possible to obtain continuous arbitrary values of φ _BC1 ′ to φ _BCn ′. Here, the resistance value of R _{131'~R 13n} 'is better to set greater than R ₁₃₁ is desirable in that it can reduce the influence of change of V _P.

Although an example in which a circuit is constituted by MOS transistors and resistors has been described above, the elements to be used are not limited to these. For example, instead of MOS transistors, bipolar type transistors or ordinary diodes, Further, any element having a non-linear rectifying characteristic such as a Zener diode can be used. As the resistance, any impedance element can be used, and it is also possible to use an on-resistance such as a MOS transistor.

FIG. 10 shows one specific example of the circuit 120 for converting V _INT into V _INT ′ in FIG. 5 and outputting it.

As shown in the figure, in this embodiment, V _INT ′
Is obtained by resistance-dividing V _INT with R ₁₂₃ and R ₁₂₂ . Further, V _BC is n in the embodiment described in FIG.
= 1 and the value of V _BC is approximately equal to the threshold voltage V _T131 of Q ₁₃₁ .

In this embodiment, 110 is V
_INT '= R ₁₂₂ / R ₁₂₃ + R ₁₂₁ · V _INT and V _BC to V
Compare the relative voltage of _T131. If the former is high, φ _BC =
When “0” and the former are low, φ _BC = “1” is output, respectively. The relation is re-arranged as follows with respect to the relationship between V _INT and V _T131 . Ie

[0057]

[Equation 2]

In the case of, φ _BC = “0”

[0059]

[Equation 3]

In the case of, φ _BC = “0”.

These are equivalent to the value of V _BC being (1 + R ₁₂₁ / R ₁₂₂ ) V _T131 in FIG. 1B.
Therefore, by choosing R ₁₂₁ and R ₁₂₂ appropriately,
The reference voltage can be easily set to any value.

[0062] Figure 11 generates a plurality of V _INT 'by the conversion circuit 120 of the V _INT, whereby an embodiment for generating a plurality of phi _BC as in FIG 7.

As shown in the figure, 120 is a resistor R ₁₂₀ ′.
˜R _12n ′. The input voltage of 121, here V _INT, is resistively divided by these resistors,
It is output as V _INT ′ to V _INn ′. These and V _BC 1
By inputting 10 inputs, φ _{BC1 to} φ _BCn can be obtained as in FIG. 7.

Therefore, also in this embodiment, the change in the operating state of the LSI chip can be detected in more detail and the operation can be controlled more finely, as in FIG. The resistors R ₁₂₀ ′ to R _12n ′ in this embodiment can be replaced by any element as long as it is an impedance element. For example, the on resistance of a MOS transistor may be used.

FIG. 12 shows still another specific example of the operating state detecting circuit 100, and uses the circuit DCV shown in FIG. 16 of Japanese Patent Application No. 57-22083 as a basic constituent circuit. .

In the figure, Q _{141 to} Q _14n and Q ₁₅₁ are MOS transistors having thresholds V _{T141 to} V _T14n and V _T151 , respectively. Here, Q _{141 to} Q _14n constitute the V _INT conversion circuit 120 in FIG. 5, and V _INT ′ = V
_INT - to output _{(V T141 + V T141 + ...} V T14n).
Although Q ₁₅₁ and R ₁₅₁ compose the discrimination circuit 110 of FIG. 5, they have a certain reference threshold value as described above, and discriminate whether the input voltage is high or low. It is a threshold circuit. Threshold value V of this circuit
_TC is Sadamari by the ratio of the ON resistance of the threshold voltage V _T151 and R ₁₅₁ and Q ₁₅₁ of the V _T151, can be arbitrarily set, if the value of R ₁₅₁ sufficiently larger than the on resistance of Q _151,
It is possible to make V _TC = V _T151 . Here, for simplicity, this case will be described.

The operation of this embodiment will be described with reference to FIG.

V _INT gradually decreases, and the voltage of 150 becomes V _INT ′ = V _INT − (V _T141 + V _T142 + ... V _T14n ) <
V _T151, that is, V _INT < V _T151 + (V _T141 + V _T142 + ...
When V _T14n ) = φ _BC (time t ₁ ) Q ₁₅₁ is turned off, and the output φ _BC changes from “0” to “1”. As a result, it is possible to detect the voltage change of V _INT and detect that the operation has shifted to the information holding state, as in the above-described embodiment.

Also in this embodiment, by adjusting the threshold voltage and the number of stages of the MOS transistor to be used, the equivalent value of V _BC in FIG. 9B can be arbitrarily set. Further, according to this embodiment, V _INT < V _T151 + (V _T141 +
Under V _T142 + ... V _T14n ), Q ₁₅₁ is turned off, which is extremely effective for reducing power consumption in the information holding state, which is the object of the present invention.

In the figure, R ₁₅₀ is a discharge resistor for preventing electric charge from being accumulated in a node such as 150 when V _INT changes from a high state to a low state. This resistance value needs to be selected according to the changing speed of V _INT , but when the changing speed is slow, it is also possible to substitute it by a parasitic resistance generated between the node 150 and the Si substrate. In that case, R ₁₅₁ is unnecessary. Where R ₁₅₀ , R
The ON resistance of the MOS transistor can be substituted for ₁₅₁ .

Various modifications can be made in the above-described embodiment as well as other embodiments. For example, Q _{141 to} Q _14n can be used as long as they can obtain a constant voltage shift, and a bipolar transistor, an FET transistor, a diode, a zener diode or the like can be used instead. Also, Q
₁₅₁ can be used as long as it is an active element having a certain threshold value, and can be replaced by a bipolar transistor, an FET transistor, or the like. Furthermore, it is also possible to use any combination of the above-described embodiments. For example, the resistance divider circuit described in FIG. 10 may be used to generate V _INT ′, or conversely, 120 in FIG. 10 may be replaced with a circuit such as Q _{141 to} Q _{14n in} this embodiment. .

FIG. 13 shows an embodiment in which the resistors R ₁₅₀ and R ₁₅₁ of FIG. 12 are replaced by Q ₁₅₂ and Q ₁₅₃ , respectively.

V _G2 and V _G3 are gate bias voltages for Q ₁₅₂ and Q ₁₅₃ , and may be connected to the drains as the case may be to set V _G2 = V _INT ′ and V _G3 = V _INT . However, V
_{When G3} = V _INT , the voltage on the high potential side of φ _BC (“1”) changes from V _INT to the threshold voltage V of Q _153.
Note that it is only _T153 lower. Therefore, if it is desired to make this voltage equal to V _INT , V _G3 > V _INT + V
Must be set like _T153 .

In this embodiment as well, the same operation and effect as in FIG. 12 can be obtained, but with V _G2 = V _INT ′, Q ₁₅₂
If the threshold voltage V _{T152 is set} to V _T152 to V _T151 , V
_{In the} information holding operation state in which _INT '< _{VT 151} , Q ₁₅₂ is also turned off, so that the power consumption in this state can be further reduced as compared with the case of FIG.

FIG. 14 shows an embodiment in which a plurality of φ _BC are generated based on the embodiment of FIG. 12 as in FIGS. 7 and 11.

In the figure, Q _{161 to} Q _16n are Q ₁₅₁ and R in FIG.
The same discrimination circuit as ₁₅₁ is constructed. R _{141 to} R ₁₅₀ are resistors for discharging electric charges.

Also in this embodiment, the same operation and effect as those in FIGS. 7 and 11, or FIGS. 12 and 13 can be obtained.

In the above, the specific examples of the operation state detecting means 100 of FIGS. 1 to 4 have been described in the examples of FIGS. Next, a concrete example of reducing the power consumption in the information holding operation state by the output signal of 100 will be described.
A dynamic memory of the OS and an address multiplex type memory will be described as an example. The scope of application of the present invention is not limited to this, and the following embodiments can be applied to various types of LSI chips as described above.

FIG. 15 shows an embodiment in which the present invention is applied to an address multiplex type MOS dynamic memory.

As is well known in the MOS dynamic memory, since the information charges accumulated in the storage capacity in the memory cell disappear with the passage of time, it is necessary to perform the rewriting operation at a constant cycle. . This is a so-called refresh operation, and this operation is necessary even in the information holding operation state of the present invention. The address multiplex method is, for example, in a memory in which memory cells are two-dimensionally arranged in rows and columns, row designation addresses and column designation addresses are multiplexed on the same signal line at different time zones and input from the outside. However, this is a method for reducing the number of input / output pins of the entire LSI. For details of these, see Japanese Patent Application No. 56-28.
No. 109 and the like.

In FIG. 15, 1 is a memory LSI chip,
3 is a power supply wiring, and V _INT indicates its voltage.
3 is applied with V _EXT or V _BT for battery backup from the outside. 4 is a ground wire, which is generally V _SS (0
V) is applied externally. Reference numeral 100 is a circuit that detects the voltage change of 3 to detect the operating state of the memory LSI chip, and the various embodiments described above can be applied. 300
Is a substrate voltage generation circuit built in the memory LSI chip. This substrate voltage is applied in order to improve the operating performance (operating speed, etc.) of the memory LSI, but it may be applied externally or may be used as it is as the ground potential as it is in some cases. In this case, 300 is unnecessary. Reference numeral 700 denotes a memory array section in which memory cells are arranged in a two-dimensional array of rows and columns, and an arbitrary row selection 80i and column selection decoder 900 selected by the row selection decoder 800.
The memory cell designated by the intersection of the arbitrary column selection line 90i selected by the read / write circuit 43
0, the data input buffer circuit 440, the data output buffer circuit 450 and the like are used to exchange signals with external D _in and D _out . Reference numeral 400 is a circuit that generates an internal clock signal required for a write operation in response to a write control signal WE from the outside. Reference numeral 410 is a circuit that mainly generates an internal clock signal related to the above-described column selection operation in response to the column selection control signal CAS. A circuit 420 compares the phases of CAS and the row selection control signal RAS to generate a refreshing signal φ _f described later. During normal operation, RAS is input prior to CAS (all signals change from "1" to "0"). Therefore, when CAS is input prior to RAS, refresh operation is generally performed. _Judge and generate φ _r0 . Reference numeral 500 is a circuit for generating an internal clock signal mainly related to the row selection operation by the RAS. Generally, in an address multiplex type memory, a row selection line (generally word line) 801
-80n sequentially (any order), address buffer 46
A refresh operation is performed by selecting an output signal of 0 and a row selection decoder to operate. Therefore, it suffices to mainly operate only 500 circuits during the refresh operation.

Reference numerals 600, 610 and 620 respectively denote a refresh control circuit, a refresh timer which generates a signal φ _f at a constant time t _{f in} accordance with an instruction from 600, and an address counter.
atic Refresh, Self Refresh
Perform each refresh operation in h).

In the auto refresh, the refresh operation is activated according to an external instruction, but the refresh address is an operation mode automatically generated by the internal address counter. On the other hand, the self-refresh is automatically performed in the memory LSI chip for both the activation of the refresh operation and the generation of the refresh address. These operations are controlled by the refresh signal REF from the outside or the output φ _r0 of 420 described above.

That is, in the auto refresh, REF
(Generally changes from high voltage to low voltage) or whenever φ _r0 is input, φ _r is generated to operate 500 necessary for the refresh operation, and at the same time, internal address counter 620 automatically refreshes internally. Address A
i ′ is generated, and instead of the external address signal Ai, 46
0 is input and 801 to 80n are sequentially selected according to Ai 'to perform a refresh operation. In the self-refresh, in addition to the internal generation of the refresh address described above, the refresh operation is automatically started internally by the signal φ _f generated by the refresh timer at every constant time t _f . Instructions from the outside of auto-refresh and self-refresh are generally distinguished by the duration of a state in which the REF signal is present (generally a low voltage state), and the self-refresh operation is performed when the duration exceeds a certain time. . These details are described in Electronic Technology, Vol. 23, No. 3, etc.

In the memory having the above-described structure, according to the present invention, as described in the embodiment of FIG. 1, the voltage change 3 is detected by 100, and the change in the operating state is detected. As a result, when it is detected that the information holding operation is started due to a power failure of the external power source, for example, 60
Circuits such as 0, 610 and 620 are activated to prevent the information in the memory cell from being erased by the same operation as the self refresh operation described above. At this time, in the present invention, the minimum necessary power is supplied only to the circuits necessary for the information holding operation, and the power supply to the other circuits is stopped, as described above. Therefore, 400, 410, 430, 44, which are largely unrelated to the refresh operation
As a general rule, circuits such as 0, 450, 900 stop operating.

Further, the power consumption of the circuit required for the information holding operation is reduced as much as possible. That is, as described above, the performance of each circuit is set according to the performance required during normal operation, so that the performance is too high for the information holding operation only. It is overkill. This performance is reduced to the minimum required for the information holding operation. For example, the circuit of 500 sets the operating speed to a speed suitable for the information holding operation to reduce the power consumption. Further, the operation of the substrate voltage generating circuit is stopped to set the substrate potential to the ground potential (0V), or the starting ability is reduced to reduce the power consumption. Further, as described in Japanese Patent Application No. 58-99341, the number of refresh operations is reduced as compared with the normal operation to reduce power consumption. For example, in the 64K-bit dynamic memory described in Electronic Technology, Vol. 23, No. 3, the refresh time t _ref
2ms, refresh cycle N _ref 128 cycles is the general specification, but this is 12ms in 2ms.
This means that eight refresh operations are required. Therefore, it is necessary to generate the signal φ _t from the refresh timer 610 at an average rate of once per t _f = t _ref / N _ref ˜15 μs to perform the refresh operation. It has been experimentally found that the value of t _f needs to be reduced as the internal temperature Tj of the LSI chip rises, and that t _f needs to be reduced by about one digit when Tj changes by 30 ° C. The above specifications are determined in consideration of the worst condition in a normal operation state. That is, the ambient temperature T at which the LSI chip is used
a is the highest (generally 70 ° C), the power consumption P of the LSI chip
d is the maximum condition. If Tj at this time is Ta = 70 ° C. and Pb = 300 mW, for example,

[0087]

[Equation 4]

[0088] In this case, θ _ja is the thermal resistance of the LSI chip package, in the conventional ceramic-type package θ _ja
It is a ~ 100 ℃ / W about.

As described above, Tj to 100 ° C. under the worst conditions.
The above t _f is determined based on this value.

Now, in the information holding state of the present invention, the purpose is to reduce the power consumption, and in this state, it is possible to make Pd < 1 mW. Therefore, even if the value of Tj is the external power source, If Ta fails
Even if the temperature is as high as 70 ° C., Tj is about 30 ° C. lower than that in the normal operating state, and therefore t _f can be increased by about an order of magnitude, as is apparent from the equation (4). That is,
The number of refresh operations per unit time can be reduced by about one digit. In the information holding operation state,
Generally, the entire electronic device using the LSI chip is also in an inoperative state, and therefore Ta can be considered to be 70 ° C. or lower. Therefore, the value of t _f may be further increased. In the present invention, by utilizing the above, φ generated from the refresh timer in the information holding state
than in normal operation the time interval t _f of _f, and about one order of magnitude or more long, to reduce the number of refresh operations, reduce power consumption. Further, in the present invention, in the information holding operation state, a part of the operating voltage of the memory array unit 700 is made higher than that of other circuits to stabilize the operation.

In this embodiment, the method of detecting the change in the operating state by the voltage change of 3 has been described. However, a method of instructing from the outside as described above is also possible, for example, refresh. As mentioned in the explanation of the operation,
A method of generating φ _r0 by the phase difference between RAS and CAS or a method of inputting a REF signal can be used instead. That is, the self-refresh instruction in the conventional technique is used as the instruction for changing the operating state in the present invention. Further, here, φ is determined by the phase difference between RAS and CAS.
_The method of generating _r0 and the method of inputting the REF signal are
Since the functions are almost the same, it is generally sufficient to provide either method. For example, the state change is detected at 100, and φ _r0 is generated by the phase difference between RAS and CAS,
A configuration in which the conventional auto refresh operation is instructed and the input of REF is eliminated is also possible. At this time, a self-refresh function may be provided, but it may be omitted because the information holding operation state of the present invention substantially corresponds to the self-refresh operation.

According to this embodiment described above, the power consumption in the information holding operation state can be greatly reduced.

Specific examples of each part of this embodiment will be described in detail below with reference to other embodiments. In the following embodiments, description will be made assuming an N-channel MOS transistor as a memory constituent element, but other P-channel MOS transistors,
Alternatively, it can be applied to the case where both P and N channel types, further bipolar type transistors, and a combination of MOS type and bipolar type are used as constituent elements.

FIG. 16 shows an embodiment of the reduction of power consumption, and the description has been made by taking the reduction of power consumption of the circuit 500 of FIG. 15 as an example.

Generally, the circuit of 500 is, as shown in FIG.
It is composed of cascade connections of a plurality of dynamic pulse generation circuits such as PG1 to PG3. This pulse generation circuit P
An example of the circuit configuration and operation of G is described in the National Conference No. 69, Semiconductor and Materials Division, Institute of Electronics and Communication Engineers, 1979. V _{INT1 to} V _INT3 represent the power supply voltage of each PG and are generally connected to the common power supply voltage V _INT in the chip.

In the present invention, as described above, the operation speed is too fast for only the information holding operation.
Reduce the power consumption by making the speed appropriate for this operation state (slow). That is, in a general circuit, the fact that the product of the signal delay time t _Pd of the circuit and the power consumption Pd is substantially constant is used. For this reason, in this embodiment, the power supply voltage of the circuit whose power consumption is desired to be reduced, for example, the power supply voltage V _{INT2 of} PG2 is made lower than the power supply voltage of the other circuits to reduce the power consumption. As another means, in the information holding state,
For example, the circuit constant of PG2 is internally switched to increase t _Pd and decrease Pd. Further, as another means, as shown by a broken line in the figure, a PG 2 ′ with low power consumption is prepared, and SW 502, SW are set in the information holding operation state.
The switches 502 ', SW503, and SW503' are used to switch the circuit to be operated from PG2 to PG2 'to reduce power consumption.

The embodiment described above makes it possible to reduce the power consumption of the circuit 500. The application range of the present embodiment is not limited to 500, and can be applied to other similar circuits.

Generally, most of the circuits shown in FIG. 16 are dynamic circuits. Therefore, input 5
A signal is input to 01 or 602, and power is consumed only when the circuit operates. However, only the circuit of PG1 is a signal from the outside RAS
However, it is always in a standby state in which power is consumed so that it can immediately respond and operate even if input is made at any time.
That is, PG1 is a static type circuit, but in the information holding state of the present invention, the number of refreshes per unit time is about 1/10 or less as compared with the normal operating state as described above. Therefore, it is particularly important to reduce the power consumption of PG1. Next, this specific example will be described.

FIG. 17 shows an embodiment for reducing the power consumption of PG1 in FIG.

The figure shows the circuit configuration of the input first stage section of PG1. In the figure, SW511, SW515, and SW51
2 and SW 516 are designed to operate in conjunction with each other depending on the operating state. In the normal operating state, the former is
The latter is turned on in the information holding state. Therefore, in the normal operation state, the NAND circuit having R ₅₁₁ as a load resistance, RAS ￣ ￣, and φ _r as inputs is
In the information holding operation state, an inverter circuit having φ _r as an input is constructed. That is, in the normal operation state, either the external input RAS ￣ ￣ or the output φ _r of the refresh control circuit in FIG. 15 changes from the high voltage (“1”) to the low voltage (“0”). At this time, the output φ _RO becomes a high voltage, and the operation after PG1 is started. Therefore, in this state, in the same manner as described above, in addition to the normal memory operation, the automatic and self refresh operations are possible. On the other hand, in the information holding operation state, when φ _r becomes a low voltage, the output φ _RO becomes a high voltage, the operation after PG1 is started, and the refresh operation described above is performed. In this state, the RAS input is disconnected by the SW515, so even if the memory drive circuit is stopped due to a failure of the external power supply or the like, the voltage of the RAS signal becomes unstable. , Not affected by it.
This circuit system can be effectively used in other circuits such as 400, 410, and 600 to which a signal is directly input from the outside.

[0102] Now, in the present embodiment, each power Pd ₀ in the normal operation, power consumption Pd ₁ during information holding ^{_{operation, Pd 0 αV INT 2 / R}} 511, Pd 1 αV INT 2 / R 512 Becomes Therefore, by setting R ₅₁₁ <R ₅₁₂ , the power consumption during the information holding operation can be reduced. Note that the signal delay time of the circuit increases by that amount (almost proportional to the load resistance), but there is no particular problem because the information holding operation does not require high-speed operation.

As described above, according to this embodiment, the power consumption can be reduced. Further, even when the voltage of the external input signal becomes unstable at the time of power failure of the external power supply, its influence can be prevented. In the present embodiment, the PG1 is taken as an example, but other circuits, for example, P in FIG.
The present embodiment can be applied to the low power consumption of G2 to PG3 as it is. That is, the load resistance of each circuit may be switched by a switch as in the present embodiment. Further, here, each load resistance is, for example, M
It is also possible to replace it with an active element such as an OS transistor and use its ON resistance. When an active element is used in this way, it can function as both a switch and a resistor, and instead of switching between two resistors with different resistance values, the ON resistance value can be changed by changing the operating conditions of the active element. It is also possible to control Further, in the present embodiment, the number of cases in which switching is possible is two, but the number in cases of switching can be further increased.

FIG. 18A shows another embodiment capable of further reducing power consumption as compared with FIG. 17, and FIG. 18B shows its timing signal waveform. In the previous embodiment, the power consumption was reduced by switching the load resistance. In addition to this, in the present embodiment, the current that constantly flows from the power supply to the ground is set to almost zero, and the power consumption is significantly reduced.

In FIG. 18A, Q ₅₁₇ and Q ₅₂₀ are obtained by _replacing the load resistances R ₅₁₁ and R ₅₁₂ of FIG. 17 with MOS transistors, respectively, and the on-resistance of Q ₅₂₀ is generally higher than that of Q _517. Keep it big. C ₅₁₇ and C ₅₂₀ are capacitors for positively feeding back the potential rise of the node 513 to the nodes ₅₁₇ and ₅₂₀ to speed up the rising speed of φ _r0 , and form a so-called bootstrap circuit. Q ₅₁₈ and Q ₅₂₁ are nodes 517-519 and ₅₂ during pre-charge and bootstrap operation of C ₅₁₇ and C _520.
This is a MOS transistor for electrically disconnecting between 0 and 522 to improve the positive feedback efficiency by bootstrap. Details of these operations are described in Japanese Examined Patent Publication No. 56-49021, in which the gate voltages V _G of Q ₅₁₈ and Q _{521 in} FIG. 18 correspond to the respective input voltages φ _{BC −} and φ _rp “. If the voltage is set higher than the voltage (high voltage) in the 1 "state by the threshold voltage of the MOS transistor, the most efficient operation is possible, and the method of generating the voltage is also described.

In the present embodiment, in the normal operation state, since φ _{BC —} is a high voltage (“1”), Q ₅₁₅ ,
Both Q ₅₁₇ are turned on and operate similarly to FIG. On the other hand, in the information holding state, since φ _BC is a high voltage (“1”), Q ₅₁₆ is turned on. At this time, the gate of Q ₅₂₀ is precharged and turned on by φ _rp , which becomes a high potential immediately before φ _r becomes a low voltage, and the current I _DC starts flowing from V _INT toward the ground. Then when φ _r becomes low voltage,
Q ₅₀₂ turns off and φ _R0 goes high. Therefore, in this embodiment, I _DC flows only for a short period of time Δt, so that a large reduction in power can be achieved. This is the data retention state phi _r is an internal refresh timer (FIG. 15
610) output φ _f , so that a signal such as φ _rp can be generated in advance prior to φ _r .

Now, it is assumed that the refresh operation cycle t _f (equal to the generation cycle of φ _r ) in the information holding operation state can be increased to about 150 μs as described in FIG.
Further, assuming Δt to be 10 ns, the time for which I _DC flows can be reduced to about 1/10 ⁴ or less in FIG. 17, and in addition to the low power consumption by load switching in FIG. 17, a significant reduction in power consumption is possible.

In the present embodiment, φ _BC is input to the node 522 instead of φ _rp , and the load resistance of FIG.
It is also possible to adopt a configuration in which the S transistor is replaced as it is. In this embodiment, Q is the same as in FIG.
_Although the example in which the ON resistance of ₅₂₀ is made larger than Q ₅₁₇ has been described, even if the ON resistances of both are made equal, as described above, the power consumption can be reduced to 1/10 ⁴ or less of the conventional one. Further, here, φ _r also occurs during normal operation auto or self refresh. Therefore,
When φ _rp is always generated in synchronization with φ _r , Q ₅₂₀ is turned on even during normal operation, but if the ON resistance of Q ₅₂₀ is set to be larger than that of Q ₅₁₇ , power consumption during normal operation increases. Such problems can be reduced. If φ _rp is generated only when φ _BC is at a high voltage, even if Q ₅₂₀
Even if the ON resistances of Q ₅₁₇ and Q ₅₁₇ are made equal, problems such as increased power consumption can be completely solved. Also, Q ₅₁₇ and Q ₅₂₀ , Q ₅₁₈ and Q ₅₂₁ are commonly used, and OR of φ _BC ￣ and φ _rp
It is also possible to input a (logical sum) signal as a precharge signal.

FIG. 19 shows one specific example for reducing the power consumption of the substrate voltage generating circuit 300 described with reference to FIG.

In general, the substrate voltage generating circuit is described in the 1976 ISC SDC Digest of Technical Papers pp. 138-139 (197).
6 ISSCC DIGEST of TECHNICAL
As described in PAPERS, pp138-139), etc., a voltage having a polarity opposite to the power supply voltage is generated by the principle of charge pump.

In the figure, reference numeral 311 is an oscillation circuit composed of a ring oscillator circuit or the like, which generates a charge pump signal φ _BB . C _BB is a charge pump capacitance Q _BB1 is a direct current regeneration MOS transistor, and Q _BB2 is a rectifying MOS transistor.
I _BB is a schematic representation of the substrate current generated in the entire circuit in the LSI chip, and generally the current drive capability I _out of the substrate voltage generation circuit must be I _out > I _BB . Details of these operations are described in the above document.

Now, in the information holding state in the present invention,
Most of the LSI chips have stopped operating,
The substrate current of the LSI chip becomes extremely small, and even if the current drive capacity I _out of the substrate voltage generation circuit is reduced, the LSI
There is no hindrance to the operation of the entire chip. Since this I _out and the power consumption Pd _BB of the substrate voltage generation circuit are in a substantially proportional relationship,
This I _out can be reduced to reduce Pd _BB .

I _out is generally expressed by the following equation.

[0113]

[Equation 5]

Here, Vφ _BB is the voltage amplitude of φ _BB , and f _BB is the frequency of φ _BB .

Therefore, in this embodiment, the value of Vφ _BB is made small and Pd _BB is made small in the information holding state. There are various methods of reducing the value of Vφ _BB , but for example, the operating voltage V _{INTB of the} circuit may be lowered (generally, V _INTB = V _INT in the normal operating state). As a means for lowering this V _INTB , for example, Japanese Patent Application No. 56-168698
It is sufficient to generate a voltage lower than the operating voltage V _{INT of the} entire LSI chip by the circuit described in Japanese Patent Application No. 57-22083 and to switch between V _INT and the low voltage depending on the operating state. Further, f _BB may be reduced in order to further reduce Pd _BB . for that purpose,
For example, the method of lowering the operating voltage described above may be used, or the time constant of the circuit that determines f _BB in 311 may be controlled by the method shown in FIGS. Also, or if 311 is composed of a ring oscillator cascaded inverters to a plurality ring shape, FIG. 17, by switching the load resistance of the inverter as shown in FIG. 18, the delay time of f _BB (inverter Pd _BB may be controlled. Moreover, as a method of further reducing Pd _BB , a plurality of C _BB are prepared,
This may be switched depending on the operating state and used.

As described above, the reduction of the power consumption of the substrate voltage generating circuit has been described. However, in some cases, the operation of the substrate voltage generating circuit is stopped in the information holding state, and V _BB = 0V is set to completely reduce the power consumption. It is also possible to do so. For that purpose, as shown in FIG. 19, Q _BB3 may be provided on the ground wire 311 (which may be on the power supply line side), and this may be turned off by φ _{BC −} to stop the power supply. At this time, the output 316 is Q
It is fixed to the ground potential (0V) with _BB4 . Thus V _BB =
If it is set to 0V, the diffusion layer capacitance Cj in the LSI chip becomes large (Cj is inversely proportional to the square root of the diffusion layer-substrate voltage), which causes a problem such as a slow operation speed.
As described above, in the information holding state, there is no problem because it is not necessary to operate at a particularly high speed. Further, when V _BB = 0V, there is a possibility that the information stored in the memory cell may be erased when noise of the opposite polarity to the power supply voltage is input from the outside via the input / output pins of the LSI chip. In such a case, a silicon substrate having a sufficiently small specific resistance is used as a silicon substrate for forming an LSI chip so that the substrate resistance can be reduced so that even if the noise is input, it can be immediately absorbed by the ground line. You can leave it. If the specific resistance is too small, there arises a problem in characteristics such as the threshold voltage of the MOS transistor formed there being too high. In such a case, the silicon of the specific resistance suitable for making the MOS transistor is generated. A layer was formed on the low resistivity silicon substrate. For example, an epi type silicon substrate may be used.

As described above, according to this embodiment, the power consumption of the substrate voltage generating circuit in the information holding state can be reduced.

FIG. 20 shows another embodiment for reducing the power consumption of the substrate voltage generating circuit.

In the present embodiment, as shown in the figure, a plurality of substrate voltage generating circuits 301 to 30n having different current supply capacities and therefore different power consumption are prepared. Figure 7 these operations, Figure 11, or the like 14, the inverted signal φ _BC1 ¯~φ _BCn ¯ signals of the generated phi _BC1 to [phi] _BCn, for example in response to changes in V _INT of FIG. 15, sequentially Control (control start / stop of operation). As a result, the current supply capacity can be optimized according to the change in the power supply voltage.

FIG. 21 shows still another embodiment for low power consumption of the substrate voltage generating circuit.

As shown in the figure, in the information holding state, as shown in FIG.
Similar to 9, the circuit operation of 311 is stopped by φ _BC , but φ _r generated during the refresh operation is used as a charge pump signal to generate V _BB . Here, it goes without saying that the period t _{f of} φ _r is generally in the relation of t _f > 1 / f _BB .

Therefore, this embodiment is also one specific example of the above-mentioned embodiments for lowering f _BB .

The outline of the operation is shown in FIG. When φ _BC ￣ is high voltage, that is, in normal operating state, φ _BB
V _BB is generated by the charge pump of. When φ _BC becomes a low voltage and enters the information holding state, the operation of 311 is stopped, and V _BB is generated by the charge pump of φ _r . At this time, the substrate voltage V _BB1 immediately after φ _r becomes a low voltage
The absolute value of is

[0124]

[Equation 6]

It becomes: Where Vφ _r is the voltage amplitude of φ _r ,
V _TBB1 ′ and V _TBB2 ′ are the threshold voltages of Q _BB1 ′ and Q _BB2 ′, respectively. For details of these, see Japanese Utility Model Application No. 54-8.
2150. After that, the substrate current of the entire LSI chip gradually approaches 0 V to V _BB2 . However, in the information holding state, most of the circuits stop operating, so that the substrate current is extremely small, and the above-mentioned decrease in V _BB is hardly a problem. As I _BB increases, the value of | V _BB1 | shown in equation (6) also decreases, but in this equation, I _BB is considered to be so small that it can be ignored. In addition, in the same figure (B), V _{BB in the} information holding state
Is shown to be lower than the normal operation state (absolute value) on the average, because it is assumed that the power supply voltage is low in the information holding state.

According to the embodiments described above, it is possible to significantly reduce the power consumption of the substrate voltage generating circuit and obtain a constant substrate voltage.

Since φ _r is generated during auto and self refresh in the normal operation state, therefore, the charge pump operation is performed even in that state. As I mentioned before, in the φ _BB period 1 / f _BB and φ _r of the period t _f of, 1
Since / f _BB <t _f , there is no particular problem, but if some trouble occurs, a signal that occurs only when φ _BC is a high voltage may be used as in the case of φ _{rp in} FIG.

FIG. 22 is one of the more preferable embodiments of FIG. 21, which makes it possible to make the substrate voltage in the information holding operation state higher (absolute value).

In FIG. 21, the absolute value of V _BB1 is calculated from V _{φ r as} V absolute value of V _TBB1 ′ and V _TBB2 ′ as shown in equation (6).
Will be lower by the sum of. In a diode-connected MOS transistor in which the drain and gate are connected, this is the drain-
This is because a forward voltage equal to the threshold voltage is generated between the sources. Accordingly, in this embodiment, by applying a 'substantially in phase of phi _r and phi _r to the gate of the' Q _BB1, and fully on the Q _BB1 ', the forward voltage of the equivalently 0
V. Therefore, according to this embodiment,

[0130]

[Equation 7]

Can be set to, for example, the power supply voltage V
_{When INT} becomes low during the battery backup operation (information holding state, of course), the operable lower limit voltage can be made lower than that in FIG.

[0132] Incidentally, when the phi _r in this embodiment is changed from a high voltage to a low voltage, i.e. at the time of generating a negative voltage by the charge pumps, Q _BB1 'completely so turned off phi _r' of It is necessary to set the phase. For that purpose, the low voltage may be applied at a time slightly earlier than φ _r ′ φ _p . Therefore, a signal such as the inverted signal of φ _rp in FIG. 18 may be used.

FIG. 23 is described in the embodiment of FIG.
This is a specific example for making the refresh synchronization t _f in the information holding state longer than the normal operation state.

The above t _f is determined by the refresh timer 610 shown in FIG. Therefore, to change t _f , 6
The time constant within 10 may be controlled. The time constant circuit generally has a configuration as shown in FIG. Here, the resistance and the capacitance may be replaced by active elements. The resistor may be an on-resistance such as a MOS transistor or a bipolar transistor,
The capacitance may be the gate capacitance of a MOS transistor (so-called inversion layer capacitance).

In the circuit of FIG. 23, in the information holding state, SW6
12 is turned off and SW618 is turned on. T _f in each state is the normal operating state t _f1 ∝τ ₁ = R ₆₁₃ · R ₆₁₄ · C ₆₁₃ / (R
₆₁₃ + R ₆₁₄ ) Information holding state t _f2 ∝τ ₂ = R ₆₁₃ · (C ₆₁₃ + C ₆₁₈ ) and set each constant value so that τ ₂ / τ ₁ is the desired ratio of t _f2 / t _f1. You can leave it.

That is, an arbitrary t _f can be obtained by this embodiment. The present embodiment can also be used as a means for controlling the oscillation frequency of the substrate voltage generating circuit described above.

FIG. 24 shows an embodiment in which the time constant circuit described with reference to FIG. 23 is composed of a capacitor type circuit for the switch.

In the circuit shown in the figure, SW616,
On the SW617 alternately, by the charge division of C ₆₁₆ and C ₆₁₃ are turned off, and transfers the 612 signal 613. The time constant τ _s of such a circuit is

[0139]

[Equation 8]

Is given by Here t _s is SW616,
This is the on / off cycle of SW617. The above details are I E E Transactions
On Circuits and Systems Vol. CAS
-25, No. 7, July 1978, pp. 490-4.
Page 97 (IEEE TRANSACTIONS ON
CIRCUITS AND SYSTEMS, VOL.
CAS-25, No.7, JULY 1978, pp49
0-pp497) and the like.

As is clear from the equation (7), also in the present embodiment, each operating state is controlled by using the SW618 or the like to control the capacitance value according to the operating state or change the value of t _s. It can be set of t _f arbitrarily.

FIG. 25 is a concrete example in which the embodiment of FIG. 4 is applied to the dynamic memory of FIG.

In the figure, MC is a memory cell and has a capacity CM.
Information charges are stored in. At this time, the CM terminal voltage V _M
The maximum value V _Mmax of V _W is approximately V _W −V, where V _W is the word line voltage and V _D and Q _M are the threshold voltages V _{TM of} the data lines.
It is determined by the lower voltage of _TM or V _D. V
_The larger _Mmax is, the larger the accumulated charge is. Therefore, V _W −V _T
> It is desirable that V _D is set. This is important when the power supply voltage V _INT becomes lower than the normal operation state in the information holding state according to the present invention. Therefore, this embodiment shows a specific example in which the word line voltage is increased during the information holding operation.

In FIG. 25, 210 is a voltage boosting circuit,
_BC is a high voltage, i.e. in the data retention state, phi _W voltage V _W of
Has a function of outputting the output at a higher level than during normal operation.

According to this embodiment, it is possible to stably hold information even when the power supply voltage becomes low, for example, in a battery backup operation. In the figure, φ _W0
Is the original signal of φ _W.

FIG. 26 shows one of the more specific examples of FIG.

In the figure, reference numeral 213 is a circuit which receives φ _in as an input and generates a drive signal φ _W of _W , and is composed of, for example, a dynamic pulse generation circuit as shown in FIG. Reference numeral 214 is a delay circuit having a delay time of τ _d .
216 is an AND circuit. C _WP is a word line parasitic capacitance, and C _WB is a word line voltage boosting capacitance.

Details of the operation will be described with reference to FIG.

When φ _in is input, φ _W is generated. The voltage V _W1 at this time is generally equal to V _INT . After that time τ _d , φ _Wd appears at 215. At this time, φ _BC is low voltage,
That is, in the normal operation state, the output of 216 remains a low voltage, and φ _W continues the voltage of V _W1 . On the other hand, when φ _BC is at a high voltage, that is, when the information is held, the AND circuit 216 operates and φ ′ _Wd is output. As a result, the voltage of φ _W rises due to the capacitive coupling of C _WB . _Ascent V _W2 at this time
Let V _{INT be} the voltage amplitude of φ ′ _Wd ,

[0150]

[Equation 9]

If, for example, C _WB = C _WP , V _W2 is boosted to about 1.5 times V _INT .

According to the above-described embodiment, the voltage during the information holding operation can be easily boosted.

Now, the delay circuit of 214 is a circuit for generating _φ'Wd because V _W1 of φ _W becomes almost equal to V _INT for the purpose of efficiently boosting. The delay time τ _d becomes important when there is a signal delay in the word line itself. Next, a preferred embodiment when the word line has a signal delay will be described.

FIG. 27 shows one of the preferred embodiments in FIG. 26 when the word line has a signal delay. That is, in the present embodiment, the signal delay itself of the word line is shown in FIG.
It is used instead of the delay circuit.

In the figure, 710 is a two-dimensional memory cell MC.
An array of memory cells arranged in ₁, D₁￣ ~ D_n, D_n
￣ is the data line, W₁~ W_nIs the word line, W₂₀₁, W₂₀₂Is
Pseudo word line having the same time constant as the word line, R_WIs
Word line resistance, C_WN, C_WEIs the parasitic capacitance of the word line.
For simplicity, they are shown in a centralized constant line format. S
A is a data line which becomes a pair by reading the memory cell.
Speaking of D₁, D₁A signal that differentially amplifies a small signal generated between
It is a sense amplifier. Note that normally this differential amplification
Each dummy data cell has a dummy memory cell for generating a reference signal.
It is added to the line, but is omitted here for simplicity.
In addition, in this embodiment, the pair of data lines are arranged in parallel.
A so-called folded bit line configuration method (folded b
It line) memory, but the
The data line is placed on both sides of the SA, so-called open
Of course applicable to the open bit line configuration method (open bit line)
It is possible. 800 is a decoder, here Q₈₁₁
~ Q₈₂₂The word line drive circuit of is also shown as part of the decoder.
is doing. 221 and 222 are word line signal detection circuits
Output a signal when the input reaches a certain voltage.
It That is, 221 is φ_W0Is the pseudo word line W₂₀₂By
Delay, resulting in a signal appearing at the farthest end (E).
When the voltage reaches a certain voltage, φ_W0Ascend
Φ for pressing_WdTo occur. 222 is for boosting
Signal φ ′_dWIs W₂₀₁By the same delay as above,
SA drive when the voltage at the far end (E) reaches a certain voltage
For φ_STo occur. Here, the signal delay of each pseudo word line is
The extension time is set equal to that of a normal word line as described above.
I have decided. Therefore, boosting is almost at the far end of the word line.
V mentioned earlier_W1When it reaches the level,
Drive SA when the result reaches the far end of the word line again.
It is supposed to do.

Details of the operation will be described below with reference to FIG.

When φ _in is input, φ _W0 is output. At this time, the MOS transistors in the decoder 800 are those corresponding to the selected word line, and Q ₈₀₁ and Q _822.
Is turned on. Therefore, a signal appears on the selected word line W _i (s) and W ₂₀₂ . At this time, at each near end (N), φ _W0
A signal appears at about the same time as, but at the far end (E),
It appears with a delay at the time when R _W , C _WN and C _WE are determined. When this signal reaches a constant voltage value, φ _Wd is generated at 221. Next, as in FIG. 26, when φ _BC is a high voltage (“1”), φ _Wd ′ is output. As a result, φ _W0 is boosted by C _WB , and its waveform appears at the near end (N) of W _i and W ₂₀₂ almost at the same time. On the other hand, the waveform of φ ′ _Wd also appears at the near end (N) of W ₂₀₁ almost at the same time. Each signal appears at the far end (E) after being delayed by the word line again. That is,
The waveform of the boosted portion of the word line and the delayed waveform of the waveform of φ _W ′ _d appear in (E) of W _i and W ₂₀₁ almost at the same time. φ _BC
Is high voltage, φ _S for SA drive is generated when (E) of W ₂₀₁ reaches a certain voltage. That is, SA is driven only when the far end of the word line is sufficiently boosted.
On the other hand, when φ _BC is a low voltage, the voltage is not boosted, so 222
Is the W ₂₀₂ (E) generates a phi _S with (almost the same time as the occurrence of _Wd phi mentioned previously) when it reaches a certain voltage.

According to the above-described embodiment, even if the signal delay time of the word line varies due to variations in the manufacturing process, it is possible to perform stable boosting consistent with it, and operate in the information holding state. The lower limit voltage can be made extremely low.

In the present embodiment, an example of a method of generating various signals by utilizing the signal delay of the word line has been described, but various modification methods are described in Japanese Patent Application No. 58-55012. The present embodiment can be applied to these modified examples as they are. Also, as for the method of increasing the pressure, various methods as described in JP-A-57-172587 can be used. For example, although the above-mentioned reference describes a method of boosting the word line twice, by applying this, the word line that has already been boosted even in the normal operation state is double-boosted in the information holding state and It is possible to further increase the voltage. Although the boosting of the word line is described here, the boosting of other circuits can be similarly performed. For example, in some cases, the data line voltage can be boosted by the method described in Japanese Utility Model Laid-Open No. 57-152698. Further, although the pulse voltage boosting is described here, it is also possible to boost the DC voltage. Further, although the present embodiment describes the dynamic memory as an example, it can be applied to various types of LSIs as described above.

FIG. 28 shows the above-described voltage boosting for CMOS
2 is an embodiment applied to a static memory of a fixed type.

In the figure, MC is a 1-bit memory cell,
Actually, a plurality of MCs are arranged two-dimensionally. D,
D-is a data line and W is a word line. The MOS transistor with P is a P-channel type, and the one with N is an N-channel type MOS transistor. Q
₂₃₁ , Q ₂₃₂ operate as a changeover switch between the power supply voltage V _INT and the power supply voltage Vu boosted inside. When φ _BC is a low voltage, that is, at a normal operating voltage, Q ₂₃₁ is turned on, and V ₂₃₁
Supply _INT to MC. When φ _{BC −} is at a low voltage, that is, in the information holding operation state, Q ₂₃₂ is turned on and Vu is supplied to MC.

In the flip-flop type memory cell shown in the figure, information is retained only by applying a voltage to MC, and it is necessary to periodically perform a refresh operation like the dynamic type memory described above. There is no. Therefore, in the information holding state of the present invention, it suffices to apply a voltage to MC, and in general, power supply to other circuit units may be stopped.

The memory cell retains information only by applying a voltage, but if the power supply voltage drops during battery backup operation, etc., the information may be affected by noise from the outside, for example, radiation (α particles, etc.). There is a risk of flipping. Therefore, in this embodiment, in the information holding operation state, the internally boosted Vu voltage is applied to MC. As a result, the above problems can be solved. Various methods of generating Vu can be considered, for example, Japanese Patent Application No. 57-2.
21 of 20083 or Japanese Patent Application No. 58-1057.
A circuit such as that shown in FIG. 16 of No. 10 may be used. At this time, the current supply capacity of Vu becomes a problem, but in the memory cell as shown in FIG. 28, since it is sufficient to supply only a current corresponding to the leak current of each node, there is almost no problem.

The specific implementation of the basic concept of the present invention described with reference to FIGS. 1 to 4 has been described above mainly using the dynamic memory as an example, but the scope of application of the present invention is not limited to this, and is described above. As described above, it can be applied to various types of LSIs.

Nowadays, due to the decrease in the element withstand voltage due to the miniaturization of the elements constituting the LSI, the operating voltage of the LSI must be lowered correspondingly. As a method of operating this with the same power supply voltage as the conventional one, a method of lowering an external power supply voltage in a chip and operating a fine element by the lowered voltage is disclosed in Japanese Patent Application No. 56-5714.
No. 3, 56-168678 and the like.

An embodiment in which the present invention is applied to the above LSI chip will be described below.

FIG. 29 shows the above-mentioned LS in which the LSI chip is provided with the voltage limiter 5 for dropping the external power supply voltage in the chip, and the circuit is operated by the lowered voltage VL.
It is an embodiment in which the present invention is applied to an I-chip.

[0168] As shown in the figure, in this embodiment controls 5 for example V _INT voltage phi _BC is generated by means 100 for detecting a change in the operating state by a change in or phi _BC ¯ by the information holding In this state, the value of VL is increased to, for example, V _INT or higher to stabilize the operation.

According to this embodiment, even in an LSI chip which is operated by internally lowering the voltage, it is possible to perform an operation such as battery backup, as in the above-mentioned embodiments. The specific configuration of the voltage limiter is described in Japanese Patent Application No. 58-105710 and the like, and the present invention is applicable to all of them. Some specific examples will be described below.

FIG. 30 is one of the more specific embodiments of FIG. 29. In the one-transistor type MOS dynamic memory circuit, the memory array circuit and its related circuits mainly operate at a lower voltage due to the externally applied power supply voltage. LS
The present invention is applied to an I chip.

In the figure, a circuit group 710 surrounded by a one-dot chain line is a memory array circuit, a circuit group 720 surrounded by a two-dot chain line is a sense amplifier for amplifying a signal from the memory cell described above,
Alternatively, a circuit such as a decoder, and a circuit group 730 surrounded by a three-dot chain line are circuits for giving an operation signal to each of the above circuit groups, amplifying a memory signal from the memory array circuit, and writing a memory signal to the memory array circuit. is there. Here, the data D and D, the word lines W _{1 to} W _n , the signal input / output lines I / O and I / O, and the sense amplifier drive signal φ _S are operated by lowering the external voltage. E, F, G,
H is a circuit mainly related to the operation of lowering these voltages. E is a circuit for generating a voltage serving as a reference for operation, which generates V _L2 ′ and V _L2 ″. F is a precharge signal φ _P2l for the data line with reference to V _L2 ″. G generates a drive signal φ _xl (corresponding to φ _W0 in FIG. 27) for the word line with reference to V _L2 ″. H has I / I with reference to V _L2 ′.
The precharge voltage V _CP of O and I / O is generated. In the figure, when the power supply voltage V _INT = 5V and the threshold voltage V _T of the MOS transistor V _T = 0.5V, the approximate voltage of each part is shown in parentheses. The above is Japanese Patent Application Sho 58
No. 105710, the details of the configuration and the operation of each circuit are described in the same specification.

[0172] Now, in the above configuration, in the present embodiment, φ _xl, φ _P2l ¯ to the booster circuit 210 ', 210 "
Are added, the voltage of φ _xl and φ _P2l ￣ is boosted in the information holding state by the output φ _BC or φ _BC of 100. In some cases, the output voltage of F, G, H is increased in the information holding state. Thereby, for example, the voltage of the data line I / O line is set to V _INT or higher. At this time,
In the information holding operation state, the circuit section unrelated to the operation stops the power supply as described above to reduce the power consumption.

As a result, during normal operation, the external power supply voltage operates at a lower voltage, while during information holding operation,
Contrary to the above, it is possible to realize an extremely stable memory LSI by increasing the operating voltage of at least part of the circuit above the external power supply voltage. Furthermore, the embodiment of the present invention described above can be applied to this embodiment as it is.

A more specific example will be described below.

FIG. 31 is one of the concrete examples of FIG. 30E.

In the figure, LM1 generates a reference voltage V _L. LM2 current-amplifies the above V _L to perform V _L2 ′, V _L2 ″
To occur. Here, when the threshold voltage of MOS transistors used for the _{V T V L2 '~ V L} + V T, V L2 "~
An example of V _L + 2V _T is shown. Details of the configuration and operation of these are described in Japanese Patent Application No. 58-105710.

FIG. 19B shows the schematic characteristics of V _L and V _INT . The characteristics shown in the figure are the result of being selected to be suitable for the reliability test of the LSI chip, and it is noted that the above-mentioned reference or Japanese Patent Application Nos. 56-168698 and 57-220.
No. 083 and the like.

Here, the value of V ₀ is Q _{11E to} Q _13E , Q _17E.
Is turned off, that is, the sum of the threshold voltages of the MOS transistors. If this relationship is generalized as in FIG. 12,

[0179]

[Equation 10]

Here, V _T17E is the threshold voltage of Q _17E , V _T17E
T1iE is a threshold voltage of V _{T11E to} V _T1nE (not shown).

In the present embodiment, the value of V ₀ is set to be substantially equal to the reference voltage V _BC for detecting the change in the operating state shown in FIG. By doing so, when V _INT decreases and becomes an information holding state of V _BC or less, that is, V ₀ or less, the current flowing through LM1 becomes 0, which is one of the main purposes of the present invention to reduce power consumption. It is extremely effective.

In FIG. 31, V _G > V _T10E +
_{V L, V PP> V L} + V T18E + V T19E + V T20E, V PP '> V
_L2 ', V _PP "> V _L2 " (V _T is the MOS corresponding to each subscript
It is as described in the above-mentioned reference that the condition of (threshold voltage of transistor) must be satisfied. If these conditions are satisfied, in the state of V _INT < V _BC , that is, the information holding state, Also, each outputs a predetermined voltage. It should be noted that the fact that _VL to _VINT in this state is _achieved is as shown in FIG.

FIG. 32 shows another embodiment of FIG. 30E.

In FIG. 31, V _L2 ′, V _L2 ″, etc. are output even in the state of V _INT < V _BC (or V ₀ ), but it may be desirable to set the output to 0 V in some cases. The embodiment is one of the specific embodiments for that purpose.

As shown in FIG. 32, in this embodiment, 11
E, 12E, 21E and 22E are grounded in Q _{24E to} Q _27E when φ _BC is in a high voltage state (information holding state). The grounding of 21E and 22E at this time is to prevent the gate voltages of Q _21E and Q _22E from fluctuating, and may be unnecessary in some cases. Further, in the case of the present embodiment, the output is 0 V in the information holding state, so V _G , V
It is desirable to set _PP , V _PP ′ and V _PP ″ to 0V in order to reduce the power consumption of the entire LSI chip.

According to the embodiment described above, V _L2 ′ = V _L2 ″ = 0 V can be set in the information holding state, and power consumption can be reduced.

FIG. 33 shows another embodiment of the LM1 shown in FIGS. 31 and 32.

In FIG. 31 and FIG. 32, V ₀ to V _BC are set to reduce the power consumption of LM1, but in the present embodiment, the circuit in the low voltage state (information holding state) of φ _BC due to Q _23E1. The whole is separated from the ground, current is prevented from flowing from V _INT to the ground, and power consumption is reduced.

According to the present embodiment, V ₀ and V _BC can be set arbitrarily, and low power consumption can be achieved.

FIG. 34 shows an embodiment in which the V _L generating circuit and the φ _BC generating circuit shown in FIG. 12 are realized by the same circuit.

As shown in the figure, here, Q ₁₅₁ ′ and R ₁₅₁ ′ (see FIG. 12) are added to LM1 to generate φ _BC at the same time as V _L. Figure 1 shows the operation related to φ _BC generation.
Exactly the same as 2.

In this embodiment, V _T17E and V _T151 ′ (Q
_If the threshold voltage of ₁₅₁ ') is made substantially equal, V ₀ to V _BC will be obtained, as is apparent from the operation described above, and FIG.
Similarly, when V _INT is V _BC or less, current does not flow and power consumption can be reduced. Further, there is an advantage that the area occupied by the circuit can be reduced.

Here, the charge discharging resistor shown in FIG. 12 is omitted.

FIG. 35 requires a voltage higher than the power supply voltage V _{INT in} some cases in the above embodiments. For example, it is one of the embodiments of the circuit for generating voltages such as V _G , V _PP ′ and V _PP ″.

The basic construction of this embodiment has already been described in Japanese Patent Application No. 57-2.
Those disclosed in 20083 No. 29, the output phi _BO of the oscillator in the chip OSC (which is 311 and serves also acceptable in FIG. 19), an inverter circuit INV1,2, φ _B ¯, as phi _B, these 40 by charge pump operation by the signal of
The voltage of V _PO to 3 (V _INT −V _T ) is output to E. Here, V _T is the threshold voltage of each MOS transistor.

In such a structure, in this embodiment, a switch for switching SW31E and SW32E is provided as shown in the figure, and the charge pump signal is changed to φ _B →
Switch from φ _r , φ _B ￣ to φ _r ￣ to reduce the number of charge pumps and reduce power consumption. In addition, INV
1, INV2 also stopped its operation by Q _30E , and OSC
Stops the operation in the same manner as in FIG. In addition to this, a significant reduction in power consumption will be achieved.

According to the embodiment described above, in the information holding operation state, a voltage of V _INT or more can be generated with the minimum necessary power consumption. In this embodiment, the charge pump signal is switched by the switch.
It is also possible to provide a charge pump circuit for φ _r and φ _{r −} in parallel as in 2 and so on.

FIG. 36 shows an example in which the embodiment of FIG. 35 is applied to the circuit of FIG. 16 of Japanese Patent Application No. 58-105710.

As shown in the figure, this circuit is a full-wave rectification type charge pump circuit, and is capable of obtaining a large output current. Here, V _PO ′ = 2 (V _INT =
V _T ) is output.

Also in this embodiment, SW3 is used as in FIG.
The charge pump signal is switched by 1E 'and SW32E'.

According to this embodiment, an internal power supply with low power consumption and a relatively large current capacity can be realized.

Now, in the embodiment of FIG. 30, F, G
In general, the voltage is reduced to φ _xl , φ _P2l ￣
The pressure is increased by 10 ', 210 ", but in the information holding state,
When the output of F and G is set to the power supply voltage V _INT or higher, the boosting efficiency may be better. The same applies to H. Specific examples will be described below.

FIG. 37 is the same as FIG. 30, F, G, and H.
This is one of the embodiments in which the voltage according to the outputs V _L2 ′ and V _L2 ″ in FIG. 30E is output in the normal operation state, and V _INT or higher voltage is output in the information holding state.

In the figure, reference numeral 253 is a circuit for outputting a voltage corresponding to the voltage of V _L2 ′, V _L2 ″, and its concrete circuit configuration is shown in Japanese Patent Application No. 56-57143, 56-168698.
And Japanese Patent Application No. 58-105710. 252 is a circuit that outputs a voltage of V _INT or higher regardless of the above. Here, the input / output (either one of them depending on the case) of the above two circuits is switched by the switches SW250 and SW251, and the output of 252 in the normal operation and the output of 253 in the information holding operation are output to φ _out .

According to the present embodiment, the output of FIGS. 30F, G, and H can be raised to V _INT or higher voltage during the information holding operation, and the boosting after that becomes easy. It goes without saying that the voltage here includes both a direct current and a pulse signal.

FIG. 38 shows an embodiment in which the SW 250 or 251 of FIG. 37 is realized by a MOS transistor.

In the figure, SWM and SWM 'are equivalent to a normal two-terminal open / close switch, and here, a two-contact changeover switch such as SW251 is realized by using the above-mentioned two open / close switches.

In the SWM shown in the figure, when a high voltage is applied to 260, 258 also becomes a high voltage. When a signal is input to 261 in this state, Q ₂₅₈ is in the on state, so that signal is output to output 262. When the input is a pulse signal, the self-bootstrap circuit by the gate inversion layer capacitance of Q ₂₅₈ operates and the voltage of 258 rises, so that the signal is transmitted at high speed. At this time, Q ₂₅₉
Electrically disconnects 256 and 260 and contributes to improving the efficiency of the self-bootstrap. On the other hand, when the voltage of 260 is low, Q ₂₅₈ is turned off and no signal is transmitted.

In this embodiment, by using the circuit having the above configuration,
260 phi _BC ¯ of SWM, enter the phi _BC in the '260' SWM, therefore, turns on the SWM under normal operating conditions, the 251 signals 256, turns on the SWM 'in the information holding operation state, 257 To output signals 251 to 251 respectively.

According to this embodiment, SW250, S of FIG.
A change-over switch such as W251 can be easily formed by a MOS transistor. In addition, when the signal to be switched in this embodiment is a pulse signal, high-speed signal transmission becomes possible by the self bootstrap operation. It goes without saying that when the signal is a DC voltage, the voltages of _{259 and 260} should be selected so that the voltage of the node 258 becomes equal to or higher than the input signal voltage + _VT258 (threshold voltage of _Q258 ).

FIG. 39 shows one more specific example of FIG. 37.

In the figure, PG "is Japanese Patent Application No. 58-10571.
No. 0 is the circuit presented in FIG. 14 and has an output φ ₀ ′ corresponding to the original purpose V _L ′ and V _INT for other purposes.
Two signals with an output φ ₀ of a voltage equal to Here, the voltage of φ ₀ ′ becomes V _L ′ −V _TLL (threshold voltage of Q _LL ), which is suitable as F in FIG. That is, 130
As "by entering the, V _L2 to output" V _L2 to V _L 'reference to FIG. 31如also circuit signal -V _TLL is obtained. For example, if V _L2 ″ = 4.5 V and V _TLL = 0.5 V, a signal of 4.0 V is obtained.

In the present embodiment, the above two outputs are S
It is switched by W251 and output as φ _out . That is, in the normal body condition, a phi ₀ 'and phi _out, in the data retention state, the phi ₀ to phi _out.

Therefore, in the present embodiment, two kinds of signals can be output by the same circuit, so that two kinds of signals having different voltages can be easily obtained only by switching the outputs. Since the output φ ₀ ′ is not selected in the information holding state, it is better to use a circuit such as that shown in FIG. 32 in which V _L ′ = 0V is used as 130 in order to reduce power consumption. desirable.

FIG. 40 shows still another embodiment of FIG. 37, in which a means for outputting a signal of a voltage corresponding to V _L ′, V _INT
In this embodiment, the means for outputting the voltage signal of (1) also serve as the switch function.

In the figure, LM is Japanese Patent Application No. 56-168969.
As shown in FIG. 23, the input φ _in is made a voltage equal to V _L ′ and output to φ _out . Here, V _L ′ is preferably a voltage that becomes 0 V in the information holding state, that is, the voltage generated in FIG. 32, and is suitable for inputting V _L2 ″ and using it as G in FIG. . For example, V _L2 ″ =
If it is set to 4.5V, the voltage of φ _xl is output as 4.5V. The SWM is the same as the SWM in FIG.

In this embodiment, in the normal operation state,
Since φ _BC is a low voltage, SWM is turned off, so φ _in becomes a voltage of V _L ′ and is output to φ _ut . On the other hand, in the information holding state, V _L ′ = 0 V, φ _BC becomes a high voltage, so LM is turned off and SWM is turned on. Therefore, generally, φ _in having a voltage amplitude equal to V _INT is directly output to φ _out . In addition, LM Q ₂₆₉ is 263
Although Q ₂₆₃ is completely turned off as a ground potential when φ _BC is at a high voltage (information holding state), it is not necessary in some cases.

According to the present embodiment, the means for lowering the voltage in the normal operation state can serve as the switching switch at the time of shifting to the information holding state, which is effective in reducing the occupied area in the LSI chip.

FIG. 41 shows still another embodiment, in which one LM serves as both the LM and the SWM of FIG.

As shown in the figure, in this embodiment, Q is set in LM.
₂₇₀ and Q ₂₇₂ are added, and in the normal operation state, Q ₂₇₀ is turned on by ￣ ￣ φ _BC , V _L ′ is input to 265, and the operation of LM described above, that is, the voltage of φ _in is set to V _L ′. Equalize and output. In the information holding state, Q ₂₇₀ is turned off and Q ₂₇₂ is turned on to operate as the SWM described above.
Output _{in as it} is to Q _out .

According to this embodiment, it is possible to easily output signals having different voltages according to the operating state with a smaller number of circuits.

FIG. 42 shows an embodiment in which F and 210 ″ or A and 210 ′ of FIG. 30 are realized by the same circuit.

[0223] PG "in the figure is similar to the circuit described in FIG. 39. Here, 'and sufficiently high, (e.g., V _L' V _L in data retention state -V _TLL> V _PP ''' ) Φ ₀ ′ can be increased, but in the present embodiment, by PPC,
Drain of Q _LL in the data retention state - a short circuit between the source,
Almost V _PP ″ ″ is output as φ ₀ ′.
That is, in the state of phi _BC high voltage, the charge pumps operate by phi _r, 282 is approximately 2 (V _INT -V _T) becomes (phi _r, a signal voltage of phi _BC I _INT, the threshold voltage of the MOS transistor , All as V _T ), Q ₂₈₂ is completely turned on, and the voltage of V _PP ″ ″ is output to φ ₀ ′ almost as it is. It is easy to understand that when 2 (V _INT −V _T ) −V _T282 <V _PP ″ ″, the value of 2 ( _INT −V _T ) −V _T282 is output (V _T282 is Q ₂₈₂ threshold voltage).

According to this embodiment, the signal for the normal operation state (generally stepped down) and the signal for the information holding state (generally stepped up) can be output in the same circuit, Since the number of required circuits is reduced, it is effective in reducing power consumption and occupied area.

In the PPC circuit, Q ₂₈₇ is for grounding 282 during normal operation and for completely turning off Q ₂₈₂ . Further, here, the V _L ′ generating unit 130 may be of any type such as that shown in FIG. 31 (outputting a constant voltage even in the information holding state) or FIG. 32 (outputting 0 V in the information holding state). .

In this embodiment, since V _PP ″ ″ is output as φ ₀ ′, its current driving capability is required. In such a case, FIG. 1 of Japanese Patent Application No. 58-105710 is used.
The problem can be easily solved by using a circuit such as 7.

FIG. 43 is one of the concrete examples of FIG. 30G.

In the figure, the circuit shown by the broken line is Japanese Patent Application No. 58-105.
710 is a circuit disclosed in No. 710, and is V in a normal operation state.
_{As PC} , V _L2 ′ -V _TSS (V _TSS is the threshold voltage of Q _SS )
Is output. On the other hand, in the information holding operation state, as described above, Q _{282 of} PPC is turned on and V _INT is output as V _CP . At this time, as the circuit for generating V _L2 ′, any circuit shown in FIGS. 31 and 32 may be used.

As described above, PPC is added as in this embodiment.
It is easy to do _L2Voltage corresponding to
Is output and V_INTTo output the circuit
realizable. In addition, according to the present embodiment, during the information holding operation
The voltage of I / O line (Fig. 30) is V_INTBut in some cases
Therefore, further boosting is performed by using each of the embodiments described above.
It is also possible.

As described above, the LS that operates the circuit by the voltage obtained by dropping the external power supply voltage in the LSI chip
Several embodiments in which the present invention is applied to I chips have been described. Although a dynamic type memory is described here as an example, it is needless to say that the present invention can be applied to a static type memory as disclosed in FIG. 4 of Japanese Patent Application No. 58-24579. Further, in FIG. 19, the memory array section is shown as one block for the sake of simplicity of description, but it is not limited to this and, for example, Japanese Patent Application No. 56-81.
It can be applied as it is to the configuration of the memory array as disclosed in Nos. 042, 57-125687, and 58-4162, which is designed to increase the S / N ratio by dividing the data after data into a plurality. Among them, the circuit related to the power feeding means constituted by Q _{5 to} Q ₇ in FIG. 19 may be shared by a plurality of divided data lines as shown in FIG. 17 of Japanese Patent Application No. 56-81042. Furthermore, the MO as disclosed in Japanese Patent Application No. 58-105710.
A combination of S-transistor dimensions can also be employed.

Although the present invention has been described in detail with reference to the embodiments, the scope of application of the present invention is not limited to these. For example, although the memory circuit is mainly described here, as described at the beginning of this specification, if a part thereof has an information holding function, a memory LSI,
It can be applied to all logic LSIs or other LSIs. Also, regarding the type of element used, p-type,
LSI using both n-type MOS transistors, CMOS type LSI using both in combination, LSI using bipolar type transistors, BI / CMOS type LSI combining CMOC type and bipolar type, and Si material. L using not only the used LSI but also compound semiconductor
LS in which elements are formed on a substrate of SI, for example, GaAs type
It can be applied to I etc. as it is.

Further, the basic idea of the present invention is that, in addition to holding information with low power consumption as described above, the entire LSI can operate at low speed under certain specific conditions, so extremely low power consumption is required. It is also applicable when you want to operate with.

[0233]

According to the present invention described above, the power consumption of the entire LSI chip in the information holding state can be made extremely small, and a semiconductor device suitable for a battery backup operation or the like can be provided.

[Brief description of drawings]

FIG. 1 is an embodiment for explaining the basic concept of the present invention.

FIG. 2 is an embodiment for explaining the basic concept of the present invention.

FIG. 3 is an embodiment for explaining the basic concept of the present invention.

FIG. 4 is an embodiment for explaining the basic concept of the present invention.

FIG. 5 shows a specific example of the operating state detecting means.

FIG. 6 is a specific example of the operating state detecting means.

FIG. 7 is a specific example of the operating state detecting means.

FIG. 8 is a specific example of the operating state detecting means.

FIG. 9 shows a specific example of the operating state detecting means.

FIG. 10 is a specific example of the operating state detecting means.

FIG. 11 is a specific example of the operating state detecting means.

FIG. 12 is a specific example of the operating state detecting means.

FIG. 13 is a specific example of the operating state detecting means.

FIG. 14 is a specific example of the operating state detecting means.

FIG. 15 is a specific example for reducing the power consumption of the entire chip.

FIG. 16 is a specific example for reducing the power consumption of the entire chip.

FIG. 17 is a specific example for reducing the power consumption of the entire chip.

FIG. 18 is a specific example for reducing the power consumption of the entire chip.

FIG. 19 is a specific example for reducing the power consumption of the entire chip.

FIG. 20 is a specific example for reducing the power consumption of the entire chip.

FIG. 21 is a specific example for reducing the power consumption of the entire chip.

FIG. 22 is a specific example for reducing the power consumption of the entire chip.

FIG. 23 is a specific example for reducing the power consumption of the entire chip.

FIG. 24 is a specific example for reducing the power consumption of the entire chip.

FIG. 25 is a specific example for reducing the power consumption of the entire chip.

FIG. 26 is a specific example for reducing the power consumption of the entire chip.

FIG. 27 is a specific example for reducing the power consumption of the entire chip.

FIG. 28 is a specific example for reducing the power consumption of the entire chip.

FIG. 29 is a drawing of each specific example in the case where the LSI chip has a voltage limiter.

FIG. 30 is a drawing showing each specific example in the case where the LSI chip has a voltage limiter.

FIG. 31 is a drawing of each specific example in the case where the LSI chip has a voltage limiter.

FIG. 32 is a drawing of each specific example in the case where the LSI chip has a voltage limiter.

FIG. 33 is a drawing of each specific example in the case where the LSI chip has a voltage limiter.

FIG. 34 is each drawing of a specific example in the case where the LSI chip has a voltage limiter.

FIG. 35 is a drawing of a specific example in the case where the LSI chip has a voltage limiter.

FIG. 36 is a drawing of each specific example in the case where the LSI chip has a voltage limiter.

FIG. 37 is a drawing showing a specific example in the case where the LSI chip has a voltage limiter.

FIG. 38 is a drawing of each specific example in the case where the LSI chip has a voltage limiter.

FIG. 39 is a drawing showing each specific example in the case where the LSI chip has a voltage limiter.

FIG. 40 is a drawing showing a specific example in the case where the LSI chip has a voltage limiter.

FIG. 41 is a drawing showing a specific example in the case where the LSI chip has a voltage limiter.

FIG. 42 is a drawing of each specific example in the case where the LSI chip has a voltage limiter.

FIG. 43 is a drawing of each specific example in the case where the LSI chip has a voltage limiter.

[Explanation of symbols]

1 ... LSI chip, 2 ... Circuit part, 3 ... Power supply wiring, 4 ... Signal input wiring, 5 ... Battery, 6 ... Diode.

Claims (14)

[Claims] 1. A first voltage is converted into a second voltage to convert the second voltage.
In a semiconductor device including a voltage conversion circuit for supplying the voltage of 1 to a load inside a chip, the memory cell operates with the second voltage from the voltage conversion circuit and has a memory cell including one transistor and one capacitor. Further comprising a dynamic memory formed in the inside of the chip, wherein the voltage conversion circuit includes a charge pump circuit that generates the second voltage for operating the memory cell of the dynamic memory, and the charge pump circuit includes the charge pump circuit. When the second voltage is generated, the operation is switched between an operation with a large current supply capacity and an operation with a small current supply capacity, and the charge pump circuit operates when the charge pump circuit operates with a small current supply capacity. It is characterized in that the value of the small current supply capacity is set so that the supply current does not become zero. Semiconductor device. 2. The semiconductor device according to claim 1, wherein the magnitude of the current supply capability of the charge pump circuit is set by the application frequency of a voltage pulse applied to the charge pump capacitance of the charge pump circuit. 3. The semiconductor device according to claim 1, wherein the voltage pulse applied to the charge pump capacitance of the charge pump circuit is supplied from a ring oscillator built in a chip of the semiconductor device. . 4. The semiconductor device according to claim 1, wherein the voltage pulse applied to the charge pump capacitance of the charge pump circuit is supplied from a refresh timer built in a chip of the semiconductor device. . 5. The voltage pulse applied to the charge pump capacitance of the charge pump circuit in the operation with the small current supply capability is generated from the refresh signal of the dynamic memory. 2. The semiconductor device according to item 2. 6. The operation is such that when the load current is large, the charge pump circuit has a large current supply capacity, and when the load current is small, the charge pump circuit has a small current supply capacity. The semiconductor device according to any one of claims 1 to 5. 7. A peripheral circuit is connected to the dynamic memory, and when the peripheral circuit operates at high speed, the load current is large,
7. The semiconductor device according to claim 6, wherein the current of the load is reduced when the peripheral circuit operates at a low speed. 8. The semiconductor device according to claim 1, wherein the charge pump circuit comprises a plurality of charge pump circuits. 9. The semiconductor device according to claim 8, wherein one of the plurality of charge pump circuits is stopped in the operation of the small current supply capacity. 10. An operation state detecting means for detecting an operation state of a semiconductor device is formed inside the semiconductor chip, and the charge pump circuit supplies a substrate voltage to a semiconductor substrate on which the dynamic memory is formed. 2. When supplying voltage, the operation is switched between an operation having a large current supply capacity and an operation having a small current supply capacity of the charge pump circuit according to the detection result of the operation state detecting means. Item 10. The semiconductor device according to any one of Items 9 to 9. 11. The semiconductor device according to claim 10, wherein said operating state detecting means detects any one of voltage, current, temperature and control signal. 12. The operating state detecting means detects a plurality of voltage levels and sets the current supply capability of the charge pump circuit according to the detection results of the plurality of voltage levels. The semiconductor device according to claim 11. 13. The operating state detecting means is a circuit for comparing with a predetermined reference voltage or a threshold circuit having a threshold value in the circuit itself.
13. The semiconductor device according to claim 12. 14. The semiconductor device according to claim 13, wherein the threshold circuit uses a threshold voltage of a MOS transistor.