JPH0758226A - Semiconductor device, manufacture thereof, and memory cell device method - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device which is prevented from deteriorating in yield and reliability without causing disconnection and short circuit of a metal wiring enhanced in degree of integration by disposing the patterns of a selecting transistor and a cell transistor of the memory cell as close to each other as possible, shortened in manufacturing term, and lessened in manufacturing cost. CONSTITUTION:A memory cell MOS transistor possessing a gate structure where a floating gate electrode 205 and a control gate electrode 207a are formed in multilayer and a selection gate MOS transistor are connected in series to form a non-volatile memory cell, and the non-volatile memory cell is built in a semiconductor device, wherein the control gate electrode of the memory cell MOS transistor and the gate electrode 207c of the selection gate MOS transistor are formed of the same wiring layer in one piece.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a built-in non-volatile memory cell and a method of manufacturing the same, and more particularly to a gate electrode structure of a non-volatile memory cell including a memory cell transistor and a select gate transistor, and its structure. The present invention relates to a forming method and a memory cell driving method.

[0002]

2. Description of the Related Art Various structures have been proposed as memory cells for nonvolatile semiconductor memories such as EPROM (UV erasable / rewritable ROM) and EEPROM (electrically erasable / rewritable ROM). One of them is a MOS transistor (cell transistor) for a memory cell having a stacked gate structure and an MO for a select gate.
There is a FLOTOX (FLOtaing gate Tunnel OXide) type cell in which an S transistor (selection transistor) is connected in series.

FIG. 5 shows an example of a plane pattern of a conventional FLOTOX type cell. FIG. 6 shows A-A in FIG.
An example of the cross-sectional structure along the line is shown. 5 and 6
, 201 is a semiconductor substrate, 202 is a source region of the cell transistor, 204 is a tunnel insulating film of the cell transistor, 205 is a floating gate electrode of the cell transistor, 206 is an interelectrode insulating film, 207 a is a control gate electrode of the cell transistor, 209 Is the first gate insulating film, 21
Reference numeral 1 is a first drain region (drain of the cell transistor and source of the select transistor). 212 is the second
Drain region (drain of selection transistor), 213
Is a gate electrode of the select transistor, and 214 is an interlayer insulating film on the control gate electrode.

Reference numeral 215 is a bit line formed of a metal wiring formed on the interlayer insulating film 214, which contacts the drain 212 of the selection transistor through a contact opening formed in the interlayer insulating film 214, and 215a is a bit line contact. The area is shown.

Next, an example of a process for manufacturing the FLOTOX type cell of FIG. 6 by the double-layer polycrystalline silicon process will be described with reference to the wafer cross-sectional structure shown in FIGS. 7A to 7D.

First, as shown in FIG. 7A, a sacrificial thermal oxide film 203 is formed on a P-type silicon substrate 201, and impurities are selectively ion-implanted and diffused to form a cell transistor. The source region 202 and the drain region 211 are formed.

Next, as shown in FIG. 7B, a first gate insulating film 209 is formed on the entire surface of the substrate, and a part of the first gate insulating film 209 is removed by a photo-etching technique to form a tunnel insulating film on the exposed substrate surface. The film 204 is formed thin.

Next, as shown in FIG. 7C, the first-layer polycrystalline silicon film 205 and the interelectrode insulating film 20 are formed on the entire surface.
6. The second-layer polycrystalline silicon film 207 is sequentially deposited. Next, as shown in FIG. 7D, the second-layer polycrystalline silicon film 207, the inter-electrode insulating film 206, and the first-layer polycrystalline silicon film 205 are selectively etched by a photo-etching technique. And the control gate electrode 2 of the cell transistor
07a, the floating gate electrode 205, and the gate electrode 213 of the select transistor are formed.

By such a manufacturing process, the interelectrode insulating film 206 is formed on the gate electrode 213 of the select transistor.
Although the second-layer polycrystalline silicon pattern 207b is left through, the polycrystalline silicon pattern 207b is not used as an electrode.

Then, the drain region 212 of the select transistor is formed by selectively ion-implanting and diffusing impurities by using the second-layer polycrystalline silicon pattern 207b of the select transistor as a mask.

After that, an interlayer insulating film (21 in FIG. 6) is formed on the entire surface.
4) is deposited and the upper surface thereof is flattened by a reflow process, and then a contact opening and a metal wiring layer (215 in FIG. 6).
And wiring patterning.

Next, a method of driving the FLOTOX type cell of FIG. 6 will be described with reference to FIGS. 8 (a) to 8 (c). When erasing data, as shown in FIG. 8A, Vpp is applied to the gate of the selection transistor QS and the control gate of the cell transistor QM while Vss is applied to the drain of the selection transistor QS and the source of the cell transistor QM. When applied, charges are injected into the floating gate of the cell transistor QM by the tunnel current,
The threshold voltage of the cell transistor QM is set high.

In writing data, as shown in FIG. 8B, the selection transistor Q is supplied with the ground potential Vss applied to the source / control gate of the cell transistor QM.
A high voltage Vpp (for example, 14 to 15) is applied to the drain and gate of S.
V) is applied to extract electric charges from the floating gate of the cell transistor QM and set the threshold voltage of the cell transistor QM low.

At the time of reading the data, FIG.
As shown in, the source of the cell transistor QM has Vss,
With the read clamp voltage (for example, 1 V) applied to the drain of the selection transistor QS, the selection transistor Q
By applying a read voltage (for example, 3 V) to the gate of S and the control gate of the cell transistor QM, the on / off state is detected by the cell current determined according to the threshold voltage of the cell transistor QM.

By the way, the FLOTOX type cell has two
Since it is composed of the individual transistors QS and QM, the cell size is large and high integration is difficult, and it was considered that it is not suitable for increasing the memory capacity.

When the gate distance between the select transistor and the cell transistor is reduced in order to achieve high integration of the FLOTOX type cell, the aspect ratio in the gap between the gates of both transistors becomes high after the gate is formed.

Thus, after that, when a BPSG (boron phosphorus silicate glass) film or a BSG (boron silicate glass) film is deposited as the interlayer insulating film 214, the gate end facing the gap between the gates of both transistors is formed. In the portion E, the deposited thickness of the interlayer insulating film 214 is locally thinned. Then, in the subsequent reflow step in a phosphorus atmosphere, high concentration phosphorus in the atmosphere reacts with boron in the locally thinned portion of the interlayer insulating film 214 to generate a precipitate, and the protrusion 214a. As a result, the problem that it grows occurs.

This protrusion causes a disconnection or a short circuit of the metal wiring in the subsequent formation of the metal wiring, which causes a reduction in yield and reliability in manufacturing the semiconductor device.

[0019]

As described above, in the conventional semiconductor device having the FLOTOX type cell built therein, when the gate distance between the select transistor and the cell transistor is made close to each other in order to achieve high integration of the cell, the semiconductor device is formed on the cell. There has been a problem that the formed metal wiring is broken or short-circuited, leading to a decrease in yield and reliability.

The present invention has been made to solve the above problems, and does not cause a disconnection or a short circuit of a metal wiring formed on a memory cell, without lowering the yield or the reliability. A semiconductor device and a method of manufacturing the same, in which the distance between the selection transistor of the memory cell and the cell transistor can be made as close as possible to achieve high integration, and further, the manufacturing period can be shortened and the manufacturing cost can be reduced. The purpose is to provide.

[0021]

According to the present invention, a MOS transistor for a memory cell having a gate structure in which a floating gate electrode and a control gate electrode are laminated and an MO for a select gate are provided.
In a semiconductor device including a nonvolatile memory cell in which an S transistor is connected in series, a memory cell MO
Control gate electrode of S transistor and MOS for select gate
It is characterized in that the gate electrode of the transistor is integrally formed by the same wiring layer.

[0022]

Since the control gate electrode of the memory cell transistor and the gate electrode of the select gate transistor are integrally formed of polycrystalline silicon in the same wiring layer, the step difference of the interlayer insulating film deposited on the both gates can be prevented. It can be kept low.

As a result, the distance between the two transistors can be minimized without causing disconnection or short circuit of the metal wiring formed on the interlayer insulating film on the memory cell, without lowering the yield and lowering the reliability. It is possible to achieve high integration by approaching.

Further, since the step of the interlayer insulating film deposited on the memory cell can be suppressed to a low level, the reflow step after the interlayer insulating film deposition can be omitted or the reflow period can be shortened, and the manufacturing cost can be reduced. Can be realized.

[0025]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows an example of a plane pattern obtained by extracting a part (four memory cells) of an array of FLOTOX type memory cells in an EEPROM according to an embodiment of a semiconductor device of the present invention.

FIG. 2 shows an example of a sectional structure taken along the line AA in FIG. In FIG. 1 and FIG.
Is a semiconductor substrate, 202 is a source region of the cell transistor, 204 is a tunnel insulating film of the cell transistor, 20
5 is a floating gate electrode of the cell transistor, 206 is an interelectrode insulating film, 207a is a control gate electrode of the cell transistor, 209 is a first gate insulating film, 211 is a first drain region (drain of the cell transistor and source of the selection transistor). Is. Reference numeral 212 is a second drain region (drain of the selection transistor), 207c is a gate electrode of the selection transistor, and 214 is an interlayer insulating film formed on the control gate electrode.

Reference numeral 215 denotes a bit line formed of a metal wiring formed on the interlayer insulating film 214, which contacts the drain 212 of the selection transistor through a contact opening formed in the interlayer insulating film 214, and 215a is a bit line contact. The area is shown.

Reference numeral 216 is a diffusion layer region (common source) formed in the inter-row portion of the cell array so as to be commonly connected to the source regions of four adjacent cell transistors in the cell array, and 216a is the common source and Vss. The contact area with the line is shown.

Here, the control gate electrode 207a of the cell transistor and the gate electrode 207c of the selection transistor are integrally formed of the same wiring layer (polycrystalline silicon in this example).

In the plane pattern of the cell array shown in FIG. 1, control lines (word lines) are integrally connected to the control gate electrodes 207a of the cell transistors and the gate electrodes 207c of the selection transistors of the cells in the same row of the cell array. Are formed. Further, a field insulating film is formed in a portion where element isolation between columns of the cell array is required.

According to the EEPROM of the above embodiment, the control gate electrode 207a of the cell transistor and the gate electrode 207c of the selection transistor are integrally formed by the same wiring layer (polycrystalline silicon in this example). The step difference of the interlayer insulating film 214 deposited on both gates can be suppressed low.

As a result, the interlayer insulating film 2 on the memory cell is formed.
It is possible to achieve high integration by making the distance between both transistors as close as possible without causing a disconnection or a short circuit of the metal wiring 215 formed on the semiconductor substrate 14 and without lowering the yield or the reliability. it can.

Incidentally, the size of the cell of the above embodiment is about 15 in the arrangement direction of the cell transistors and the selection transistors (Y direction in FIG. 1) as compared with the cell of the conventional example.
% Can be reduced.

Next, an example of a process for manufacturing the FLOTOX type cell of FIG. 2 by the double-layer polycrystalline silicon process will be described with reference to the wafer sectional structure shown in FIGS. 3 (a) to 3 (d).

First, as shown in FIG. 3A, a sacrificial thermal oxide film 203 is formed on a P-type silicon substrate 201, and further, a channel formation region thereof is formed in order to make a cell transistor described later a depletion type. A channel impurity region 301 is formed by selectively ion-implanting.

Next, as shown in FIG. 3B, a first gate insulating film 209 is formed on the entire surface of the substrate, and a part of the first gate insulating film 209 is removed by a photo-etching technique to form a tunnel insulating film on the exposed substrate surface. The film 204 is formed thin, and the first-layer polycrystalline silicon film 205 is further deposited on the entire surface.

Next, as shown in FIG. 3C, the first-layer polycrystalline silicon film 205 is selectively etched by a photo-etching technique to make the floating gate electrode 2 of the cell transistor.
Form 05. After that, the source region 302 and the drain region 303 of the cell transistor are formed by selectively ion-implanting and diffusing the impurities by using the floating gate electrode 205 as a mask. After that, an interelectrode insulating film 206 and a second-layer polycrystalline silicon film 207 are sequentially deposited on the entire surface.

Next, as shown in FIG. 3D, the second-layer polycrystalline silicon film 207 is selectively etched by a photo-etching technique to control cell electrode control gate electrode 2
07a and the gate electrode 207c of the selection transistor are integrally formed.

Then, the drain region 304 of the select transistor is formed by selectively ion-implanting and diffusing the impurities using the gate electrode 207c of the select transistor as a mask.

After that, an interlayer insulating film (21 in FIG. 2) is formed on the entire surface.
4) is deposited and the upper surface thereof is flattened by a reflow process, and then contact openings and metal wiring layers (21 in FIG. 2) are formed.
5) Deposition and wiring patterning are performed.

According to the manufacturing method as described above, since the step difference of the interlayer insulating film 214 deposited on the memory cell can be suppressed to a low level, the reflow process after the interlayer insulating film deposition is omitted or the reflow period is shortened. It becomes possible to reduce the manufacturing cost.

Next, a driving method of the FLOTOX type cell of FIG. 2 will be described with reference to FIGS. 4 (a) to 4 (c). Although erasing and reading of data from the FLOTOX type cell of FIG. 2 are performed in the same manner as in the conventional FLOTOX type cell, data writing is slightly different from that of the conventional example FLOTOX type cell.

That is, when erasing data, FIG.
As shown in (a), in the state where Vss is applied to the drain of the selection transistor QS and the source of the cell transistor QM, the erase high voltage Vpp (for example, 1 pp) is applied to the gate of the selection transistor QS and the control gate of the cell transistor QM.
4 to 15 V) to inject charges into the floating gate of the cell transistor QM by a tunnel current,
The threshold voltage of the cell transistor QM is set high (for example, set to about 5 to 6V).

When writing data, as shown in FIG. 4B, the ground potential Vss is applied to the source of the cell transistor QM and the write high voltage Vpp (eg 14 to 15 V) is applied to the drain of the selection transistor QS. Then, by applying a write gate voltage (for example, 5 V) lower than the write high voltage Vpp to the gate of the selection transistor QS and the control gate of the cell transistor QM, charges are extracted from the floating gate of the cell transistor QM, Lower threshold voltage of (eg −
Set to about 5-6V).

In this case, since the cell transistor QM is a depletion type, even if its drain voltage is low,
It is possible to extract charges from the floating gate.
In reading data, as shown in FIG. 4C, the source of the cell transistor QM is supplied with Vss, and the drain of the selection transistor QS is supplied with a read clamp voltage (for example, 1 V). By applying a read gate voltage (for example, 3 V) to the control gate of the transistor QM, the cell current on / off state determined according to the threshold voltage of the cell transistor QM is detected. The threshold value of the selection transistor QS is about 0.8V.

The drive circuit for supplying Vcc, Vpp, the read clamp voltage, and the read gate voltage necessary for driving the FLOTOX type cell as described above is provided on the EEPROM chip. Also, V
Although pp may be supplied from the outside of the chip, if a boosting circuit for boosting Vcc to generate Vpp is provided on the chip, Vpp can be supplied from this boosting circuit.

Although the above embodiment shows the EEPROM integrated circuit, the present invention is not limited to this, and is generally applied to a semiconductor device including a FLOTOX type cell such as a logic type integrated circuit having a FLOTOX type cell. Applicable.

[0048]

As described above, according to the present invention, a memory cell can be selected without causing a disconnection or a short circuit of a metal wiring formed on the memory cell, and without lowering the yield or the reliability. (EN) Provided are a semiconductor device and a method for manufacturing the semiconductor device, in which the patterns of the transistor and the cell transistor can be made as close as possible to each other to achieve high integration, and further, the manufacturing period can be shortened and the manufacturing cost can be reduced. it can.

[Brief description of drawings]

FIG. 1 is an EEPR according to an embodiment of a semiconductor device of the present invention.
FIG. 3 is a plan pattern diagram showing a part (four memory cells) of an array of FLOTOX type memory cells in the OM.

FIG. 2 is a sectional view showing an example of a sectional structure taken along line AA in FIG.

3 is a cross-sectional view showing a wafer cross-sectional structure in an example of a process of manufacturing the FLOTOX type cell of FIG. 2 by a two-layer polycrystalline silicon process.

4 is a circuit diagram shown for explaining a driving method of the FLOTOX type cell of FIG.

FIG. 5 is a plan pattern diagram showing an example of a conventional FLOTOX type cell.

6 is a cross-sectional view showing an example of a cross-sectional structure taken along the line AA in FIG.

7 is a cross-sectional view showing a wafer cross-sectional structure in an example of a process of manufacturing the FLOTOX type cell of FIG. 6 by a two-layer polycrystalline silicon process.

8 is a circuit diagram shown for explaining a driving method of the FLOTOX type cell of FIG.

[Explanation of symbols]

201 ... Semiconductor substrate, 202 ... Source region of cell transistor, 204 ... Tunnel insulating film of cell transistor,
205 ... Floating gate electrode of cell transistor, 206 ...
Inter-electrode insulating film, 207a ... Control gate electrode of cell transistor, 207c ... Gate electrode of selection transistor, 2
09 ... First gate insulating film, 211 ... First drain region (drain of cell transistor and source of select transistor), 212 ... Second drain region (drain of select transistor), 214 ... Interlayer insulating film, 215 ... Bit line, 215a ... Bit line contact region.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 27/115

Claims (5)

[Claims] 1. A memory cell MOS transistor having a gate structure in which a floating gate electrode and a control gate electrode are stacked, and a source connected to a drain of the memory cell MOS transistor, and a control gate of the memory cell MOS transistor. A semiconductor device having a built-in non-volatile memory cell including a selection gate MOS transistor having a gate electrode integrally formed with the same wiring layer as the electrode. 2. The semiconductor device according to claim 1, wherein the memory cell MOS transistor is a depletion type. 3. A step of forming a first gate insulating film on the entire surface of a semiconductor substrate, removing a part of the first gate insulating film by a photo-etching technique, and forming a tunnel insulating film on the exposed substrate surface, and the first gate. A step of depositing a first-layer polycrystalline silicon film on the entire surface of the insulating film and the tunnel insulating film; and a step of selectively etching the first-layer polycrystalline silicon film by a photo-etching technique for a memory cell A step of forming a floating gate electrode of a MOS transistor; and a step of selectively implanting and diffusing impurities into the semiconductor substrate using the floating gate electrode as a mask,
A step of forming a source region / drain region of the memory cell MOS transistor; a step of sequentially depositing an interelectrode insulating film and a second-layer polycrystalline silicon film on the entire surface of the semiconductor substrate; A step of selectively etching the second-layer polycrystalline silicon film by a photo-etching technique to integrally form a control gate electrode of the memory cell MOS transistor and a gate electrode of the select gate MOS transistor; A step of forming a drain region of the selection gate MOS transistor by selectively ion-implanting and diffusing impurities into the semiconductor substrate using the gate electrode of the gate MOS transistor as a mask. Device manufacturing method. 4. The method for manufacturing a semiconductor device according to claim 3, wherein before the first gate insulating film is formed on the entire surface of the semiconductor substrate, a MOS transistor for a memory cell to be formed on the semiconductor substrate is formed. A method of manufacturing a semiconductor device, further comprising a step of implanting ions for depleting the memory cell MOS transistor in a channel formation region. 5. A memory cell MOS transistor having a gate structure in which a floating gate electrode and a control gate electrode are stacked, and a source connected to a drain of the memory cell MOS transistor, and a control gate of the memory cell MOS transistor. When erasing data when driving a non-volatile memory cell comprising a select gate MOS transistor having a gate electrode integrally formed with the same wiring layer as the electrode, the drain of the select gate MOS transistor and the memory cell With the ground potential applied to the source of the MOS transistor, the MO for the selection gate
When a high voltage for erasing is applied to the gate of the S transistor and the control gate of the memory cell MOS transistor, when writing data, the source of the memory cell MOS transistor is at ground potential and the drain of the select gate MOS transistor is at high voltage. In the state where a voltage is applied, a write gate voltage lower than the write high voltage is applied to the gate of the selection gate MOS transistor and the control gate of the memory cell MOS transistor, and when reading data, the memory cell MOS transistor The read gate voltage is applied to the gate of the selection gate MOS transistor and the control gate of the memory cell MOS transistor in a state where the ground potential is applied to the source and the read clamp voltage is applied to the drain of the selection gate MOS transistor. The memory cell driving method to be.