JPH0758114A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device having excellent reliability and being capable of eliminating the peel-off and decrease in strength of a bump during etching in a semiconductor device having semiconductor chips mounted to a wiring substrate by the face-down method. CONSTITUTION:A barrier metal 14 is formed on an electrode pad 13 of a semiconductor chip 11, on which a solder bump 16 is formed smaller than the barrier metal 14, and a solder removing film 15 is formed on the barrier metal 14 around the solder bump 16 in this semiconductor device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a semiconductor chip is mounted on the surface of a wiring board via bumps.

[0002]

2. Description of the Related Art Recently, many methods using bare chips have been developed as a technology for high density and high speed of electronic equipment. As a method of mounting a bare chip on a substrate, there are a wire bonding method, a TAB method, a flip chip method and the like. The wire bonding method is a method in which a semiconductor chip is placed face-up on a substrate and the aluminum pad of the chip and the pad on the substrate are connected by a fine wire such as gold. 50 μm by wire bonding method
At present, it is difficult to connect a very small pitch such as a pitch, and it is not suitable for high density. The TAB method is a method in which wiring is made of Cu foil on a polyimide film and the electrode pads of the semiconductor chip and the Cu foil leads are connected via bumps. This method has the drawbacks that the polyimide film itself is expensive and that dimensional accuracy cannot be sufficiently obtained due to heat shrinkage of the film for fine connection.

On the other hand, in the flip chip method, metal bumps are formed on a pad of aluminum or the like on a semiconductor chip by a vapor deposition method, a dipping method, a plating method or the like, and a Si wiring board, an aluminum nitride wiring board, an alumina wiring board or the like is formed. This is a method of aligning and connecting with the metal pads on the surface, and research and development is being conducted as a favorite of high-density and high-speed semiconductor device technology.

13 to 18 show a conventional method of manufacturing a semiconductor device by flip chip mounting. First, as shown in FIG. 13, the aluminum electrode pad 131 and the insulating film 1
A semiconductor chip 132 on which 33 is formed is prepared.

Next, as shown in FIG. 14, a barrier metal 141 is formed on the semiconductor chip 132. Next in FIG.
As shown in FIG. 5, a mask 151 is formed of photoresist to form bumps of solder on the barrier metal 141.

Next, as shown in FIG. 16, solder bumps 161 are formed by a plating method. Next, as shown in FIG. 17, the resist mask 151 is removed. Next, as shown in FIG. 18, the barrier metal 141 is removed by etching using the solder bump 161 as a mask.

Finally, the semiconductor chip 132 is mounted by reflow on a wiring board having connection pads. In the semiconductor device configured as described above, the barrier metal and the solder bump can be formed in a self-aligned manner. Therefore, when the solder is melted by the reflow process, the solder bumps are rounded due to the surface tension, but since the underlying barrier metal is sufficiently small, the height of the solder bumps can be increased.

However, as shown in FIG. 18, when etching the barrier metal 141, there is a problem in that the connection of the solder bumps 161 is violated due to side etching, and sufficient strength cannot be obtained. That is, although the height of the solder bump can be increased in order to ensure the reliability of the device, there is a problem that the connection strength cannot be obtained and the solder bump is very fragile against external force such as thermal stress.

On the other hand, as a method of solving the above-mentioned problems, there is a method of cutting the barrier metal larger than the solder bump by using a photolithography technique, instead of forming the barrier metal by self-alignment using the solder bump as a mask. According to this method, the resist mask is formed so as to cover the solder bumps, so that the barrier metal is not side-etched under the solder bumps. The steps will be described below with reference to FIGS.

First, as shown in FIG. 19, a semiconductor chip 1
After the solder bumps 161 are formed on the surface 32, a mask 191 is formed of photoresist so as to cover the solder bumps 161. At this time, the mask 191 is formed larger than the solder bump 161 so that the side etching of the barrier metal 141 does not reach the lower part of the solder bump 161.

Next, as shown in FIG. 20, a barrier metal 141 is formed by etching using this resist mask 191 as a mask. However, as shown in FIG. 21, when the semiconductor chip 161 is mounted on a wiring board, if the solder bump melts, it spreads due to the surface tension, which causes a problem that the height of the solder bump cannot be sufficiently secured. Therefore, since the height of the solder bump is not sufficient, such a solder bump cannot sufficiently absorb the stress generated by the difference in thermal expansion force between the substrate and the semiconductor chip.

The above-mentioned two problems become remarkable in the case of a fine bump. That is, when the solder bumps are formed by the plating method and then the metal of the barrier metal is etched using the solder bumps as a mask, the strength of the bumps is reduced by the side etching when the bumps become fine, and the bumps are peeled off. On the other hand, if the size of the barrier metal is increased in order to prevent the influence of side etching, the solder bumps cannot spread laterally due to surface tension and a sufficient height cannot be obtained. There was a problem that the bumps were short-circuited.

[0013]

As described above, a semiconductor device having solder bumps having sufficiently high bumps and high connection strength has not been obtained so far. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device having bumps with sufficiently high bump height and high connection strength.

[0014]

In order to solve the above problems, as shown in FIG. 1, a semiconductor device according to the present invention has a semiconductor chip 11 having an electrode pad 13 on its main surface, and an electrode pad 13 on the semiconductor chip 11. A first metal layer 14 formed and having a main surface, and a second metal layer 16 formed on the main surface of the first metal layer 14 and having a contact surface smaller than the main surface of the first metal layer 14. And the first portion of the peripheral portion of the second metal layer 16
A layer 15 formed on the main surface of the metal layer 14 that is not compatible with the second metal 16 and a wiring board 17 having connection pads 18 on the main surface, and the semiconductor chip 11 is provided on the wiring board 17. The first metal layer 14 and the second metal layer 1
It is mounted via 6 and the electrode pad 13 and the connection pad 18 are electrically connected.

That is, for example, a barrier metal such as Cu, Ti, Ni, C is formed as the first metal layer 14 on the electrode pad 13 formed of aluminum or the like on the semiconductor chip 11.
It is composed of r, Fe or the like or a composite film of these. Second on this
As the metal layer 16 of, for example, solder bumps are formed, and the solder bumps 16 smaller than the barrier metal 14 are formed. A layer 15 that is not compatible with the second metal layer is formed on the surface of the barrier metal 14 as the first metal layer around the solder bump 16 as the second metal layer.

Here, the layer which is not compatible with the second metal layer means, for example, when the second metal layer is composed of solder,
Any oxide film or nitride film of the metal layer may be used. In addition, C that does not get wet with resins such as epoxy and acrylic and the second metal
It can be formed of a metal such as r or Ti. That is,
In the reflow step, the layer 15 that does not repel the second metal layer when the second metal melts may be one that repels the molten layer of the second metal.

The barrier metal 14 is formed in order to prevent the second metal formed of solder or the like and the electrode pad 13 of aluminum or the like from diffusing and mixing in the heat treatment step. Code 1
Reference numeral 2 is an insulating film formed of SiO ₂ or the like for protecting the semiconductor chip 11.

In the above structure, the barrier metal 14 is 2
You may form more than one layer. In addition, as the second metal layer,
Tin, lead, indium, cadmium, silver, antimony,
A simple substance such as gallium or an alloy thereof may be used.

[0019]

A layer in which the area of the main surface of the first metal layer 14 is larger than the contact area with the second metal layer 16 and which does not fit in the second metal layer 16 around the second metal layer 16. 15 is formed, and at the time of etching the first metal layer 14, the layer 15 that is not compatible with the second metal layer 16 is used as a mask or a resist mask is formed so as to cover the second metal layer 16. By forming and etching, the side etching does not affect the contact surface between the first metal layer 14 and the second metal layer 16. Therefore, the problem of bump strength reduction bump peeling does not occur. Further, since the layer 15 that is not compatible with the second metal layer 16 is formed around the second metal layer 16, even if the second metal 16 is melted in the reflow process, It does not spread over the entire surface, and the bump height can be increased. Moreover, since the bumps 16 can be prevented from spreading in the lateral direction, even if the bump pitch becomes small, there is no short circuit with the adjacent bump.

[0020]

EXAMPLES Examples of the present invention will be described in detail below. 1 to 6 are cross-sectional views in each step illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

First, as shown in FIG. 2, a 6-inch-thickness 500 μ having an electrode pad 13 formed of aluminum.
m semiconductor chip wafers are prepared. 15m in this
There is an m-square semiconductor chip 11, the size of the aluminum electrode pad 13 is 40 μm square, and the pad pitch is 80 μm.
m is formed in the peripheral portion of the semiconductor chip 11.

Next, as shown in FIG. 3, Ti (0.1) is formed as a first metal barrier metal 14 on the entire surface of the wafer.
μm), Cu (1.0 μm), or Cr (0.1 μm
m), Cu (1.0 μm) or Ti (0.1 μm) N
A metal composite film of i (1.0 μm) or the like is formed by an electron beam evaporation device or a sputtering device.

Next, as shown in FIG. 4, the aluminum electrode pad 13 is overlapped with the opening of 50 μm square whose one side is 10 μm larger than that of the aluminum electrode pad 13 (40 μm square) by photolithography technique and almost the center of this opening. After forming the first resist 41 (thickness 3 μm),
An oxide film or a nitride film of the barrier metal is formed as a layer 15 that is not compatible with solder as the second metal by using an appropriate oxidant or nitriding agent.

Next, as shown in FIG. 5, the first resist 4 is formed.
1 is removed, and a second resist 51 is formed by photolithography technique so as to overlap with the aluminum pad 13.
A μm square opening is formed. 12g tin / in this opening
The barrier metal layer 1 was immersed in a solution consisting of 1 g of lead, 8 g / l of lead, and 100 g / l of alkanesulfonic acid at a bath temperature of 25 ° C.
4 is the cathode, the second metal is solder (tin 63%, lead 37
%) As an anode and a current density of 5 A / dm ² is applied and gently agitated, Sn / Pb = 63
/ 37 solder alloy 16 was plated at 50 μm.

Next, the semiconductor chip 1 is manufactured by the method described above.
After forming the solder bumps 16 on the surface electrode pads via the barrier metal layer 14, the second resist 51 was dissolved and removed with acetone.

Next, as shown in FIG. 6, the barrier metal layer 1
4 is etched using the oxide film or nitride film of the barrier metal, which is the solder plating layer 16 and the layer 15 that is not compatible with solder, as a mask. For the barrier metal layer 14, for example, Cu / Ti
When Cu is used, Cu is etched with a solution consisting of a mixed solution of citric acid and hydrogen peroxide, and then Ti is removed by EDT.
Etching is performed with a mixed solution of A, ammonia, and hydrogen peroxide solution. This semiconductor wafer is heated at 230 ° C in a nitrogen atmosphere.
And heat for 1 minute to reflow the solder. The solder bump is completed here.

Next, as shown in FIG. 1, the semiconductor chip 11 having the bumps 16 produced as described above is mounted on the wiring board 1.
Join to 7. The connection pads made of Cu or the like on the wiring board 17 and the solder bumps 16 on the semiconductor chip 11 are
For example, the contact is made by using a positioning device using a half mirror. At this time, the wiring board 17 is placed on a stage having a heating mechanism and preheated to about 230 ° C., which is higher than the melting point 183 ° C. of the eutectic solder (Sn / Pb = 63/38) forming the solder bumps. On the other hand, the stage for fixing the semiconductor chip 11 is also heated in a nitrogen atmosphere at the same temperature as the stage temperature of 230 ° C. to melt the eutectic solder forming the bumps 16 and thereby the semiconductor chip 11 is formed.
Are electrically connected and mounted on the wiring board 17 to form a semiconductor device.

At this time, a semiconductor device may be constructed by filling and hardening a silicone resin between the semiconductor chip 11 and the wiring board 17 so as to cover the mounted semiconductor chip 11.

In the semiconductor device thus produced, the height of the bump could be as high as about 50 μm. The connection strength was 20 g / piece. A 15 mm square semiconductor chip having 1000 bumps, for example, manufactured as described above was mounted on an aluminum nitride wiring board. This sample is -65 ° C (30 min) to 25 ° C (5 min)
~ 150 ° C (30min) ~ 25 ° C (5min) 30
No breakage was observed at the connection portion even after performing 00 cycles. Furthermore, in the case of a semiconductor device configured by filling a silicone resin or the like between the semiconductor chip 11 and the wiring board 17 and curing it, no breakage occurred even after 5000 cycles.

As described above, a sufficiently high bump can be formed even at the time of mounting a fine bump, and at the same time, the bonding strength of the bump can be obtained. Therefore, it is possible to improve the reliability of the semiconductor device by simultaneously ensuring the height of the bump and strengthening the bonding strength of the bump, which are in a trade-off relationship with each other.

In the present embodiment, the oxide layer or the nitride layer of the barrier metal 14 is used as the layer 15 that is not compatible with the second metal, but a resin layer such as epoxy, acrylic or polyamine acid or the like is formed on the barrier metal 14. When the second metal is solder, the same effect can be obtained by using Cr, Ti, or the like as a metal that does not wet the solder.

Next, the second embodiment of the present invention will be described with reference to FIGS. 7 to 9.
An example will be described. 7 to 9 are cross-sectional views in each step. In this embodiment, a nickel plating layer is used as the first metal layer and a solder layer is used as the second metal layer.
An oxide film of a nickel-plated layer was used as the layer that is not compatible with the second metal.

As shown in FIG. 7, the aluminum electrode pad 13 (40 μm square) having a thickness of 5 μm is formed by the photolithography technique.
A first resist 71 having a 50 μm square opening whose one side is 10 μm larger than that of the first resist 71 is formed, and nickel sulfate 250 g / l, nickel chloride 40 g / l, and boric acid 4 are formed in the opening.
Immersing in a solution consisting of 0 g / l and using the barrier metal layer 14 as a cathode and high-purity nickel as an anode at a bath temperature of 25 ° C.,
With a current density of 5 A / dm ² applied and gentle stirring, a nickel layer 72 is plated in a thickness of 3 μm on the opening.
Next, the surface of the nickel plating film 72 is oxidized with an oxidizing agent to form a layer 15 that is not compatible with solder. After this first
The resist layer 71 is removed by dissolution with acetone.

Next, as shown in FIG. 8, a second resist 8 is formed.
1 (thickness: 50 μm) is spin-coated, and a resist layer 81 having an opening of 40 μm square whose one side is 10 μm smaller than the 50 μm square of the nickel plating film 15 is formed by photolithography. After that, the nickel oxide film 15 in the opening is removed by etching, and the nickel plated film 72 is dipped in a solution of tin 12 g / l, lead 8 g / l, and alkanesulfonic acid 100 g / l, and the bath temperature is 25 ° C. The barrier metal layer 14 is used as a cathode and solder (tin 6
3%, lead 37%) as an anode, current density of 2 A / dm ^{2 is} applied and gently agitated, Sn / Pb = 63 /
37 solder alloy 16 is plated to 50 μm. After that, the resist mask 81 is removed with a solvent such as acetone.

Next, as shown in FIG. 9, the barrier metal layer 1
4 is a solder plating layer 16 and a layer that is not compatible with solder, and is etched using the nickel oxide film 15 as a mask. This semiconductor wafer is heated in a nitrogen atmosphere at 230 ° C. for 1 minute to reflow the solder. The solder bump is completed here.

Next, as shown in FIG. 1, the semiconductor chip 11 having the bumps 16 produced as described above is bonded to the wiring board 17 as in the first embodiment. The connection pads made of Cu or the like on the wiring board 17 and the solder bumps 16 on the semiconductor chip 11 are brought into contact with each other by using, for example, an alignment device using a half mirror. At this time, the wiring board 17 is placed on a stage having a heating mechanism, and the eutectic solder (Sn / Pb = 63/3) that forms the solder bumps.
It is preheated to about 230 ° C, which is higher than the melting point of 183 ° C of 7). On the other hand, the base for fixing the semiconductor chip 11 is also heated in the nitrogen atmosphere at the same temperature as the stage temperature of 230 ° C. to melt the eutectic solder forming the bumps 16 to electrically connect the semiconductor chip 11 to the wiring board 17. A semiconductor device is formed by mounting.

At this time, a semiconductor device may be constructed by filling and hardening a silicone resin between the semiconductor chip 11 and the wiring board 17 so as to cover the mounted semiconductor chip 11.

A 15 mm square semiconductor chip having, for example, 1000 bumps formed as described above was mounted on an aluminum nitride wiring board. This sample is -65
℃ (30min) ~ 25 ℃ (5min) ~ 150 ℃ (3
Even after 3000 cycles of 0 min) to 25 ° C. (5 min), no break was observed at the connection point. Further, in the case of a semiconductor device configured by filling a silicone resin or the like between the semiconductor chip 11 and the wiring board 17 and curing it, 50
No fracture occurred even after 00 cycles.

Further, the aluminum pad 13 on the semiconductor chip 11 is formed in a 15 μm square, and the pad pitch is 20 μm.
With a very fine pad with 10 bumps
Barrier metal layer 72 when formed to a thickness of 20 μm square
The bumps 16 did not peel off even after etching. Also, the bump strength was 10 g / piece, and there was no problem. When this semiconductor chip was mounted on a wiring board, no short circuit occurred between the bumps.

In the present embodiment, nickel was used as the first metal, but the present invention is not limited to this, and copper or copper alloy may be used, and the melting point may be higher than that of the second metal. The resin used for the encapsulation is not limited to silicone-based ones; for example, acrylic or epoxy-based ones have an encapsulating effect and are not particularly limited as long as they are insulating resins. Those with a low value are desirable.

Next, a method of manufacturing a semiconductor device according to the third embodiment of the present invention will be described with reference to FIGS. 10 and 11 are cross-sectional views in each step. First of all,
The solder bump 16 is formed as a second metal layer of 40 μm square by the conventional method shown in FIG. Next, as shown in FIG. 10, a resist is applied to the front surface in a thickness of 3 μm, and a resist 101 having a 50 μm square is formed by photolithography so as to cover the solder bumps 16.

Next, after the barrier metal 14 is removed using the resist 101 as a mask, the resist 101 is also removed. Next, as shown in FIG. 11, an oxide film or a nitride film 15 of the barrier metal is selectively formed on the barrier metal 14 having no solder bump. At this time, instead of the oxide film or the nitride film 15, a resin layer or a metal layer which is not wet with solder may be formed. This layer 15 constitutes a layer that is not compatible with the second metal.

By mounting the semiconductor chip 11 thus formed on the substrate as shown in FIG. 1, the same effects as those of the first and second embodiments can be obtained. In this example, a 15 mm square semiconductor chip having 1000 bumps was mounted on an aluminum nitride wiring board. This sample is -65 ° C (30 min) to 25 ° C (5 min) to 1
3000 at 50 ° C (30 min) to 25 ° C (5 min)
No fracture was observed at the connection points even after cycling. Furthermore, in the case of a semiconductor device configured by filling a silicone resin or the like between the semiconductor chip 11 and the wiring board 17 and curing it, no breakage occurred even after 5000 cycles.

Further, in the present embodiment, as shown in FIG. 12, by forming the layer 15 that is not compatible with the second metal with a resin to a height substantially equal to that of the solder bumps 16, the solder bumps have a high height and a straight wall shape. A semiconductor device which can be formed and has high reliability and long life can be provided.

In the embodiment described above, Sn / Pb eutectic solder was used as the second metal, but the second metal is not limited to this. For example, high temperature solder of Sn / Pb = 5/95 or Bi is used for solder alloy. , In, Sb, etc. added or I
It may be an n, In alloy.

Although the second metal layer is formed by electroplating, it may be formed by other means such as chemical plating. Of course, the wiring board may be of silicon type, aluminum nitride type, alumina type, resin substrate type, or the like. In addition, various modifications may be made without departing from the scope of the present invention.

[0047]

As described above in detail, the strength of the bumps is not reduced and the bumps are not peeled off during the etching of the barrier metal, and the bumps are difficult to spread in the lateral direction when mounted on the wiring board, and the height is high. It is possible to prevent the occurrence of breakage due to thermal stress in the bump connection portion, and to provide a semiconductor device having a connection with high electrical and mechanical reliability.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a semiconductor device of the present invention.

FIG. 2 is a cross-sectional view explaining the method of manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 3 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 4 is a cross-sectional view illustrating the method of manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 5 is a cross-sectional view illustrating the method of manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 6 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 7 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 8 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 9 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 10 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 11 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 12 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.

FIG. 13 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.

FIG. 14 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.

FIG. 15 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.

FIG. 16 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.

FIG. 17 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.

FIG. 18 is a cross-sectional view illustrating the conventional method for manufacturing a semiconductor device.

FIG. 19 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.

FIG. 20 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.

FIG. 21 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 Reference Signs List 11 semiconductor chip 12 protective layer 13 electrode pad 14 barrier metal layer that is a first metal layer 15 layer that is a second metal layer that is not compatible with solder 16 solder layer that is a second metal layer 17 wiring board 18 connection pad

Claims (1)

[Claims] 1. A semiconductor chip having an electrode pad on a main surface, a first metal layer formed on the electrode pad and having a main surface, and a contact surface formed on the main surface of the first metal layer. The first
A second metal layer that is smaller than the main surface of the metal layer, and a layer that is formed on the main surface of the first metal layer in the peripheral portion of the second metal layer and that is not compatible with the second metal; A wiring board having a connection pad on its main surface, wherein the semiconductor chip has the first and second wiring boards on the wiring board.
The semiconductor device, wherein the electrode pad and the connection pad are electrically connected to each other by being mounted via the metal layer.