JPH0756979B2 - Multiplex distribution device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a time division multiplex distribution device used in a data communication system, and particularly, in multiplex distribution delivery
The present invention relates to a buffer mechanism for compensating a mismatch between a data reception speed from a low speed line side and a data transmission speed to a high speed line side.

[Prior Art] In an open data communication system such as VAN, it is not always easy to achieve perfect system synchronization. In particular, in a system including a telephone-type public line network, with regard to a multiplex distribution device interposed between a terminal device group accommodated via the public line network and a high-speed relay line, the reception speed from the low-speed line side and the high-speed line It is difficult to match the transmission speed to the side.

In general, it is a conventional technique to provide a buffer to compensate for a mismatch in transmission speed, and a multiplex distribution device is also provided with a buffer for each low speed line in order to compensate for the above speed mismatch. It is beyond the scope of conventional technology to configure such that a certain amount of data is sent to the high-speed line side when it is accumulated. Documents relating to this type of apparatus include Japanese Patent Laid-Open Nos. 47-37224 and 58-161439.

[Problems to be solved by the invention]

In the conventional buffer mechanism as described above, the buffer amount is fixed, and the relation with the modem interface signal is not sufficiently taken into consideration, so that the length of the message transmitted by the terminal device is limited, and the message is absorbed. The range of possible speed differences is also limited. To remove these restrictions, the amount of buffer must be increased. However, if a general-purpose multiplex / distribution device is manufactured under such a policy, a terminal device with a short message to be transmitted causes an unnecessary transmission delay, and in a system with a small speed difference. Also causes similar complaints. It should be noted that these problems will be described later in detail with reference to the embodiments of the present invention.

It is an object of the present invention to solve these problems and to absorb the difference between the receiving speed from the low speed line side and the transmitting speed to the high speed line side under different kinds of conditions. An object of the present invention is to provide a high multiplex distribution device.

[Means for solving problems]

In the multiplex / delivery device according to the present invention, the low-speed line corresponding unit is a fast-in / fast-out type buffer for temporarily storing data from the low-speed line, and a counter for counting input data to the buffer. And a means for starting the buffer input operation and the counter counting operation when the carrier detection signal in the low-speed line modem interface is turned on, and when the count value of the counter reaches a predetermined value or the carrier detection signal. Has means for starting data transfer from the buffer to the high-speed line side when is turned off, and means for presetting the predetermined count value to a desired value.

[Action]

According to the above configuration, the buffer operation and the counting of the input data are started simultaneously with the arrival of the data from the low speed line side,
Data transfer from the buffer to the high-speed line side is started when a certain amount of data is accumulated in the buffer or when the arrival of the data ends. Moreover, this scheduled count value can be set to meet various conditions such as the message length of the terminal device to be connected and the transmission speed difference between the low speed line side and the high speed line side. Therefore, both sufficient reliability and sufficient flexibility can be obtained.

〔Example〕

In the following, one embodiment of the present invention will be described in detail together with the problems in the conventional device.

FIG. 1 shows an example of a data communication system suitable for use with the present invention. The communication control device 1 includes a multiplex / distribution device (hereinafter abbreviated as TDM) 2 on the center side and a low-speed line 7
TDM2 is a high-speed trunk line modem (M) 3
Is connected to the high speed relay line 12 via. The other end of the trunk line 12 is connected to the terminal-side TDM 5 via the high-speed trunk line modem 4. This TDM 5 is connected to a telephone-type public line network (hereinafter referred to as a telephone line network) 10 via a plurality of terminal line modems 6 and a network control unit (NCU) 9, and this telephone line network 10 has a plurality of terminals. The devices 11 are connected to the terminal line modem 8 and the network control device 9, respectively.

FIG. 2 is for explaining the timing system in the system of FIG. In FIG. 2, the telephone network 10 and the network control device 9 in FIG. 1 are omitted, and instead,
The internal structure of TDM2 and 5 is shown in some detail. Each TDM
Has a low speed line corresponding unit 20 connected to each low speed line, a common control unit 21, and a relay line corresponding unit 22 connected to a relay line, and the relay line corresponding unit 22 has a built-in jitter absorbing circuit. . The system timing and problems associated with it will be described below with reference to this figure.

The data transmission from the communication control device 1 to the terminal device 11 is controlled by a single clock source, so that a data error due to the difference between the transmission speed and the reception speed does not occur. More specifically, the transmission timing st2 for the communication control device 1 is TDM.
2, the transmission timing S from the high speed trunk line modem 3
Derived from T2. That is, the timing ST2 is divided into 1 / n by the common control unit 21 after the jitter is absorbed by the relay line corresponding unit 22, and is supplied to the communication control device 1 as the transmission timing st2 via the low speed line corresponding unit 20. It On the other hand, the reception timing RT synchronized with this ST2 is supplied from the high speed trunk line modem 4 to the TDM 5, and after the jitter is absorbed by the trunk line corresponding part 22, it is divided into 1 / n by the common control part 21.
It is supplied to the terminal line modem 6 as the transmission timing st1 via the low speed line corresponding unit 20, and is further supplied to the terminal device 11 as the reception timing rt via the terminal line modem 8. In short, the data transmission from the communication control device 1 to the terminal device 11 is controlled by a single clock sourced from the high speed trunk line modem 3. Therefore, in each TDM, there is no difference between the receiving speed and the transmitting speed, and neither data loss nor void occurs.

However, the situation is different regarding the data transmission from the terminal device 11 to the communication control device 1. As shown in FIG. 1, the TDM 5 and the terminal device 11 are connected via a telephone line network 10. The telephone line is a two-line type line, so that the terminal line modems 6 and 8 normally send out carrier signals in turn. More specifically, when sending data from the terminal device 11 to the communication control device 1, the terminal modem 8
Send a carrier signal to the modem 6 on the TDM side, while the modem 6
The carrier signal from the modem to the modem 8 is stopped, and conversely, when data is sent from the communication control device 1 to the terminal device 11, the TDM signal is transmitted.
A carrier signal is sent from the side modem 6 to the terminal side modem 8,
Meanwhile, the carrier signal from the modem 8 to the modem 6 is stopped. That is, when transmitting data from the terminal device 11 to the communication control device 1, since there is no carrier signal sent from the TDM side modem 6 to the terminal side modem 8, a means for supplying timing to the terminal device 11 from the TDM 5 side is provided. There is no. As a result, the terminal device 11 transmits data in accordance with the transmission timing st2 with the terminal modem 8 as the clock source. This st2 is given as the reception timing rt to the low speed line corresponding unit 20 in the TDM 5 via the TDM side modem 6.
On the other hand, the trunk line corresponding unit 22 in the TDM 5 receives the transmission timing from the high speed trunk line modem 4 in synchronization with the reception timing RT.
Upon receipt of ST2, data is sent to the modem 4 in accordance with this. Reception timing R with which this transmission timing ST2 is synchronized
The clock source of T, and hence the clock source of ST2, is the high-speed trunk line modem 3 on the center side as described above.

That is, in TDM5, the reception timing rt and the transmission timing ST2 are independent of each other, and as a result, a difference occurs between their speeds. If the transmission speed is higher than the reception speed, a gap (surplus data) will occur in the data sent from the terminal device 11 to the communication control device 1, and conversely,
If the reception speed is higher than the transmission speed, the data collides with each other and is lost, and in any case, a data error results.

The inconvenience caused by the speed difference as described above can be basically solved by providing each low speed line corresponding unit 20 with a buffer for absorbing the speed difference. However,
Applying the normal buffer technology as it is will not give sufficiently satisfactory results. FIG. 3 generally shows a terminal side TDM 5 equipped with a speed absorbing buffer. Fast-in / fast-out (FI
FO) type bit buffer 201, bit counter 202,
Bit counter control circuit 203 and data transfer control gate 2
04 is provided. Data bits sent from the terminal device via the terminal line modem 6 are sequentially accumulated in the bit buffer 201, and the accumulated data bits are counted by the bit counter 202. According to the conventional technique, the bit counter control circuit 203 monitors whether or not the count value of the bit counter 202 has reached a specific value set in setting, and when it is detected that the specific value has been reached. , The data transfer control gate 204 is opened, and the contents of the bit buffer 201 are sequentially transferred to the common control unit 21.

In the device thus configured, the count value of the bit counter as the data transmission start condition is fixed,
Even in a system in which the transmission speed and the reception speed are matched, data is not transmitted until a predetermined number of bits are accumulated, and as a result, the transmission delay time increases. In addition, even if there is a speed difference, more messages than necessary will be accumulated for short messages, so the transmission delay time will be longer than necessary, and conversely, for messages that are longer than a certain amount, more bits will be accumulated. Due to the lack of numbers, data errors cannot be prevented.

FIG. 4 shows the low-speed line support unit 20 of the terminal-side TDM 5 according to the present invention.
An example will be shown. However, FIGS. 1 to 3 and 4
It should be noted that the figure is reversed left and right. This low-speed line support unit 20 is a FIFO-type hit buffer 201.
And a bit counter 202 for counting the bits written in the bit buffer 201, and this bit counter 2
Bit counter control circuit 203 for controlling 02, data transfer control gate 204, and modem interface 205
And an initial value generation circuit 206 for setting an initial value in the bit counter 202. The initial value to be generated by the initial value generation circuit 206 is designated by the initial value setting strap 207. A plurality of initial values that can be specified are prepared. In the present embodiment, they are provided for the 64-bit bit buffer 201,
These are "0", "8", "16", and "32". Data transfer control gate 2
Upon receiving the transfer permission signal from the bit counter control circuit 203, the 04 changes the contents of the bit buffer 201 to the common control unit 2
Send to the multiplexing circuit in 1. Modem interface 205
Receives the data RD and various modem interface signals from the terminal line modem 6, and the reception timing signal rt and the carrier detection signal CD in the modem interface signal are the bit buffer 201, the bit counter 202, and the bit counter control circuit 203. Used to control.

When the bit counter control circuit 203 senses that the carrier detection signal CD is on, it performs an initializing operation. That is, a reset signal is sent to the bit buffer 201 to clear it, and then the initial value generating circuit 206 sets the initial value generated according to the specification of the initial value specifying strap 207 in the bit counter 202.

When the carrier detection signal CD is turned on, the bit buffer 20
At 1, the reception data RD is sampled at the reception timing rt and written at the # 64 position. The bit written at the # 64 position is shifted toward the # 1 position and held at the vacant position closest to the # 1 position. That is, the received successive bits are held in order at successive bit positions starting from the # 1 position. Reading is always performed from the # 1 position and 1
Each time a bit is read, the remaining bit in the bit buffer 201 is shifted one bit toward the # 1 position.

The bit counter 202 subtracts "1" from the count value every time the bit of the received data is written at the position # 64 of the bit buffer.

When the count value of the bit counter 202 becomes “0” or the carrier detection signal CD is turned off, the bit counter control circuit 203 sends the data transfer enable signal to the data transfer control gate 2
The bit at position # 1 of the bit buffer 201 is sequentially transmitted to the multiplexing circuit in the common control section 21 in synchronization with the transmission timing from the bit. The countdown operation of the bit counter 202 is not performed after the count value reaches "0" and when the carrier detection signal CD is off. When the carrier detection signal CD is off, data input to the bit buffer 201 is also prohibited.

Data reading from the bit buffer 201 continues until it is empty. If the carrier detect signal CD is on when it becomes empty, it will be the same as when the first "CD on" was detected, bit buffer 201 and bit counter 2
02 is initialized. Bit buffer 201
These are initialized even when the overflow occurs.

The operation of each part of the circuit shown in FIG. 4 described above is summarized as follows.

(1) Initialization of bit buffer and bit counter When the carrier detection signal CD changes from OFF to ON, the bit buffer becomes empty, and when the signal CD is ON, the bit buffer overflows. (2) Reading from the bit buffer starts. When the count value of the counter reaches "0" When the signal CD turns off (3) Prohibition of reading from the bit buffer If the count value of the bit counter is other than "0" and the signal is
When the CD is on When the bit buffer becomes empty (4) When the write signal CD to the bit buffer is on (5) When the write inhibit signal CD to the bit buffer is off (6) The countdown of the bit counter A value other than "0" and a signal
When reception timing rt occurs while CD is on (7) Bit counter countdown prohibition When the bit counter count value is "0" When signal CD is off The initial value of the bit counter is as follows. It is good to specify. If the system synchronization is perfect and the transmission speed and the reception speed match, specify "0". As a result, the data retention time in the bit buffer becomes "0", and the transmission delay due to the buffer is eliminated. When there is a difference between the transmission speed and the reception speed, a small value is generally designated if the message (data block) transmitted by the terminal device is short, and a large value is designated if the message is long. If the transmission speed is higher than the reception speed, a value that is as large as possible is specified so that voids do not occur in the data, and if the reception speed is higher than the transmission speed, a value that is as small as possible is selected so that rear-end collision of data does not occur. If the initial value is selected to be half the capacity of the bit buffer, the same speed difference absorption capability can be obtained for both the case where the transmission speed is higher and the case where the reception speed is higher. Therefore, when it is not known which speed is higher, or when the magnitude relationship is not constant, it is preferable to specify such an initial value. These conditions are investigated in advance, and the optimum initial value is designated by the initial value designation strap 207 when the device is installed or when the circumstances change thereafter.

Next, the overall operation will be described with reference to FIGS. When attempting to send data from the terminal device 11 to the communication control device 1, the terminal device 11 turns on the RS signal (not shown) in the modem interface signal,
The transmission of the carrier signal is requested to the terminal line modem 8 on the terminal side, and accordingly, the modem 8 transmits the carrier signal to the terminal line modem 6 on the TDM5 side. When the modem 6 receives the carrier signal, it turns on the carrier detection signal CD.
When the low speed line corresponding unit 20 in the TDM 5 detects this "CD ON", it resets the bit buffer 201 and sets the initial value designated in the bit counter 202.

After that, in synchronization with the reception timing rt from the modem 6,
The data from the terminal device 11 is written in the bit buffer 201 one bit at a time, and at the same time, the content of the bit counter 202 is decremented by "1". When the content of the bit counter 202 becomes "0", the bit counter control circuit 203 supplies the data transfer enable signal to the data transfer control gate 204, whereby the content of the bit buffer 201 is multiplexed in the common control unit 21. 1 in synchronization with the transmission timing from the circuit
Bits are sent one by one. The content of the bit counter 201 is "0"
After reaching, the bit counter 202 does not count down even if data is input to the bit buffer 201.

When the bit buffer 201 becomes empty, the bit counter control circuit 203 turns off the data transfer permission signal to stop the data transmission to the multiplexing circuit, and the bit buffer 20.
Initialize 1 and bit counter 202. The initialization operation is also performed when the bit buffer 201 overflows.

When the signal CD from the modem 6 turns off, the bit buffer
Data input to 201 is stopped. At this time, if the content of the bit counter 202 is not "0", a data transfer enable signal is generated and data transmission to the multiplexing circuit is started.
In addition, the countdown of the bit counter 202 thereafter is stopped.

By the above operation, in the terminal side TDM5, the difference between the receiving speed from the terminal device side and the transmitting speed to the relay line side is absorbed by the low speed line corresponding unit 20, and the data is transferred to the common control unit 21 without error. You can

The common control unit 21 in the TDM 5 also receives data from the other low speed line corresponding unit 20 and generates multiplexed data. This multiplexed data is sent from the relay line corresponding unit 22 to the high speed relay line modem 4. As described above, the timing used at this time is the transmission timing ST2 which is synchronized with the reception timing RT of the high-speed trunk line modem 4, and the clock source is T
The high-speed trunk line modem 3 on the DM2 side. On the other hand, the communication control device side TDM2 receives the multiplexed data from the high speed relay line modem 3 and controls the communication through the relay line corresponding unit 22, the common control unit 21, and the low speed line corresponding unit 20. Send to device 1. Regarding the timing at this time, the reception timing RT from the high speed relay line modem 3 is divided into 1 / n by the common control unit 21 after the jitter is absorbed by the relay line corresponding unit 22, and the low speed line corresponding unit 20 is After that, it is supplied to the communication control device 1 as the reception timing rt. That is, data is transmitted / received from the common control unit 21 of the terminal side TDM 5 to the communication control device 1 based on a single clock source (modem 3), and accordingly, a data error due to speed mismatch may occur. There is no. Therefore, the data error due to the speed mismatch is prevented by the speed difference absorption in the low speed line corresponding unit 20 of the terminal side TDM 5 as described above.

In the above, the present invention is applied to a network including a telephone line network, but the present invention is applied to TDM interposed between lines whose communication speeds do not match regardless of the type of the line network. You can If necessary, communication control unit side TD
The present invention may be applied to M.

〔The invention's effect〕

INDUSTRIAL APPLICABILITY According to the present invention, it is possible to prevent a data error caused by a mismatch between the transmission rate and the reception rate in TDM under various conditions, and thus, it is possible to achieve multiplex and delivery that is excellent in both reliability and flexibility. A device can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a data communication system suitable for using TDM according to the present invention, and FIG.
1 is a block diagram showing the timing system in the system of FIG. 1, FIG. 3 is a block diagram showing the terminal side TDM in FIGS. 1 and 2 in a little detail, and FIG. 4 is a low speed line support in TDM according to the present invention. It is a block diagram which shows an example of a part. 1 ... Communication control device, 2,5 ... Multiple collection and distribution device, 3,4 ...
High-speed trunk line modem, 6,8 …… Terminal line modem, 10 ……
Telephone line network, 11 …… Terminal device, 20 …… Low speed line compatible part,
21 ... Common control section, 22 ... Relay line corresponding section, 201 ... Bit buffer, 202 ... Bit counter, 203 ... Bit counter control circuit, 204 ... Data transfer control gate, 205
...... Modem interface, 206 …… Initial value generation circuit, 2
07: Initial value specification strap, CD: Carrier detection signal.

Claims (3)

[Claims] 1. A time division multiplex distribution system having a high-speed line connection unit connected to a high-speed line and a plurality of low-speed line connection units respectively connected to a plurality of low-speed lines, wherein the low-speed line support unit is provided. A fast-in / fast-out buffer for temporarily storing data from the low-speed line, a counter for counting input data to the buffer, and carrier detection in a modem interface signal of the low-speed line. Means for starting an input operation of the buffer and a counting operation of the counter when the signal is turned on in response to a signal, and the count value of the counter reaches a predetermined value or the carrier detection signal is turned off. Means for starting data transfer from the buffer to the high-speed line side in response to the failure, and means for presetting the predetermined value to a desired value Multiple collection and delivery device equipped with. 2. The multiplex distribution apparatus according to claim 1, wherein the means for starting the data transfer from the buffer to the high speed line side simultaneously stops the counting operation of the counter. 3. The multiplex distribution device according to claim 2, wherein the low speed line is connected to a terminal device via a public line network.