JPH0752755B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor device having a well structure, and relates to a dynamic random access memory (DRAM) having a CMOS structure. Is what is used.

(Prior Art) In a conventional dynamic random access memory (DRAM), a CMOS structure has not been adopted in a peripheral circuit of a memory cell array. But recently, DR with CMOS structure
AM is increasing. FIG. 2 shows an IC cross section of a 1-transistor / 1-capacitor type DRAM having a CMOS structure. In the figure, 1 is a P-type semiconductor substrate, 2, 2'is a Pwell (P-type well ... manufactured in the same step), 3 is an Nwell (N-type well), 4 is a capacitor insulating film, and 5 is a capacitor electrode. , 6 is a transistor gate insulating film, 7 is a transistor gate electrode, 8 is an N ⁺ diffusion layer (source or drain), 9 is a P ⁺ diffusion layer (source or drain), 10 is an insulating film, 11 is an Al wiring, A is a memory cell section, and B is its peripheral circuit section. Pw
The ell layer 2 has a higher concentration than the P-type substrate 1. By the way, recently, it has been found that it is desirable to form cells in a high-concentration well in order to prevent soft error, as reported in IEDM (International Association).

(Problems to be Solved by the Invention) However, in the conventional method, Pwel containing cells is used.
The concentration of the 1-layer 2'and the P-well layer 2 containing the peripheral circuit were the same. Higher densities are required to reduce the soft error rate. On the other hand, from the viewpoint of circuit characteristics, too high a concentration is not desirable because it increases the diffusion capacitance between the N ⁺ diffusion layer and the Pwell and lowers the junction breakdown voltage. On the other hand, with further miniaturization in the future, the input / output circuit section will need to operate at 5V, and the internal circuit section will need to operate at a voltage of about 3.3V. It is necessary to change the well concentration such as Pwell according to such a difference in operating voltage.

The object of the present invention is to provide a method for solving the above-mentioned problems of the conventional method, and by using wells having different concentrations according to the present invention, the problems can be solved very easily.

[Structure of the Invention] A method of manufacturing a semiconductor device of the present invention comprises a step of forming a first well of a first conductivity type in a semiconductor substrate, and a step of forming a first well in the semiconductor substrate and in a selected region of the first well. Two
A step of simultaneously introducing conductivity type impurities to form second and third wells of the second conductivity type having different surface concentrations in the semiconductor substrate and the first well; and the second and third wells respectively. And forming at least one MOS transistor using the well as a substrate, respectively.

Embodiment An embodiment of the present invention will be described below with reference to the drawings. First, as shown in FIG. 1A, the first Pwell portion 102 in the cell region A of the dynamic RAM is formed on the P-type semiconductor substrate 101.
Boron is ion-implanted into the place where it should be, using the photo-etching method (the ion implantation condition at this time is that the dose amount is 2 × 10 5
^{At 14} cm ^-2 , the accelerating voltage is 100 KeV), and at the same time, ions are implanted into the portion of the peripheral circuit section B that should be the second Pwell region 102 '. After that, in a N ₂ atmosphere at a temperature of about 1190 ° C,
After the first heat treatment for about 6 hours, the Pwell regions 102, 10
2'is formed. Next, with the resist 103, the first Nwell
Areas to be regions (indicated by reference numeral 106 in FIG. 1 (b)) and parts to be second Pwell regions (FIG. 1 (b))
And indicated by reference numeral 105), phosphorus 104 is added, and the dose amount is 5 × 10 ¹³ c.
Ion implantation with m ^-2 and acceleration voltage of 100 KeV. Then 1190 ℃
The second heat treatment is performed in the N ₂ atmosphere for about 4 hours. As a result, the first Pwel with a surface concentration of 5 × 10 ¹⁷ cm ^-3 was found in the cell area.
l region 107 is formed, and in the N channel region of the peripheral circuit,
A second Pwell region 105 having a surface concentration of 2 × 10 ¹⁷ cm ⁻³ is formed (FIG. 1 (b)). After that, in the cell region A, the capacitor insulating film 108, the storage node electrode 109, the N ⁺ diffusion layer 11 are formed.
0, the gate electrode 111 of the writing and reading transistor, and the bit line wiring layer 112 are formed. Further, in the second Pwell and the first Nwell for the peripheral circuit, the gate electrode 113 of the N-channel transistor, the gate electrode 114 of the P-channel transistor, the diffusion layer regions 115 and 116, and the wiring layer 117 for drawing out each electrode, etc. Forming a CMO
An S-type DRAM is formed. (FIG. 1 (c)).

The present invention is not limited to the above embodiment, and various applications are possible. For example, in the embodiment, the present invention is applied to the case where the dynamic RAM is provided, but it may be applied to the static type memory. Although a P-type substrate is used in FIG. 1, this may be an N-type substrate. Further, in the embodiment, the P well having a low concentration is formed in the peripheral circuit portion B by using the impurity of the opposite conductivity type. However, for example, the P well having a high concentration can be formed in the cell portion A by using the impurity of the same conductivity type. . In the embodiment, the first N well is formed in the first P well to form the second P well whose concentration is lower than that of the first P well. However, naturally, the concentration is higher than that of the first P well. Dark first
Forming an N-well in the first P-well
It is also possible to form a thin N well and a dark N well.

[Effects of the Invention] According to the present invention, it is possible to form various well regions very easily, and as a result, it is possible to use wells suitable for each element. This allows
The bias voltage applied to each well can be made different to form a P-type or N-channel type transistor having various threshold voltages or ON resistances, and a circuit using these transistors can be formed in a chip. Is obtained. In dynamic RA or the like, a memory cell can be placed in a well having a high concentration and a peripheral circuit portion can be placed in a well having a low concentration, so that performance and characteristics can be significantly improved.

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram of an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional DRAM. 101 …… P-type substrate, 102,102 ′ …… Pwell 103 …… Resist, 105 …… Thin Pwell, 106 …… Nwell, 107 …… Dense Pwell, 108 …… Capacitor insulating film, 109 …… Capacitor electrode , 110, 115 …… N ⁺ diffusion layer, 111, 113, 114 …… Transistor gate electrode, 116 ……
P ⁺ diffusion layer.

Claims (1)

[Claims] 1. A step of forming a first well of a first conductivity type in a semiconductor substrate, and a step of simultaneously introducing a second conductivity type impurity into selected regions of the semiconductor substrate and the first well, respectively. A step of forming second and third wells of the second conductivity type having different surface concentrations in the substrate and the first well, and at least one of each of the second and third wells using the respective wells as a substrate And a step of forming a MOS transistor.