JPH0750808A - Video signal processing circuit - Google Patents

Abstract

PURPOSE:To prevent bits below a decimal point from being rounded off due to an arithmetic result of a coefficient circuit in the video signal processing circuit having a feedback loop including at least a memory and the coefficient circuit and processing a digitized video signal. CONSTITUTION:A feedback loop is formed by memories 23a, 23b and a coefficient circuit 24. Then an N-bit digital video signal fed to an input terminal 20 and a video signal via the coefficient circuit 24 are subtracted by a subtractor circuit 27 and the result of subtraction is fed back to the memories 23a, 23b in which a bit number per sample is selected larger than the N-bits.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has at least a memory and a coefficient circuit such as an emphasis circuit for pre-emphasis or de-emphasis of a video signal with respect to the frequency of the video signal in the time axis direction and a cyclic noise reduction circuit in a feedback loop. The present invention relates to a video signal processing circuit.

[0002]

2. Description of the Related Art When a video signal is recorded on a recording medium such as a magnetic tape, the high frequency component of the video signal is enhanced (pre-emphasis) in comparison with the low frequency component in order to reduce the influence of noise during recording and reproduction. Is recorded and reproduced, and the high frequency component is attenuated during reproduction (de-emphasis) to improve the SN ratio. 2. Description of the Related Art Conventionally, there is a device that performs pre-emphasis or de-emphasis in the time axis direction of a video signal as a device for improving the SN ratio improving effect. Here, the time-axis direction emphasis of the video signal will be described as temporal emphasis, the time-axis direction pre-emphasis as temporal pre-emphasis, and the time-axis direction de-emphasis as temporal de-emphasis.

FIG. 7 is a diagram showing a schematic block system of a video signal recording / reproducing apparatus using a conventional temporal emphasis circuit. In the figure, the video signal to be recorded which has entered the input terminal 1 is supplied to the temporal pre-emphasis circuit 2, where the high frequency component of the frequency in the time axis direction is relatively increased in level relative to the low frequency component. After that, the signal is supplied to the recording system signal processing circuit 3, where signal processing suitable for recording the video signal, for example, frequency modulation is performed. The video signal taken out from the recording system signal processing circuit 3 is supplied to a magnetic head (neither is shown) via a recording amplifier or the like, and is recorded on the magnetic tape 4 by this.

On the other hand, at the time of reproduction, the recorded video signal of the magnetic tape 4 is reproduced by the magnetic head, and the reproduction system signal processing circuit 5 goes through a reproduction amplifier (not shown) or the like to perform signal processing opposite to the signal processing at the time of recording. Is performed and then supplied to the temporal de-emphasis circuit 6. The temporal de-emphasis circuit 6 is provided to restore the high frequency component of the frequency in the time axis direction, which has been enhanced by the temporal pre-emphasis circuit 2, to its original value, and its output reproduction video signal is taken out from the output terminal 7. .

FIG. 8 is a diagram showing the configuration of a conventional temporal pre-emphasis circuit 2. In the figure, the video signal input to the input terminal 10 of the temporal pre-emphasis circuit 2 is supplied to the subtraction circuits 17, 18 and 19, respectively. The video signal extracted by the subtraction circuit 17 is supplied to the delay circuit 13. The delay circuit 13 has a delay time of 2m field or {(2m + 1) field-0.5H} of the video signal (where m is 0, 1, 2, ...
H indicates one horizontal period). The delayed video signal extracted from the delay circuit 13 is supplied to the subtraction circuit 18, where it is subtracted from the video signal from the input terminal 10. Subtraction circuit 18
The output video signal of 1 is multiplied by the coefficient K1 by the coefficient circuit 14 and then supplied to the subtraction circuit 17, where it is subtracted from the video signal from the input terminal 10 and then fed back to the delay circuit 13. The output video signal of the subtraction circuit 18 is also supplied to the addition circuit 19 through the coefficient circuit 15 which multiplies the coefficient K2. The adder circuit 19 adds the output signal from the coefficient circuit 15 to the input video signal from the input terminal 10, and the output signal is output from the output terminal 16.

In the above configuration, the feedback loop of the subtraction circuit 17, the delay circuit 13, the subtraction circuit 18, and the coefficient circuit 14 extracts the high frequency component of the frequency of the video signal in the time axis direction. By adding the extracted high frequency component to the video signal from the input terminal 10 by the addition circuit 19 via the coefficient circuit 15, the high frequency component of the frequency of the video signal in the time axis direction is output at the addition circuit 19. It is possible to obtain a video signal provided with a pre-emphasis characteristic (temporal pre-emphasis characteristic) whose level is relatively enhanced as compared with the low frequency component.

FIG. 9 is a diagram showing the configuration of a conventional temporal de-emphasis circuit 6. In the figure, a reproduction video signal converted into the original signal form enters the input terminal 20 of the temporal de-emphasis circuit 6. However,
The reproduced video signal is given the temporal pre-emphasis characteristic. This reproduced video signal is subtracted from the subtraction circuit 27.
Is supplied to the delay circuit 23 through the subtraction circuit 2
It is also supplied to 8,29. The delay circuit 23 is set to the same delay time as the delay circuit 13 shown in FIG. 8, and the delayed reproduction video signal is supplied to the subtraction circuit 28, where it is subtracted from the reproduction video signal from the input terminal 20. . The output video signal of the subtraction circuit 28 is multiplied by the coefficient N1 in the coefficient circuit 24.
Is supplied to the subtraction circuit 27, where it is subtracted from the reproduced video signal from the input terminal 20 and then fed back to the delay circuit 23 again. The output video signal of the subtraction circuit 28 has a coefficient N.
It is also supplied to the subtraction circuit 29 via the coefficient circuit 25 that multiplies by 2. The output signal of the subtraction circuit 29 is output to the output terminal 26.

In the above configuration, the feedback loop of the subtraction circuit 27, the delay circuit 23, the subtraction circuit, and the coefficient circuit 24 extracts the high frequency component of the frequency of the video signal in the time axis direction. By subtracting the extracted high frequency component from the video signal from the input terminal 20 by the subtraction circuit 29 via the coefficient circuit 25, the high frequency component of the frequency of the video signal in the time axis direction is output at the subtraction circuit 29. It is possible to obtain a video signal provided with a de-emphasis characteristic (temporal de-emphasis characteristic) in which the level is relatively attenuated compared to the low frequency component.

In FIGS. 8 and 9, for example, the coefficient K1 =
2.11, K2 = 0.422, N1 = 0.566, N2 =
When set to 0.679, the temporal pre-emphasis characteristic and the temporal de-emphasis characteristic become opposite characteristics (that is, the product of transfer functions is 1), and the characteristics are complementary to each other. That is, in FIG. 7, the temporal pre-emphasis circuit 2
The transfer function from the input to the output of the temporal de-emphasis circuit 6 matches the transfer function when the temporal pre-emphasis circuit 2 and the temporal de-emphasis circuit 6 cancel each other and there is no temporal emphasis. Therefore, the original waveform of the video signal recorded / reproduced by the video signal recording / reproducing apparatus such as the VTR is restored. Further, since the temporal de-emphasis circuit 6 operates in the same manner as the cyclic noise reduction circuit with the values of the coefficients N1 and N2, it has the effect of reducing the noise of the video signal reproduced from the magnetic recording medium. There is.

FIG. 10 shows how the temporal pre-emphasis circuit 2 and temporal de-emphasis circuit 6 described above perform temporal emphasis operations on a magnetic tape.

For example, when a video signal is recorded by a VTR, it is recorded on the magnetic tape 4 in the order of frames as shown in FIG. In the processing of the temporal pre-emphasis circuit 2, the subtraction circuit 17 and the delay circuit 1
3. Due to the presence of the feedback loop formed by the subtraction circuit 18 and the coefficient circuit 14, the frame being processed, which is input to the temporal pre-emphasis circuit 2, is cyclically multiplied by a predetermined coefficient and cyclically multiplied by a predetermined coefficient. It For example, the frame Pn shown in FIG. 10 includes information on a plurality of frames before Pn-1.

When the magnetic tape recorded as described above is reproduced, it is reproduced in the order of the passage of time during recording and subjected to temporal de-emphasis processing. Therefore, for example, when performing temporal de-emphasis on the frame Pn, information before the frame Pn-1 has already been read into the delay circuit 23 of the temporal de-emphasis circuit 6, and the temporal de-emphasis complementary to the characteristics of the temporal pre-emphasis circuit 2 is obtained. Emphasis processing can be performed.

[0013]

The delay circuit 13 shown in FIG. 8 or the delay circuit 13 shown in FIG. 9 used for the temporal emphasis described above.
The delay circuit 23 shown in FIG. 2 has a delay time of, for example, 2m field or {(2m + 1) field −0.5H} of the video signal (where m is 0, 1, 2, ..., And H is 1).
(Indicating a horizontal period) is required, and thus a digital memory is usually used. Therefore, the temporal pre-emphasis circuit 2 or the temporal de-emphasis circuit 6 is input with a video signal converted into a digital signal by an A / D converter (not shown). And the temporal pre-emphasis circuit 2 or the temporal de-emphasis circuit 6
The output signal digitally processed by
It is converted into the form of an analog signal by the A converter.

In the digital memory used as the delay circuit 13 or 23, sampling data obtained by digitizing a luminance signal (hereinafter also referred to as a Y signal) in accordance with the clock shown in FIG. 11A is sequentially provided as shown in FIG. Written. Further, in the case of a temporal emphasis circuit (not shown) for a color signal (hereinafter also referred to as a C signal) which is in a side-by-side relationship with the temporal emphasis circuit for the Y signal, the digital memory used as the delay circuit has the same structure. As shown in FIG. 6C, the C signal sampled at the sampling frequency of 1/3 of the Y signal is sequentially written. In the case where the digital memory for the C signal has the same configuration as the digital memory of the delay circuit 13 or 23, the C signal data may be written in two addresses.

In the temporal de-emphasis circuit 6 shown in FIG. 9, the number of bits of the digitized reproduced video signal supplied to the input terminal 20 is 8 bits, and the number of bits per sample of the memory constituting the delay circuit 23 is set. Is also 8 bits. In this case, as shown in FIG. 12C, for example, for the sample Y0 of the Y signal data, 8-bit data of Y01 to Y08 is input / output to / from the digital memory. Although not shown, the same applies to the C signal. In such a case, the feedback coefficient, that is, the calculation result by the coefficient N1 (for example, N1 = 0.566) of the coefficient circuit 24 is supplied to the delay circuit 23 through the subtraction circuit 27, but the calculation result includes data below the decimal point 9 Even if the data has more bits, the number of bits per sample in the delay circuit 23 is 8 bits, so that the data after the decimal point is discarded at least by the delay circuit 23. The output signal obtained by subtracting the output of the delay circuit 23 from the reproduced video signal by the subtraction circuit 28 is a signal that is a high frequency component in the time axis direction of the reproduced video signal and that also includes a noise component included in the reproduced video signal. . Therefore, the level of noise subtracted from the reproduced video signal by the subtractor 29 is reduced by the amount corresponding to the data below the decimal point truncated by the delay circuit 23, and the noise reduction effect of the temporal de-emphasis circuit 6 is reduced. There was a problem that it decreased.

[0016]

In view of the above-mentioned problems, the present invention provides a video signal processing circuit having a feedback loop including at least a memory and a coefficient circuit to which a video signal digitized into N bits per sample is input. The memory is configured to write at least the video signal fed back through the coefficient circuit as a video signal having a number of bits per sample of more than N bits. It is a thing.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a first embodiment of the video signal processing circuit of the present invention will be described with reference to FIGS. 1 is a block diagram of the configuration of a first embodiment of a video signal processing circuit of the present invention, and FIG. 2 is a diagram for explaining the operation of a memory in the first embodiment. The same components as those described above are designated by the same reference numerals, and the description thereof will be omitted.

The video signal processing circuit of FIG. 1 constitutes a temporal de-emphasis circuit. In the configuration of the temporal de-emphasis circuit 6 shown in FIG. 9 described above, instead of the delay circuit 23, memories 23a and 23b which will be described later are provided. It is equivalent to the one used. In this temporal de-emphasis circuit, 23a and 23b are memories, and the memory 23a is a memory in which the number of bits per sample is the same as the number of bits of the reproduced video signal input to the input terminal 20, for example, 8 bits per sample. Is a memory having. Reference numeral 23b is, for example, a memory of 2 bits per sample, which is controlled similarly to the memory 23a. And the memories 23a and 23b are 1 per sample
It constitutes a 0-bit memory.

The 8-bit data of the reproduced video signal input to the input terminal 20 is subjected to the coefficient circuit 24 by the subtraction circuit 27.
Is calculated with 10-bit data which is the output of. The upper 8 bits of the output of the coefficient circuit 24 are data indicating the integer part of the value obtained by multiplying the output of the subtraction circuit 28 by the coefficient N1 of the coefficient circuit 24, and the lower 2 bits are the data below the decimal point. It represents. Therefore, the data output from the subtraction circuit 27 is also 10-bit data. This is written in the memories 23a and 23b, delayed for one frame, and output. The memory 23a has an integer part of 8
Bit data is stored in the memory, and the memory 23b stores 2-bit data below the decimal point. The delay circuit 23 in the temporal de-emphasis shown in FIG. 9 shown as a conventional example
Although the memories 23a and 23b are shown separately in order to facilitate the comparison with the above, it is needless to say that they may be constituted by one frame memory.

The 10-bit output from the memories 23a and 23b is subtracted from the reproduced video signal from the input terminal 20 by the subtraction circuit 28 and supplied to the coefficient circuit 24 and the coefficient circuit 25. It is multiplied by the factor N2. The output of the coefficient circuit 25 is 10-bit data, which is subtracted from the reproduced video signal from the input terminal 20 by the subtraction circuit 29, and the higher 8-bit data of this is output as the output of the temporal de-emphasis circuit.
It is taken out from the output terminal 26.

Next, in FIG. 2, FIG. 2A is a clock for writing or reading, and FIG. 2B is a sample (Y0, Y2, ...) Of Y signals stored in the memories 23a and 23b, respectively. FIG. 6C shows integer data (Y01 to Y08, Y11 to Y1) of the sample data.
8, ...), and the same figure (D) shows the data (Y09, Y010, Y19, Y110,
...).

For the C signal, a temporal de-emphasis circuit similar to that shown in FIG. 1 can be provided. FIG. 2E shows a sample (C) of the C signal stored in a memory (not shown) having the same structure as the above-mentioned memories 23a and 23b of the temporal de-emphasis circuit for the C signal.
0), C3, ...), and FIG. 4F shows integer data (C01 to C08, C31 to C38,
...), and the figure (G) shows the data after the decimal point of the sample data (C09, C010, C39, C310, ...).
Is represented.

Now, the video signal recorded on the magnetic tape 4 is reproduced through the temporal pre-emphasis circuit 2 and the recording system signal processing circuit 3 shown in FIG. 7 having a configuration complementary to the above-mentioned temporal de-emphasis circuit. Then, when the de-emphasis processing is performed using the temporal de-emphasis circuit as described above after passing through the reproduction signal processing circuit 5, write data to the memory configuring the temporal de-emphasis circuit and reading from the memory. By increasing the number of bits of data as compared with the conventional temporal de-emphasis circuit (increasing from 8 bits to, for example, 9 bits), the feedback loop of the temporal de-emphasis circuit (subtraction circuit 27, memory 23).
a, 23b, the subtraction circuit 28, and the coefficient circuit 24), the coefficient of the coefficient circuit 24 (for example, N1 = 0.56)
Bits below the decimal point generated by the operation of multiplying by 6) can be written in the memories 23a and 23b without being truncated. By configuring in this way,
The high frequency component of the reproduced video signal supplied from the input terminal 20 in the time axis direction and the noise component generated by the recording / reproduction of the video signal, that is, the output signal of the coefficient circuit 25 is the subtraction circuit 29
The level does not decrease when the input is negative. Since such an output of the coefficient circuit 25 can be subtracted from the reproduced video signal from the input terminal 20, the noise reduction effect of the temporal de-emphasis circuit can be enhanced and the SN ratio improvement degree can be enhanced.

In the above description, the number of bits after the decimal point written in the memory 23b is 2 bits, but
Of course, other numbers of bits, such as 3 bits or more, may be used.

Next, a second embodiment of the video signal processing circuit of the present invention will be described with reference to FIGS. FIG. 3 is a block diagram of the second embodiment of the video signal processing circuit of the present invention, and FIG. 4 is a diagram for explaining the operation of the memory in the second embodiment. 5 and 6 are diagrams showing details of the data processing circuit of the video signal processing circuit, respectively. The same components as those described above are designated by the same reference numerals, and the description thereof will be omitted.

In the description of the video signal processing circuit of the first embodiment described above, the temporal de-emphasis circuit for the Y signal was mainly described, but in the video signal recording / reproducing apparatus such as the VTR, the Y signal and the C signal are used. , The temporal de-emphasis circuit for the C signal is also configured in the same manner. In the case of a normal video signal, the frequency bandwidth of the C signal is narrower than that of the Y signal,
When converted to a baseband signal, the highest frequency of the C signal is lower than that of the Y signal. Therefore, when converting to a digital signal, the sampling frequency of the C signal is set low, and for example, a sampling frequency of 1/3 of the sampling frequency of the Y signal is sufficient.

As described in the conventional example, the digital memory used as the delay circuit 23 of the temporal de-emphasis circuit 6 shown in FIG. 9 has sampling data of the Y signal according to the clock shown in FIG. B)
In the digital memory written as shown in FIG. 3 and used as a delay circuit of the temporal emphasis circuit for C signal, the C signal sampled at the sampling frequency of 1/3 of the Y signal is written in the digital memory as shown in FIG. . The digital memory for the C signal is the delay circuit 13 or 23.
In the case of the same configuration as that of the digital memory of C, the C signal data is written in two addresses.

Therefore, in the second embodiment of the present invention, as shown in FIG.
In the part shown as “empty” in the memory of the C signal in (C),
By storing the data after the decimal point of the Y signal and the C signal, the bit number larger than the bit number of the supplied reproduced video signal is stored in the memory, and the SN of the temporal de-emphasis circuit which is the video signal processing circuit is stored. The ratio improvement effect was enhanced.

As shown in FIG. 3, the video signal processing circuit of the present invention is for a Y signal having an input terminal 20, subtraction circuits 27, 28 and 29, a memory 33a, coefficient circuits 24 and 25, and an output terminal 26. Temporal de-emphasis circuit,
Input terminal 30, subtraction circuits 37, 38, 39, memory 33
C having b, coefficient circuits 34 and 35, and an output terminal 36
Temporal de-emphasis circuit for the signal, Y signal data from the subtraction circuit 27 for storing the Y signal and the data after the decimal point of the C signal in the address not conventionally written as "empty" in the memory 33b for the C signal. And the data processing circuit 41 that sorts the C signal data from the subtraction circuit 37 into integer bits and bits below the decimal point, and the 8-bit data read from the memory 33a and the memory 33b into the 9-bit data of the Y signal. 9 of C signal
It is composed of a data processing circuit 42 for reconstructing bit data.

Next, the operation of the temporal de-emphasis circuit for Y and C signals will be described with reference to FIG. The data of the Y signal output from the subtraction circuit 27 is, for example, 9-bit data as shown in FIGS. 4C and 4D, respectively. Integer data in this (Y01 to Y08, Y
11 to Y18, ...) Are separated in the data processing circuit 41 and supplied to the memory 33a. Similarly, the subtraction circuit 3
The data of the C signal output from 7 is shown in FIG.
It is, for example, 9-bit data as shown in (G). Integer data in this (C01-C08, C31-C
38, ...) Is separated in the data processing circuit 41 and supplied to the memory 33b. Then, the data processing circuit 41
In the data of samples Y0 to Y5 of the Y signal shown in FIG. 4B, 6 bits of Y09 to Y59 which are bits after the decimal point shown in FIG. (G) in the figure of the data of the samples C0 and C3 of the C signal shown
Separate the two bits of C09 and C39, which are the bits after the decimal point shown in, and insert these as 8-bit data into the part marked with * between the samples of the C signal shown in FIG. 33b. Therefore, the memory 33a, which is an 8-bit frame memory, stores 8 bits of the integer data of the Y signal shown in FIG. 4C and delays for one frame period. Similarly, the memory 33b stores the C signal shown in FIG. 4F. 8 bits of integer data and 8 bits of 1-bit data after the decimal point of the Y signal and the C signal are sequentially stored and delayed by one frame period.

The data output from the memories 33a and 33b after being delayed by one frame period is used as the data processing circuit 4.
2 and the data processing circuit 41 performs the reverse operation and restores the original 9-bit Y signal data and C signal data respectively, and supplies them to the subtraction circuits 28 and 38, respectively.

FIG. 5 is a detailed block diagram of the data processing circuit 41. In the figure, 50 and 60 are terminals to which the data of the Y signal and the C signal from the subtraction circuits 27 and 37 shown in FIG. 3 are respectively supplied. Of the 9-bit Y signal supplied to the terminal 50, 8 bits of the integer part are supplied to the timing adjustment circuit 51, and 1 bit after the decimal point of the 9th bit is supplied to the delay elements (DL) 53 to 58. The DLs 53 to 58 have different delay times, so that the serially supplied 9th bit data (Y09 to Y59) is converted into parallel data.
The delay time of each DL 53-58 is set.

Similarly, 9-bit C supplied to the terminal 60
8 bits of the integer part of the signal are supplied to the timing adjustment circuit 61, and the 9th bit after the decimal point is supplied to the DLs 63 and 64. DL 63, 64 are the 9th bit data (C09, C3) supplied serially.
9) so that it is converted into parallel, and the above-mentioned DL5
The delay time is set so that the timing also matches the 6 bits (Y09 to Y69) below the decimal point of the Y signal which is the output of 3 to 58.

Bits below the decimal point of the Y signal and the C signal output from the DLs 53 to 58, 63, and 64 are supplied to the selector 66. On the other hand, the data of the integer part of the C signal output from the timing adjusting circuit 61 is also supplied to the selector 66, and these are selected and supplied to the memory 33b shown in FIG. The data of the integer part of the Y signal output from the timing adjustment circuit 51 is supplied to the memory 33a shown in FIG. Here, Y for the clock (illustrated in FIG. 4A)
The delay times of the timing adjustment circuits 51 and 61 are set so that the timing relationship between the signal integer part, the C signal integer part, and the data after the decimal point becomes the relationship shown in FIGS. 4 (C) and 4 (F). There is.

Next, FIG. 6 is a detailed block diagram of the data processing circuit 42. The outputs of the memories 33a and 33b shown in FIG. 3 are supplied to the terminals 70 and 80, respectively, and are supplied to the timing adjustment circuits 71 and 81, respectively. The 8-bit data supplied to the terminal 80 is also supplied to the DLs 73 to 78, 83, and 84, respectively. The outputs of DL73 to 78 are set by the selector 79.
Only the bits after the decimal point of the Y signal inserted between the C signals are sequentially selected for each sample, and the timing adjustment circuit 7
The corresponding subtraction circuit 2 shown in FIG.
8 are supplied. On the other hand, for the outputs of the DLs 83 and 84, only the bits after the decimal point of the C signal inserted between the C signals are sequentially selected for each sample by the selector 89, and the corresponding 8-bit C output from the timing adjustment circuit 81 is output.
As a 9-bit data together with the signal, the terminal 82 is connected to
Is supplied to the subtraction circuit 38 shown in FIG.

In this way, the data processing circuit 42 inserts the data after the decimal point (Y09 to Y59, shown in FIG. 4F) inserted between C0 and C3 of the C signal shown in FIG. 4E.
C09, C39) are rearranged so as to match the integer part of the Y signal and the C signal corresponding to each sample, as shown in FIGS. The signal is restored to the C signal and output to the subtraction circuits 28 and 38 shown in FIG. 3, respectively. Therefore, the second shown in FIG.
In the embodiment, the bit after the decimal point of the video signal is written in the empty address portion of the memory 33b of the temporal de-emphasis circuit for the C signal so that the input video signal of the input video signal is written in the memory forming the feedback loop. It is possible to write Y signals and C signals having more bits than the number of bits. As a result, the high-frequency component of the input playback video signal in the time axis direction and the noise component generated by recording / playback of the video signal do not decrease, and can be subtracted from the input video signal, so that the temporal component is simple and simple. The noise reduction effect of the de-emphasis circuit can be increased,
The degree of improvement in the SN ratio can be increased.

In the above-described first and second embodiments of the present invention, the temporal de-emphasis circuit has been described, but the temporal pre-emphasis circuit having a characteristic complementary to the temporal de-emphasis circuit is also the same. Can be applied. For example, the temporal pre-emphasis circuit can be configured by using the subtraction circuit 29 or the subtraction circuit 39 as an addition circuit and changing the coefficients of the coefficient circuits 24 and 25. Furthermore, it is applied not only to the emphasis circuit but also to a video signal processing circuit that has at least a memory and a coefficient circuit in the feedback loop such as a cyclic noise reduction circuit, and the bits after the decimal point of the video signal to be fed back are not truncated. The amount can be set accurately, and accurate video signal processing can be performed.

[0038]

As described above, according to the video signal processing circuit of the present invention, the video signal digitized into N bits per sample is input, and the video signal has a feedback loop including at least a memory and a coefficient circuit. In the processing circuit, the memory writes at least the video signal fed back through the coefficient circuit as a video signal having a bit number per sample larger than N bits.
Since the bits after the decimal point of the video signal fed back by the feedback loop which has been truncated as data larger than the bits are not truncated, the feedback amount can be set accurately and the video signal can be processed accurately.

Particularly when the video signal processing circuit is a temporal de-emphasis circuit or a cyclic noise reduction circuit,
Since the levels of high frequency components and noise components extracted by the feedback loop do not decrease, the noise reduction effect can be enhanced. Further, in the temporal pre-emphasis circuit used complementarily to such a temporal de-emphasis circuit, it is possible to reduce the calculation error with the temporal de-emphasis circuit.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a first embodiment of a video signal processing circuit of the present invention.

FIG. 2 is a diagram for explaining the operation of the memory in the first embodiment.

FIG. 3 is a block configuration diagram of a second embodiment of a video signal processing circuit of the present invention.

FIG. 4 is a diagram for explaining the operation of the memory according to the second embodiment.

5 is a diagram showing details of a data processing circuit 41 of the video signal processing circuit shown in FIG.

6 is a diagram showing details of a data processing circuit of the video signal processing circuit shown in FIG.

FIG. 7 is a diagram showing a schematic block system of a video signal recording / reproducing apparatus in which a conventional temporal emphasis circuit is used.

FIG. 8 is a block diagram of a conventional temporal pre-emphasis circuit.

FIG. 9 is a block diagram of a conventional temporal de-emphasis circuit.

FIG. 10 is a diagram for explaining how recording is performed on a magnetic tape.

FIG. 11 is a diagram for explaining the operation of the conventional temporal de-emphasis circuit.

FIG. 12 is a diagram for explaining the operation of the memory of the conventional temporal de-emphasis circuit.

[Explanation of symbols]

23a, 23b, 33a, 33b Memory 27, 28, 29, 37, 38, 39 Subtraction circuit 24, 25, 34, 35 Coefficient circuit 41, 42 Data processing circuit 51, 61, 71, 81 Timing adjustment circuit 53-58, 63, 64, 73 to 78, 83, 84 Delay element 66, 79, 89 Selector

Claims (1)

[Claims] 1. A video signal processing circuit having a feedback loop including at least a N-bit digitized video signal per sample and including at least a memory and a coefficient circuit, wherein the memory feeds back at least through the coefficient circuit. A video signal processing circuit configured to write a video signal as a video signal in which the number of bits per sample is greater than N bits.