JPH0748299B2 - Semiconductor memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device.
The present invention relates to a technology which is particularly effective when used in a dual port memory for image processing having both a random input / output function and a serial input / output function.

[Conventional technology]

The image frame buffer memory used for displaying characters or figures on the screen of a CRT (cathode ray tube) is described in, for example, Nikkei McGraw-Hill, March 1986.
It is described on pages 243-264 of “Nikkei Electronics” dated 24th of March.

The dual port memory as described above has a random access port for inputting / outputting stored data in units of 1 bit or several bits, and a serial access for inputting / outputting in units of word lines, that is, rows of a memory array. Cereal·
An access port is provided. Also, this random
The access port has a so-called arithmetic write function which performs arithmetic processing on write data input from the outside and storage data read in advance from a memory cell at a specified address and then writes the data to the memory cell. Therefore, the random access port is provided with an arithmetic logic unit for performing various operations and a function control circuit for controlling the arithmetic mode.

On the other hand, the operation code FC1 for designating the operation mode of the operation logic unit is, as shown in FIG. 4, a row address strobe signal ▲ ▼ and a column address strobe signal ▲ which are externally supplied as control signals.
In a specific combination of ▼ and write enable signal ▲ ▼, for example, 4-bit address signal lines A0 to
Supplied via A3. That is, the column address strobe signal ▲ ▼ is changed before the row address strobe signal ▲ ▼ is changed from the high level to the low level.
By setting both ▼ and write enable signal ▲ ▼ to the low level, the timing signal φfw is formed, and at this time, the 4-bit operation code FC1 supplied via the address signal lines A0 to A3 is the random access port. It is taken into the operation code registers (fc1 to fc4) of. The row address strobe signal ▲
By setting the falling timing of ▼, column address strobe signal ▲ ▼ and write enable signal ▲ ▼ to a specific combination that is not in the normal operation mode, the number of external terminals is increased without providing a special control signal line. Instead, the dual port memory can be set to the operation mode for setting the arithmetic mode.

[Problems to be solved by the invention]

However, when such a method is adopted, the number of combinations of control signals is limited, and, for example, an operation code read operation mode for reading the operation code set in the operation code register is provided. -It will prevent the memory from becoming multifunctional. Also, the microcomputer that controls the dual port memory must simultaneously perform the control for setting the mode and the control for outputting the operation code within one start-up cycle. In some cases, the input timing condition as a dual port memory may not be satisfied.

An object of the present invention is to provide a semiconductor memory device such as a dual port memory which has been made multifunctional without adding an external terminal for a control signal.

The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

The outline of a typical one of the embodiments disclosed in the present application will be briefly described as follows. That is,
By setting a predetermined combination of control signals supplied from the outside, one operation mode of the semiconductor memory device is executed by the start cycle and a plurality of start cycles that follow.

[Action]

According to the above means, the semiconductor memory device can be made multi-functional without adding an external terminal by a plurality of combinations of the control signals in a plurality of consecutive start-up cycles, and the latter stage of the plurality of start-up cycles can be achieved. By inputting the function code or the like in the startup cycle, the processing speed of the main device can be given a margin.

〔Example〕

FIG. 2 shows a dual port type to which the present invention is applied.
A block diagram of one embodiment of a memory is shown. Although not particularly limited, each circuit block shown in the figure is formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

The dual port memory of this embodiment has a random access port which is basically constructed by a dynamic RAM and is accessed in 4-bit units, and a serial access port which performs serial input / output operation of stored data in word line units. A port is provided. This allows the dual port memory to simultaneously access the random access port while performing a series of serial I / O operations. The random input / output circuit RIO included in the random access port is provided with an arithmetic logic unit ALU for performing a raster operation and the like, and a function control circuit FC for controlling this arithmetic logic unit ALU. The serial access port is provided with a serial input / output circuit SIO, and storage data corresponding to four memory arrays are normally input / output serially via four serial input / output terminals SIO1 to SIO3. Further, in a specific operation mode, read data output from the four memory arrays is transferred to the serial input / output terminal SIO1.
It can also be used as a memory of a so-called x1 bit configuration which alternately outputs via.

The dual port memory uses an external device to output a row address strobe signal ▲ ▼ and a column address strobe signal ▲ used in a normal dynamic RAM.
In addition to the control signals such as ▼ and the write enable signal ▲ ▼, the data transfer control signal ▲ ▼ / ▲ ▼ used for controlling the data transfer between the random access port and the serial access port, and the serial access A serial output control signal ▲ ▼ used for input / output switching control of the port and a serial clock signal SC used as a synchronization signal during serial input / output are input.

Although not particularly limited, the random access port of the dual port memory of this embodiment is provided with four memory arrays M-ARY1 to M-ARY4, and the sense amplifiers SA1 to SA1 to M4 corresponding to the respective memory arrays. SA4 and column switches CSW1 to CSW4 are provided. In addition, the memory array M
A column address decoder RCD for random access ports and a row address decoder RD are provided commonly to -ARY1 to M-ARY4. A plurality of these address decoders may be provided depending on the arrangement of the memory array on the semiconductor substrate. FIG. 2 shows the memory array M-ARY1.
And its peripheral circuits are shown as representatives.

In FIG. 2, the memory array M-ARY1 has m + 1 word lines W0 to Wm arranged in the vertical direction in the same figure and n + 1 sets of complementary data lines D0.
.About.Dn.multidot..quadrature. And (m + 1) .times. (N + 1) memory cells arranged at the intersections of these word lines and complementary data lines.

Each word line is connected to the row address decoder RD and is connected to X
One word line designated by the address signals AX0 to AXi is selected and designated.

The row address decoder RD is a row address buffer RADB.
Complementary internal address signals a x0 to a xi (where, for example, an internal address signal ax0 in phase with the externally supplied X address signal AX0 and an internal address signal in opposite phase ▲
Together with ▼, it is expressed as a complementary internal address signal a x0. The same shall apply hereinafter) are decoded, and X address signals AX0 to A
Selects one word line specified by Xi and puts it in the high-level selected state. The operation of selecting the word line by the row address decoder RD is performed according to the word line selection timing signal φx supplied from the timing control circuit TC.

The row address buffer RADB is an address multiplexer
It receives a row address signal supplied from MAX, forms complementary internal address signals a x0 to a xi, and supplies it to a row address decoder RD. In the dynamic RAM of this embodiment, the X address signal AX0 for designating the row address is used.
.About.AXi and Y address signals AY0 to AYi for designating a column address adopt a so-called address multiplexer system in which they are time-divisionally supplied through the same external terminals A0 to Ai.

Therefore, in the normal operation mode of the dual port memory, the X address signals AX0 to AXi and the column address strobe signal ▲ ▼ are synchronized with the fall of the row address strobe signal ▲ ▼ supplied as an external control signal. The Y address signals AY0 to AYi are supplied to the external terminals A0 to Ai, respectively, in synchronization with the falling edge of. Further, the dynamic RAM of this embodiment is provided with an automatic refresh mode for reading / rewriting the stored data of the memory cell within a predetermined cycle,
A refresh address counter REFC for designating a word line to be refreshed in this automatic refresh mode is provided.

The address multiplexer AMX is a timing control circuit TC
In the normal memory access mode in which the timing signal φref supplied from
~ X address signal supplied from external device via Ai
In the automatic refresh mode in which AX0 to AXi are selected and the timing signal φref is set to the high level, the refresh address signals cx0 to cxi output from the refresh address counter REFC are selected.

As described above, since the X address signals AX0 to AXi are supplied to the external terminals A0 to Ai in synchronization with the fall of the row address strobe signal ▲ ▼, the row address buffer RA
The row address signal is fetched by the DB in the timing control circuit TC with the row address strobe signal ▲
Timing signal φ formed by detecting the falling edge of ▼
Done according to ar.

On the other hand, the complementary data line D0 of the memory array M-ARY1
On the other hand, ▼ to Dn and ▲ ▼ are coupled to the corresponding switch MOSFETs of the column switch CSW1 and, through these switch MOSFETs, the complementary common data line C D1 (where the complementary common data line is The non-inverted signal line CD1 and the inverted signal line {circle around (1)} that are formed are collectively represented as a complementary common data line C D0.

The column switch CSW1 is composed of n + 1 pairs of switch MOSFETs respectively coupled to the corresponding complementary data lines. The other terminals of these switch MOSFETs are commonly coupled to the non-inverted signal line CD1 or the inverted signal line {circle around (1)} forming the complementary common data line. Thus, the column switch CSW1 is selectively connects the complementary data D0 · ▲ ▼ ~Dn · ▲ ▼ the common complementary data C D1. The gates of the two switch MOSFETs of each pair forming the column switch CSW1 are commonly connected to each other, and the data line selection signal formed by the column address decoder RCD for the random access port is supplied.

Column address decoder for random access port
The CRD decodes the complementary internal address signals a y0 to a yi supplied from the column address buffer CADB, forms the data line selection signal according to the data line selection timing signal φyr supplied from the timing control circuit TC, and Supply to switches CSW1 to CSW4.

The column address buffer CADB is the timing control circuit TC
In accordance with the timing signal φac formed by detecting the falling edge of the column address strobe signal ▲ ▼, the Y address signals AY0 to AYi supplied through the external terminals A0 to Ai are input and held, and the complementary internal address is stored. The signals a y0 to a yi are formed and supplied to the random access port column address decoder RCD.

Complementary data line D0 of memory array M-ARY1.
On the other side, ▲ ▼ is coupled to the corresponding unit circuit of the sense amplifier SA1 and further to the corresponding unit circuit of the data register DR1 of the serial access port.

Each unit circuit of the sense amplifier SA0 has as its basic configuration a latch composed of two CMOS inverter circuits that are cross-connected. These sense amplifier unit circuits are simultaneously activated at the timing φpa supplied from the timing control circuit TC, amplify the minute read signals of the memory cells output to the corresponding complementary data lines, and set the high level / low level. Is a binary signal.

The complementary common data line C D1 to which the complementary data lines designated by the Y address signals AY0 to AYi are selectively connected is coupled to the random access port input / output circuit RIO.
Complementary common data lines C D2 to C D4 provided corresponding to the memory arrays M-ARY2 to M-ARY4 are similarly coupled to the random access port input / output circuit RIO.

The random input / output circuit RIO is, as described later, a data buffer DB that inputs and outputs data and a dual port
An arithmetic logic unit ALU, which performs various arithmetic operations on input write data and stored data in an arithmetic write cycle of a memory, is its main constituent element. Random input / output circuit R
The IO data buffer DB is set to an operating state by the timing signal φrw supplied from the timing control circuit TC in the random access port write operation mode of the dual port memory, and externally connected via the input / output terminals IO1 to IO4. Take in the write data supplied from the device. Further, in the random access port read operation mode of the dual port memory, the operation is activated by the timing signal φrr supplied from the timing control circuit TC, and the read binary signal of the memory cell is further amplified to input / output terminals. It is sent from IO1 to IO4. The arithmetic logic unit ALU of the random input / output circuit RIO is a dual
In the operation write cycle of the port memory, various operation processes are performed between the storage data read from the memory cell at the specified address and the write data supplied from the outside. The arithmetic logic unit ALU is provided with various arithmetic modes for performing raster arithmetic and the like.

The operation mode of the logical operation circuit is selected and designated by the function control circuit FC. The function control circuit FC has external terminals A0 to A3.
An operation code register FCR for holding an operation code supplied via the operation code and an operation code decoder FCD for decoding the operation code and selecting / designating the operation mode of the logical operation circuit.

In the dual port memory of this embodiment, the multi-function is achieved without adding an external terminal, and the microcomputer controlling the dual port memory allows the output processing of the operation code and the like with a time margin. In order to be able to perform, a double cycle mode is provided in which one operation mode is executed in two start cycles including the next start cycle by making a specific combination of control signals. That is, the column address strobe signal ▲ ▼ and the write enable signal ▲
When ▼ is set to the low level prior to the row address strobe signal ▲ ▼, this cycle is a dummy cycle for setting the dual port memory in the double cycle mode, that is, the first cycle. in this case,
The substantial operation of the dual port memory is executed in the second cycle in which the row address strobe signal ▲ ▼ and the column address strobe signal ▲ ▼ temporarily return to the high level and then become the low level again.

Double cycle mode of dual port memory
The operation mode setting cycle for inputting the operation code designating the operation mode of the operation logic unit ALU to the operation code register of the function control circuit FC and the operation code held in the operation code register of the function control circuit FC Is used as an operation code read cycle for In these double cycle modes, the second cycle is executed in a manner similar to the normal operating mode of dual port memory. That is, in the second cycle of the double cycle mode, the row address strobe signal ▲ ▼ is first changed from high level to low bell,
After a slight delay, the column address strobe signal ▲ ▼ is set to low level. If the write enable signal ▲ ▼ is set to the low level at the fall of the column address strobe signal ▲ ▼, the dual
A port / memory operation mode setting cycle is performed, and a 4-bit operation code is supplied through the external terminals A0 to A3 for inputting address signals. If the write enable signal ▲ ▼ remains high level at the falling edge of the column address strobe signal ▲ ▼ in the second cycle, the dual port memory is set to the cycle in which the operation code is read and the operation code register FCR is set. The operation code data fc0 to fc3 held in the data input / output terminals IO1 to IO3 from the data buffer DB of the random input / output circuit RIO.
It is output via IO4. In this case, the random input / output circuit RIO changes the operation code data according to the high level of the timing signal φfr supplied from the timing control circuit TC.
Select fc0 to fc3.

The operation code register FCR of the function control circuit FC is set in the operation mode setting cycle of the dual port memory.
Timing signal φ supplied from timing control circuit TC
According to fw, the operation code supplied via the external terminals A0 to A3 is fetched and the operation code decoder of the function control circuit FC
Send to FCD. The operation code decoder FCD decodes these operation codes and forms operation mode selection signals am0 to am15 for designating the operation mode of the operation logic unit ALU of the random input / output circuit RIO. Although not particularly limited, a specific operation mode selection signal, for example, am3, is used as an internal control signal sp for making the output of the serial input / output circuit SIO, which will be described later, a x1 bit configuration.

The configurations and operations of the random input / output circuit RIO and the function control circuit FC will be described in detail later.

On the other hand, the serial access port of the dual port memory of this embodiment is an n + 1-bit data register provided corresponding to the complementary data line of each memory array.
DR1 to DR4 and data selectors DSL1 to DSL4 and these 4
It is composed of a pointer PNT, a serial access port column address decoder SCD, and a serial input / output circuit SIO, which are commonly provided for two data registers and a data selector. A plurality of pointers PNT and serial access port column address decoders SCD may be provided due to the arrangement of the memory array on the semiconductor substrate.

The data register DR1 includes an n + 1-bit flip-flop provided corresponding to each complementary data line of the memory array M-ARY1. Switch MOSFETs for data transfer are respectively provided between the non-inverted signal lines and the inverted signal lines of the complementary data lines corresponding to the input / output nodes of these flip-flops. These switch MOSFETs are simultaneously turned on by the high level of the timing signal φdt supplied from the timing control circuit TC, and the data register DR
Input / output of storage data is simultaneously performed between each 1 flip-flop and n + 1 memory cells coupled to the selected word line.

The input / output terminal of each bit of the data register DR1 is further coupled to the corresponding switch MOSFET of the data selector DSL1. The data selector DSL1 is the above-mentioned column switch CS
W1 and is configured similarly to, for selectively connecting the bit serial input-output complementary common data line C DS1 data register DR1. Each pair of switch MOSFETs in the data selector DSL1
Are commonly connected to each other, and a corresponding data register selection signal is supplied from the pointer PNT.

The pointer PNT is composed of an n + 1-bit shift register, and the output terminal ps of the last bit thereof is coupled to the input terminal of the first bit thereof. The pointer PNT performs a loop-shaped shift operation in accordance with the shift clock timing signal φc supplied from the timing control circuit TC in the serial input / output mode of the dual port memory. Each bit of the pointer PNT is further coupled to a corresponding output terminal of the column address decoder SCD for serial access port.

Column address decoder for serial access port
The SCD decodes the complementary internal addresses a y0 to a yi supplied from the column address buffer CADB, and logically decodes only the bit of the pointer PNT corresponding to the first bit of serial input / output specified by the Y address signals AY0 to AYi. 1 ".
That is, in the serial input / output mode, the X address signals AX0 to AXi specify the word line, and the Y address signals AY0 to AYi specify the top column address to be serially input / output. Pointer PNT by column address decoder SCD for serial access port
The signal of logic "1" written in the designated bit of
The pointer PNT is shifted in a loop according to the timing signal φc. By shifting the signal of the logic "1", the data selector DSL1 is sequentially supplied with the high-level data register selection signal and the data register DR1.
Each bit of 1 is connected to the serial input-output complementary common data line C DS1 one after another. As a result, the dual port memory of this embodiment can start serial input / output of stored data from any column address.

The serial input / output circuit SIO includes complementary common data lines C DS1 to C DS4 for serial input / output and serial input / output terminals SIO1 to SI.
It includes four main amplifiers provided corresponding to O4, a data input buffer and a data output buffer. The data output buffer of the serial I / O circuit SIO uses the timing signal φsr supplied from the timing control circuit TC in the read data transfer cycle of the dual port memory.
Is the high level and the operating state, the read data is amplified by the output via the corresponding serial input-output complementary common data line C DS1~ C DS4 corresponding main amplifier, the external serial input-output terminal SIO1~SIO4 Output to the device. The data input buffer of the serial input / output circuit SIO is activated by the high level of the timing signal φsw supplied from the timing control circuit TC during the serial data write cycle of the dual port memory, and the corresponding serial input / output Terminal SIO1 to SI
Write data supplied from an external device through O4 is used as a complementary write signal and transmitted to the corresponding serial common I / O complementary common data lines C DS1 to C DS4.

In the dual port memory of this embodiment, the serial output signal of the normal serial input / output circuit SIO is simultaneously output by 4 bits via the four serial input / output terminals SIO1 to SIO4 as described above. However, if a serial memory with a larger storage capacity is required, this dual port memory can be replaced with four memory arrays M-ARY1 to M-ARY4.
It can be used as a so-called x1 bit configuration memory that serially outputs read data output from a single serial input / output terminal. In this case, as described above, one of the operation mode selection signals is the internal control signal s for making the serial input / output circuit SIO have a × 1 bit configuration.
is p.

When the internal control signal sp supplied from the function control circuit FC goes high, the serial input / output circuit SIO outputs read data serially output via the complementary common data lines C DS1 to C DS4 for serial input / output. Serial I / O circuit SI
Select sequentially by the multiplexer provided in O,
For example, it outputs to an external device via the serial input / output terminal SIO1.

The timing control circuit TC has a row address strobe signal ▲ ▼, a column address strobe signal ▲ ▼, a write enable signal ▲ ▼, and a data transfer control signal ▲ ▼ / ▲ ▼ which are externally supplied as control signals.
Also, the above various timing signals are formed by the serial output control signal () and supplied to each circuit. Also,
Timing signal φ for synchronizing the serial I / O operation by the serial clock signal SC supplied from the outside
c is formed and supplied to the pointer PNT and the serial input / output circuit SIO.

As described above, the dual port memory is set to the double cycle mode by the specific combination of the control signals. Therefore, in the timing control circuit TC,
A determination circuit for identifying the double cycle mode is provided. This determination circuit is provided with a logic circuit for identifying a predetermined combination of control signals and a flip-flop DCM (not shown) for designating the double cycle mode, which is set by the output signal of the logic circuit. The output signal of this flip-flop DCM is
It is used as an internal control signal dcm for forming the above timing signals φfw and φfr.

FIG. 1 shows a circuit block diagram of one embodiment of the random input / output circuit RIO and the function control circuit FC in the dual port memory shown in FIG.

In FIG. 1, the data buffer DB of the random input / output circuit RIO is a 4-bit data input register (not shown).
It consists of DIR and data output buffer DOB. The data input / output terminals IO1 to IO4 are the corresponding data input registers DI.
It is coupled to the input terminal of R and to the output terminal of the corresponding data output buffer DOB. The data input register DIR of the data buffer DB is a dual port
In the operation write cycle of the memory, according to the timing signal φrw supplied from the timing control circuit TC,
It takes in and holds the write data supplied via the data input / output terminals IO1 to IO4. Also, the data buffer DB
The data output buffer DOB is operated in accordance with the timing signal φrr supplied from the timing control circuit TC in the random read cycle or the operation code read cycle of the dual port memory, and is read through the data multiplexer DMX. The data or the operation code is output from the input / output terminals IO1 to IO4 to the external main unit. When the timing signal φrr is low level, the output of the data output buffer DOB is in a high impedance state.

Output signal d of data input register DIR of data buffer DB
0 to d3 are supplied to one input terminal of the arithmetic logic unit ALU. To the other input terminal of the arithmetic logic unit ALU,
The output signal of the data latch DL is supplied. The data latch DL holds the storage data m0 to m3 read from the designated memory cell in the operation write cycle. The arithmetic logic unit ALU is provided with various arithmetic modes for performing raster arithmetic and the like. These operation modes are selected by the operation mode selection signals am0 to am15 supplied from the operation code decoder FCD of the function control circuit FC. The arithmetic unit ALU uses the write data d0 to
After the arithmetic processing of d3 and the stored data m0 to m3 read from the memory cell of the designated address, the result is used as a binary write signal and the corresponding complementary common data line C D1.
Via ~ C D4 written in the memory cells which are above specified.

One input terminal of the data multiplexer DMX has a complementary common data line C D1 from a designated memory cell in a random read cycle of the dual port memory.
-The 4-bit storage data read out via C D4 is input. The operation code data fc0 to fc3 held in the operation code register FCR of the function control circuit FC are input to the other input terminal of the data multiplexer DMAX. The data multiplexer DMX selects these read storage data or operation code data according to the timing signal φfr supplied from the timing control circuit TC, and sends them to the data output buffer DOB of the data buffer DB. That is, in the normal random read cycle in which the timing signal φfr is at low level, the complementary common data lines C D1 · C
In the operation code read cycle in which the storage data read via D4 is selected and the timing signal φfr is set to the high level, the operation code data fc0 to fc3 supplied from the operation code register FCR is selected and the data buffer DB of the data buffer DB is selected. Transfer to the data output buffer DOB.

The function control circuit FC is composed of an operation code register FCR and an operation code decoder FCD. Operation code register F
CR is set to the address bus by the high level of the timing signal φfw supplied from the timing control circuit TC in the operation mode setting cycle of the dual port memory.
The operation code supplied via A0 to A3 is fetched and held. The output signals fc0 to fc3 of the operation code register FCR are
Data multiplexer D of the above random input / output circuit RIO
It is supplied to the other input terminal of MX and is also supplied to the operation code decoder FCD of the function control circuit FC. The operation code decoder FCD has 4-bit operation code data fc0 to fc
3 is decoded and 16 types of calculation mode selection signals am0 to am15
To form. Although not particularly limited, am3 of these operation mode selection signals is used as an internal control signal sp for making the output of the serial input / output circuit SIO a so-called x1 bit configuration, and is sent to the serial input / output circuit SIO. Further, the calculation mode selection signal am5 is used for performing the conventional write operation. In this mode, the write data d0 to d3 are sent to the selected memory cell from the complementary common data lines C D1 and C D4 without passing through the arithmetic circuit of the arithmetic logic unit ALU, so that the write operation can be speeded up. Planned.

FIG. 3 is a timing diagram for explaining the double cycle mode of the dual port memory of this embodiment. In the figure, in the double cycle mode, the operation mode setting cycle is shown by a solid line, and the operation code read cycle is shown by a dotted line. These double cycle modes are composed of two cycles, a first cycle Cycle1 and a second cycle Cycle2, which are dummy cycles.

In FIG. 3, the dual port memory is activated by changing the row address strobe signal () from high level to low level. As described above, in the double cycle mode of the dual port memory, this row address strobe signal
Prior to the fall of ▼, the column address strobe signal ▲ ▼ and the write enable signal ▲ ▼ are changed to the low level. Further, although not particularly limited, the data transfer control signal ▲ ▼ / ▲ ▼ and the serial output control signal ▲ ▼ remain at the high level.

In the dual port memory timing control circuit TC, the column address strobe signal ▲
Since the ▼ and the write enable signal ▲ ▼ are at the low level, the flip-flop DCM of the determination circuit is set and the output signal dcm thereof is at the high level. This places the dual port memory in double cycle mode.

Next, the row address strobe signal ▲ ▼, the column address strobe signal ▲ ▼, and the write enable signal ▲ ▼ are once returned to the high level, and then the row address strobe signal ▲ ▼ is changed to the low level again, whereby the second Cycle2 is started. The column address strobe signal ▲ is slightly delayed after the fall of the row address strobe signal ▲ ▼.
▼ is changed to low level. At the trailing edge of the column address strobe signal ▲ ▼, as shown by the solid line in FIG. 3, the write enable signal ▲
When ▼ is set to low level, dual port
The memory has a calculation mode setting cycle. Further, when the write enable signal ▲ ▼ is kept at the high level as shown by the dotted line in FIG. 3 at the time of the fall of the column address strobe signal ▲ ▼, the dual port memory has the operation code read cycle. To be done.

In the operation mode setting cycle of the dual port memory, the external pin A0 for inputting the address signal is input prior to the fall of the column address strobe signal ▲ ▼.
The operation code FC1 is supplied via ~ A3. dual·
In the port memory, the internal control signal dcm is set to high level and the operation mode setting cycle is further identified, so that the timing signal φfw is set to high level and the operation code FC1 supplied from the external terminals A0 to A3 is functionally controlled. It is taken into the operation code register FCR of the circuit FC.

On the other hand, in the case of the operation code read cycle of the dual port memory, in the dual port memory, the internal control signal dcm is set to the high level and the operation code read cycle is further identified, so that the timing signal φfr is set to the high level. To be done. As a result, in the data multiplexer DMX of the random input / output circuit RIO, the operation code FC0 held in the operation code register FCR of the function control circuit FC is selected and sent to the data output buffer DOB of the data buffer DB. The data output buffer DOB outputs the operation code FC0 to the external main device via the data input terminals IO1 to IO4 according to the timing signal φrr which is brought to a high level with a slight delay.

As described above, the dual port memory of this embodiment is set to the double cycle mode by the control signals supplied from the outside in the specific combination, and the operation mode setting cycle or the operation code reading cycle is performed in two cycles. It is executed by one boot cycle. In the first cycle Cycle1, which is a dummy cycle in the double cycle mode, only the double cycle mode is determined, and the actual operation is the subsequent second cycle Cy.
executed in cle2. Therefore, a new function such as an operation code read cycle can be provided without adding an external terminal to the dual port memory. By changing the combination of the control signals in the second cycle Cycle2, various operation modes can be further specified, and the dual port memory can have multiple functions. In addition, by executing a substantial operation such as operation code setting in the second cycle Cycle2, it is possible to allow a processing speed of a microcomputer or the like which controls the dual port memory to have a margin. The timing adjustment of the memory and the microcomputer becomes easy.

When the present invention is applied to a semiconductor memory device such as a dual port memory used as an image processing memory as shown in the above embodiment, the following effects can be obtained. That is, (1) by providing a predetermined combination of control signals supplied from the outside to provide a plurality of cycle modes for executing one operation mode of the semiconductor integrated circuit device by the start cycle and a plurality of subsequent start cycles. Thus, there is an effect that various operation modes of the semiconductor integrated circuit device can be designated by a plurality of combinations of control signals in a plurality of consecutive activation cycles.

(2) According to the above item (1), it is possible to provide the semiconductor integrated circuit device with expandability without increasing the number of external terminals, and it is possible to achieve multi-functionality.

(3) In the multi-cycle mode of the above item (1), by executing a substantial operation such as setting of operation code and other function codes after the second cycle, a main device such as a microcomputer and a dual port The effects of facilitating the timing adjustment with a semiconductor memory device such as a memory, simplifying the peripheral circuits, and providing a margin in the processing speed of the main device are obtained.

(4) In the multiple cycle mode described in (1) above,
By making the cycles after the second cycle the same as the conventional operation mode, it is possible to realize a multi-functional semiconductor memory device without making major changes to the conventional semiconductor memory device such as a dual port memory. The effect of being able to be obtained is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above-mentioned embodiments and can be variously modified without departing from the scope of the invention. Nor. For example, in the dual port memory of this embodiment, a double cycle mode consisting of two start cycles may be provided, and one operation mode may be executed by three or more start cycles. In the dual port memory of this embodiment, the double cycle mode is identified by the time relationship between the row address strobe signal ▲ ▼, the column address strobe signal ▲ ▼ and the write enable signal ▲ ▼. A specific control signal for designating the double cycle mode may be provided, or the double cycle mode may be identified by another combination of the control signals. In the case of the double cycle mode, for example, the row address strobe signal ▲ ▼ is set to low solid (remains low level),
Only the column address strobe signal ▲ ▼ may be repeatedly changed from the high level to the low level. Further, in the operation mode setting cycle, the operation code or the like may be supplied through the data input / output terminals IO1 to IO4, or the random input / output circuit RIO, the function control circuit FC, and the function control circuit FC shown in FIGS. The block configuration of the dual port memory, the combination of control signals, and the like can adopt various embodiments.

In the above description, the invention made by the present inventor is a field of application which is the background of the invention.
Although the case where the invention is applied to the memory has been described, the invention is not limited thereto, and the invention can be applied to, for example, a static RAM and other semiconductor memory devices. The present invention can be applied to a semiconductor memory device controlled by at least a plurality of activation control signals.

〔The invention's effect〕

The following is a brief description of an effect obtained by the representative one of the inventions disclosed in the present application. That is, by providing a control signal supplied from the outside in a predetermined combination, a plurality of cycle modes for executing one operation mode of the semiconductor memory device by its start cycle and a plurality of start cycles subsequent thereto are provided, and thus continuous operation is performed. Various operation modes of the semiconductor memory device can be designated by a plurality of combinations of control signals in a plurality of start-up cycles, and the semiconductor memory device can be made multifunctional without adding external terminals. The timing adjustment between the main device such as a microcomputer and the semiconductor storage device such as a dual port memory becomes easy, and the processing speed of the main device can be afforded.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a random input / output circuit and a function control circuit of a dual port memory to which the present invention is applied, and FIG. 2 is a random input / output circuit and a function control of FIG. FIG. 4 is a block diagram showing an embodiment of a dual port memory including a circuit, FIG. 3 is a timing diagram showing an embodiment of the double cycle mode of the dual port memory of FIG. 2, and FIG. 3 is a timing diagram for explaining the operation of the dual port memory of FIG. RIO: Random input / output circuit, FC: Function control circuit, ALU
…… Arithmetic logic unit, DB …… Data buffer, DL ……
Data latch, DMX ... Data multiplexer, FCR ...
Operation code register, FCD ... Operation code decoder. M-ARY1 …… Memory array, SA1 …… Sense amplifier, CSW
1 …… Column switch, DR1 …… Data register, DSL1…
… Data selector, PNT… Pointer, RCD… Column address decoder for random access port, SCD…
… Column address decoder for serial access port, RD… Row address decoder, CADB… Column address buffer, RADB… Row address buffer, AMX…
... Address multiplexer, SIO ... Serial input / output circuit, TC ... Timing control circuit, REFC ... Refresh address counter.

Claims (2)

[Claims] 1. A judgment circuit for identifying a dummy cycle when a control signal supplied from the outside has a predetermined combination, and an input signal supplied from a predetermined external terminal is normally provided after the dummy cycle. A semiconductor memory device, wherein an operation cycle is input or output as a signal having a meaning different from a cycle. 2. The control signals are a row address strobe signal ▲ ▼ and a column address strobe signal ▲ ▼.
And the write enable signal ▲ ▼, the determination circuit outputs the column address strobe signal ▲ before the row address strobe signal ▲ ▼ is set to the low level.
The ▼ and the write enable signal ▲ ▼ are used to identify that they have been set to the low level, and this identification signal is used to change the input signal supplied through a part of the address terminal or the data terminal in the next operation cycle to the address signal or the data. 5. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is input or output as a predetermined function code having a different meaning from each other.