JPH0744602A - Designing method for semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To shorten designing period by checking a wiring where electromigration occurs without omission at the stage of designing a semiconductor integrated circuit device. CONSTITUTION:In the designing method of a semiconductor integrated circuit device, data of signal wirings composed of plural wiring routes are prepared (101), the signal wirings are arranged in order from an input terminal to an output terminal (102), an approximate calculation is performed for the current value flowing in the wirings for all the signal wirings (103), the calculated current value is compared with a prescribed allowable current value for the signal wirings, the signal wirings having a possibility of generating electromigration are indicated based on this comparison result (104), the wiring widths of the signal wirings are reset to the wiring widths where electromigration is not generated (105), and based on these wiring widths, the patterns of the signal wirings are prepared. Thus, at the stage of designing of the semiconductor integrated circuit device, the wirings where electromigration occurs can be checked without omission and designing period can be shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the design of a semiconductor integrated circuit device, and more particularly to a technique effectively applied to the design of a semiconductor integrated circuit device which needs to have improved electromigration resistance.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device, a well region is formed on a main surface of a semiconductor substrate made of single crystal silicon, and an element isolation insulating film is formed on a non-active region of the well region. A channel stopper region is formed on the main surface of the well region below the element isolation insulating film.

On the element forming region of the well region, M
A semiconductor element such as ISFET is configured. An insulating film is formed on the semiconductor element, and inter-element wiring (signal wiring or the like) is formed via a connection hole formed in the insulating film.

Since the semiconductor integrated circuit device is highly integrated,
The wiring width is decreasing, and the operating frequency tends to increase for speeding up. Therefore, the wiring (especially the signal wiring) has a problem of disconnection due to electromigration.

Conventionally, at the stage of designing a semiconductor integrated circuit device, signal wiring has been designed and prototyped with a margin for its wiring width. At this prototype stage, all signal wirings are designed with the same wiring width.

Then, the prototype semiconductor integrated circuit device is operated, the value of the current flowing through each signal wiring is measured, and the signal wiring in which electromigration may occur is found.

After that, the photomask used for patterning the signal wiring at the time of manufacturing was remade, and the wiring width of the signal wiring which might cause electromigration was designed to be wide so as to prevent the disconnection due to the electromigration of the signal wiring.

[0008]

Conventionally, the signal wiring of a semiconductor integrated circuit device is designed with a margin in its wiring width. After that, a semiconductor integrated circuit device was prototyped, operated, and the current value flowing in each signal wiring was measured to find a signal wiring in which electromigration might occur. However, in this method, the wiring is checked one by one by hand, and the number of steps is enormous, so not only does it take time to design the semiconductor integrated circuit device,
There was a problem of omission of check.

Further, after the semiconductor integrated circuit device is prototyped,
Since the wiring is checked and the photomask used for patterning the signal wiring is remade, there is a problem that it takes a long time to design the semiconductor integrated circuit device.

It is an object of the present invention to provide a technique for checking a wiring in which electromigration occurs without omission in designing a semiconductor integrated circuit device.

Another object of the present invention is to provide a technique for designing a semiconductor integrated circuit device, which can shorten the design period.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0013]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

In a method of designing a semiconductor integrated circuit device,
The following steps (a) to (e) are provided.

(A) preparing data of signal wirings having a plurality of wiring paths, (b) organizing the signal wirings in order from the input end to the output end, and (c) all the signal wirings. In comparison with the step (d), the step of (d) comparing the calculated current value with a predetermined allowable current value for the signal wiring. Based on this, a step of pointing out the signal wiring that may cause electromigration.

In the method of designing a semiconductor integrated circuit device according to claim 1, the step of resetting the wiring width of the signal wiring to a wiring width at which electromigration does not occur, and a pattern of the signal wiring based on the wiring width And creating.

[0017]

According to the above-mentioned means, at the design stage of the semiconductor integrated circuit device, the current value flowing in each of the signal wirings is approximately calculated, and the calculated current value is calculated for each of the signal wirings. Is compared with a predetermined allowable current value to point out the signal wiring that may cause electromigration. That is, it is possible to fully check the signal wiring that may cause electromigration at the design stage.

Further, the wiring width of the signal wiring, which has been pointed out that electromigration may occur, is reset to a wiring width at which electromigration does not occur, and wiring patterns are created based on the respective set wiring widths. As a result, it is not necessary to remake the photomask used for patterning the signal wiring after the trial manufacture of the semiconductor integrated circuit device. As a result, the design period of the semiconductor integrated circuit device can be shortened.

Embodiments of the present invention will be described below with reference to the drawings. In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and repeated description thereof will be omitted.

[0020]

1 is a flow chart showing the procedure of a method for designing a semiconductor integrated circuit device according to the present invention.

As shown in FIG. 1, the method for designing a semiconductor integrated circuit device according to this embodiment is [wiring element input processing 10
1] → [wiring path trace processing 102] → [current value calculation processing 103] → [electromigration occurrence part search processing 104] → [wiring width setting processing 105]. Hereinafter, each processing content will be described in the order of processing.

[Wiring Element Input Processing 101] The semiconductor integrated circuit device is designed by a design computer, and the layout and dimensions of semiconductor elements and wirings are stored as numerical data. In particular, the wiring is treated as a wiring element consisting of a plurality of straight line portions, and the X coordinate, Y coordinate, wiring width, thickness, wiring material, etc. of the end portion of each wiring element are stored in the wiring information file. There is.

As shown in FIG. 2, in the wiring element input processing 101, X at the end point of the wiring element of each signal wiring.
Call the coordinates and Y coordinates from the wiring information file. The coordinates are SX and SY on the input side of the wiring and EX and E on the output side.
Y

[Wiring Route Trace Process 102] In the wiring route trace process 102, the wiring element input process 10 is performed.
Based on the coordinates of the end points of the wiring elements input in 1, the wiring elements are rearranged in the order from the input pin to the output pin.

For example, as shown in FIG. 3, the input pins are rearranged in the order of output pins via H4 → H2 → H3 → H1.

[Current Value Calculation Processing 103] In accordance with the order given to the wiring elements in the wiring route trace processing 102,
The current value flowing through the end points of the wiring element is approximately calculated by the current value calculation formula (Equation 1), and the current distribution of the current flowing over the wiring element is calculated.

[0027]

[Equation 1] current value = wiring capacity × power supply voltage × operating frequency ×
Activation Rate (Equation 1) In (Equation 1), the wiring capacitance is obtained by multiplying the capacitance per unit length of the wiring (wiring capacitance unit price) by the wiring length. The wiring capacity unit price is prepared in advance for each wiring layer and wiring width, as shown in FIG. The wiring width is
The minimum wiring width that can be formed is set to 1 time width, the wiring width that is 3 times the 1 time width is set to 3 times width, and the wiring width that is 5 times is set to 5 times width. The unit of the wiring capacitance is F (farad). For example, AL1
If the wiring width is 100 times the width of one layer, the wiring capacitance is 29p.
It becomes F.

The power supply voltage is a voltage of a power supply for operating the semiconductor integrated circuit device, and its unit is V (volt).

The operating frequency is a frequency when the semiconductor integrated circuit device is operating, and its unit is Hz (hertz).

The activation rate represents the frequency of the current signal flowing through each wiring path, and is input according to the frequency of use of each signal wiring, and the unit is% (percent).

For example, since the input pin is connected to the end point a on the input side of the wiring element H4 shown in FIG. 3, the wiring capacitance of the current value calculation formula becomes the capacitance of the input pin (input pin capacitance), The current value A1 expressed by (Equation 2) flows.

[0032]

## EQU00002 ## Current value A1 = capacity of input pin × power supply voltage × operating frequency × activation rate (Equation 2) Further, at the end point b which is the output side of the wiring element H4 and the input side of the wiring element H2. , Wiring element H
The capacitance between 4 and the input pin becomes the wiring capacitance, and the current value A2 calculated by (Equation 3) flows.

[0033]

## EQU00003 ## Current value A2 = (wiring capacitance of wiring H4 + input pin capacitance) × power supply voltage × operating frequency × activation rate (Equation 3) Further, at the end point c on the output side of the wiring element H2,
The wiring capacitance between the wiring H4 and the wiring H2 and the input pin capacitance become the wiring capacitance, and the current value A3 calculated by (Equation 4) flows.

[0034]

## EQU00004 ## Current value A3 = (wiring capacitance of wiring H4 + wiring H
2 wiring capacitance + input pin capacitance) × power supply voltage × operating frequency × activation rate (Equation 4) In this way, the current value flowing to the end points is calculated for all the wiring elements of the signal wiring.

FIG. 5 is a flow chart for explaining the electromigration occurrence portion search processing 104 and the wiring width setting processing 105.

[Electromigration Occurrence Searching Process 104] As shown in FIG. 5, the allowable current value is calculated based on the wiring layer and the wiring width of the wiring element (50).
1).

The allowable current value is set for each wiring layer and wiring width, as shown in FIG. 6, and is a current value that can be passed through the wiring without causing electromigration.

Then, the current value calculated in the current value calculation process 103 is compared with the allowable current value (502).

If the current value is smaller than the allowable current value, it is determined that the wiring element does not cause electromigration (503).

On the other hand, if the current value is larger than the permissible current value, it is judged that the wiring element is liable to cause electromigration and pointed out (50).
4).

For example, the current values (A1, A2) flowing through the wiring element H4 and the allowable current value are compared with each other by first referring to the current value calculated in the current value calculation process 103 in FIG.
As shown in (a), the current distribution in the wiring element H4 is approximated.

Then, this current distribution is compared with the allowable current value, and if the current value is equal to or less than the allowable current value as shown in FIG. 7B, the wiring element H4 determines that electromigration does not occur. .

On the other hand, as shown in FIG. 7C, when the current value exceeds the permissible current value, when the current value exceeds the permissible current value, electromigration may occur in the wiring element H4. Judge and point out.

[Wiring Width Setting Processing 105] As shown in FIG. 5, electromigration occurring portion searching processing 10 is performed.
With respect to the wiring element which is pointed out that electromigration may occur in (4), the allowable current of all wiring widths of the wiring layer is compared with the current distribution. Then, all wiring widths in which electromigration does not occur are obtained, and the smallest wiring width among them is set as the wiring width of the wiring element (505).

For example, as shown in FIG. 8, the wiring width having an allowable current value larger than the current value flowing in the wiring element is three times wide and five times wide. Therefore, since the minimum wiring width required for this wiring element is triple, the wiring width of this wiring element is set to triple.

Then, the wiring element is set to a wiring width in which electromigration does not occur, and a wiring pattern is created. Then, a photomask is created based on this wiring pattern, and a semiconductor integrated circuit device is prototyped.

As can be seen from the above description, according to the present embodiment, at the designing stage of the semiconductor integrated circuit device, it is checked whether or not there is a risk of electromigration occurring in all signal wirings, and the occurrence of electromigration is checked. Point out wiring elements that may be a concern. In other words, it is possible to check the wiring where electromigration occurs without omission.

The wiring width of the signal wiring, which has been pointed out that electromigration may occur, is set to a wiring width at which electromigration does not occur, and a wiring pattern is created. Then, a photomask is created based on the wiring pattern, and a semiconductor integrated circuit device is prototyped. As a result, it is not necessary to remake the photomask used for patterning the signal wiring after the trial manufacture of the semiconductor integrated circuit device. As a result, the design period of the semiconductor integrated circuit device can be shortened.

The inventions made by the present inventors are as follows.
Although the specific description has been given based on the above-described embodiments, the present invention is not limited to the above-described embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

[0050]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

1. At the designing stage of a semiconductor integrated circuit device, it is possible to check the wiring in which electromigration occurs without omission.

2. The design period of the semiconductor integrated circuit device can be shortened.

[Brief description of drawings]

FIG. 1 is a flowchart showing a procedure of a method for designing a semiconductor integrated circuit device according to the present invention,

FIG. 2 is a diagram for explaining a wiring element input process,

FIG. 3 is a diagram for explaining a wiring route trace process,

FIG. 4 is a diagram showing a wiring capacitance unit price,

FIG. 5 is a flowchart showing an electromigration occurrence part search process and a wiring width setting process;

FIG. 6 is a diagram showing an allowable current value,

FIG. 7 is a diagram illustrating electromigration occurrence part search processing;

FIG. 8 is a diagram illustrating a wiring width setting process.

[Explanation of symbols]

Reference numeral 101 ... Wiring element input processing, 102 ... Wiring path trace processing, 103 ... Current value calculation processing, 104 ... Electromigration occurrence portion search processing, 105 ... Wiring width setting processing.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location 8122-4M H01L 21/82 C (72) Inventor Kazutaka Mori 2326 Imai, Ome, Tokyo Hitachi, Ltd. In-house Device Development Center (72) Inventor Kyoji Yuyama 2326 Imai, Ome City, Tokyo Hitachi Ltd. Device Development Center (72) Inventor Masakatsu Kosaka 1 Horiyamashita, Hadano-shi, Kanagawa Hitachi Computer Engineering Co., Ltd. Within

Claims (2)

[Claims] 1. A method for designing a semiconductor integrated circuit device, comprising the following steps (a) to (e): (A) preparing data of signal wirings consisting of a plurality of wiring paths, (b) organizing the signal wirings in the order from the input end to the output end, (c) wiring for all the signal wirings. Of approximating the value of the current flowing through, (d)
Comparing the calculated current value with a predetermined allowable current value for the signal wiring, and (e) pointing out a signal wiring that may cause electromigration based on the comparison result in step (d). . 2. The method for designing a semiconductor integrated circuit device according to claim 1, wherein the wiring width of the signal wiring is reset to a wiring width at which electromigration does not occur, and a pattern of the signal wiring based on the wiring width. A method of designing a semiconductor integrated circuit device, the method comprising: