JPH0736490B2 - Arbitrary waveform generator - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an arbitrary waveform generator, and more particularly, to high resolution of an output waveform.

<Prior Art> FIG. 4 is a block diagram showing an example of a conventional arbitrary waveform generator. A plurality of bits (for example, 8 bits) of waveform data output from the pattern generator 1 is added to the D / A converter 2 to be converted into an analog signal, and the analog signal is output through the low pass filter 3. ing.

<Problems to be Solved by the Invention> However, the resolution of the output waveform in such a configuration is
Since the resolution of the D / A converter 2 is limited, it is not possible to obtain an output waveform having a resolution higher than that of the D / A converter 2.

The present invention focuses on such a point, and an object thereof is to provide an arbitrary waveform generator which can obtain an output waveform having a resolution higher than that of a D / A converter with a relatively simple configuration. Especially.

<Means for Solving the Problem> An arbitrary waveform generator of the present invention converts waveform data output from a pattern generator into an analog signal by a D / A converter, and outputs this analog signal through a low-pass filter. In the arbitrary waveform generator configured to, the change polarity determining means for determining the change polarity of the waveform data output from the pattern generator, and from the pattern generator according to the determination result of the change polarity determining means Modulation data generating means for outputting modulation data for performing pulse width modulation that monotonically increases or monotonically decreases on the least significant bit data of waveform data to be output, the modulation data output from the modulation data generating means, and the pattern generation. The addition means for adding the waveform data output from the converter and outputting the output data to the D / A converter is provided. To.

<Operation> In the high resolution output mode, the pulse width modulation data corresponding to the change polarity of the waveform data is added to the least significant bit (LSB) of the waveform data output from the pattern generator.

As a result, the resolution of the output waveform is increased by the resolution of pulse width modulation.

<Example> Hereinafter, an example of the present invention is described in detail using a drawing.

FIG. 1 is a block diagram showing an embodiment of the present invention, and the same parts as those in FIG. 4 are designated by the same reference numerals. In the figure, the output data of the pattern generator 1 is applied to one input terminal of the selector 4 and the high resolution block 5
Has been added to. The high resolution block 5 is for subjecting the LSB of the output data of the pattern generator 1 to pulse width modulation. The high-resolution block 5 is output from the pattern generator 1 according to the change polarity determination circuit 6 that determines the change polarity of the waveform data output from the pattern generator 1 and the determination result of the change polarity determination circuit 6. Modulation data generation circuit 7 that outputs modulation data for pulse width modulation that monotonically increases or monotonically decreases the LSB of waveform data
And an adder 8 that adds the modulation data output from the modulation data generation circuit 7 and the waveform data output from the pattern generator 1 and adds the output data to the other input terminal of the selector 4. There is. The selector 4 selects the data to be input to the D / A converter 2 according to the operation mode. In the low resolution output mode similar to the conventional one, the waveform data output from the pattern generator 1 is selected. In the high resolution output mode according to the present invention, the output data of the adder 8 of the high resolution block 5 is transmitted. Such a selector 4 can be omitted when the device is configured as a device dedicated to the high resolution output mode.

The operation of the apparatus thus configured will be described.

FIG. 2 shows that the resolution of a monotonically increasing output waveform is substantially 2
It is operation | movement explanatory drawing at the time of raising a bit.

In this case, the modulated data generator 7 is, as shown in (a) and below, Is used as a unit block, and the modulation data that changes periodically in 16-clock units is output to the adder 8. Here, this series of modulated data is the LSB when divided every 4 clocks.
Is set to increase by 1 bit.
That is, all the LSBs in the first section of 1 to 4 clocks are set to 0, the LSBs in the second section of 5 to 8 clocks are 1 for 5 clocks and 0 for other clocks, and 9 to 12 LSB in the third section of the clock is 9,1
1 clock is 1 and other clocks are set to 0, 13 to 1
The LSB in the fourth section of 6 clocks is set to 0 for only 14 clocks and set to 1 for other clocks. By converting such data into an analog signal by the D / A converter 2 and applying it to the low-pass filter 3, the average value of the analog signal in the first section is 0, and the average value of the analog signal in the second section is 1/4, the average value of the analog signal in the 3rd section is 2/4, the average value of the analog signal in the 4th section is 3/4, which means that it increases monotonically by 1/4 for each section. .

On the other hand, the pattern generator 1 is, as shown in (b) and below, The waveform data updated every 16 clock units is output to the adder 8. Such waveform data is, for example, previously calculated and stored in the pattern generator 1, and sequentially read out according to the clock when the high resolution output mode is selected.

The adder 8 adds the output data of the modulation data generator 7 and the output data of the pattern generator 1 and outputs waveform data as shown in (c) and below.

(D) shows an analog signal converted and output from the D / A converter 2, and (e) shows an output signal of the low-pass filter 3. Further, (f) shows the output data of the pattern generator 1 in an analog manner.

As is apparent from these, when the output data of the pattern generator 1 is added to the D / A converter 2 and converted into an analog signal, it greatly changes with a resolution of one level as 0 → 1 → 2 → ... However, when the output data of the adder 8 is added to the D / A converter 2 and converted into an analog signal, 0 → 1/4 → 2/4 →
As shown in 1 3/4 → 2 →, the output level changes with a resolution of 1/4 level, and an output signal whose level changes with a resolution higher than that of the D / A converter 2 can be obtained. .

Specifically, for example, when the operation in the conventional low resolution output mode is to output a frequency waveform of 100 MHz for two cycles with 8-bit resolution at a clock frequency of 1 GHz, the high resolution output mode of the above embodiment is used. According to this, if the memory areas are the same, a frequency waveform of 100 MHz can be output for 1/4 cycle with a resolution of 10 bits.

FIG. 3 is a block diagram showing another embodiment of the present invention,
An example of a circuit that operates similarly to the operation explanatory view of FIG. 2 is shown. In the figure, an arithmetic control unit (CPU) 9 detects an increase or decrease of 8-bit waveform data corresponding to the output data of the pattern generator 1 of FIG.
1 with lower 2 bits added as B pulse width modulation data
The 0-bit data is output to the memory 10. In particular,
As shown in FIG. 2 (e), four kinds of 2-bit data (00,01,10,11) are added to each waveform data in order to change 1/4 level in four steps, and four data are added. Output. Of the 10-bit waveform data written in the memory 10, the upper 8 bits of data are passed through the latch 11 and shown in FIG.
Is read out by the selector 4 and the adder 14 as the data shown in FIG. On the other hand, the added lower 2-bit data is read by the decoder 12. The decoder 12 decodes the 2-bit lower-order data into a data string of LSB of the modulation data shown in FIG. 2 (a) and outputs it to the shift register 13. That is, "00" is converted into "0000" in the first section, "01" is converted into "1000" in the second section, and "10" is converted into "10" in the third section.
10 "and" 11 "are converted to" 1011 "in the fourth section. The output data of the shift register 13 is added to the adder 14 and the LSB of the 8-bit output data added via the latch 11. As a result, the data shown in Fig. 2 (c) is output from the adder 14. Note that D /
A 1 GHz clock 1 is added as a shift clock of the A converter 2 and the shift register 13, and a 250 MHz clock 2 is added as a load clock of the memory 10 and the shift register 13.

Even in such a configuration, similarly to FIG. 1, a high speed low resolution output and a low speed high resolution output can be selectively obtained.

In the above embodiment, the example in which the level is changed by 1/4 has been described, but the level resolution may be appropriately set according to the application.

Further, when the waveform data decreases, the modulation data may be decreased with a predetermined level resolution.

The pattern generator may output desired pattern data according to a predetermined program, or may store a measured waveform as digital data like a digital oscilloscope.

<Effects of the Invention> As described above, according to the present invention, it is possible to realize an arbitrary waveform generation device having a relatively simple configuration and capable of obtaining an output waveform having a resolution higher than that of the D / A converter.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an operation explanatory diagram of FIG. 1, FIG. 3 is a block diagram showing another embodiment of the present invention, and FIG. 4 is a conventional device. It is a block diagram showing an example. 1 ... Pattern generator, 2 ... D / A converter, 3 ... Low pass filter, 5 ... High resolution block, 6 ... Change polarity discrimination circuit, 7 ... Modulation data generator, 8 ... Adder .

Claims (1)

[Claims] 1. An arbitrary waveform generator configured to convert waveform data output from a pattern generator into an analog signal by a D / A converter and output the analog signal through a low pass filter. A change polarity discriminating means for discriminating the change polarity of the waveform data output from the pattern generator, and a monotonically increasing least significant bit data of the waveform data output from the pattern generator according to the discrimination result of the change polarity discriminating means. Alternatively, a modulation data generating means for outputting modulation data for applying a monotonically decreasing pulse width modulation, and the modulation data output from the modulation data generating means and the waveform data output from the pattern generator are added to output the sum. An arbitrary waveform generating device, comprising: an adding means for outputting data to the D / A converter.