JPH07319841A - Serial control device - Google Patents

Abstract

PURPOSE:To provide a serial control circuit capable of executing high speed real time processing by generating an interruption signal only for a signal required with quick processing. CONSTITUTION:A received data buffer 3 is provided with plural latch circuits, sets up '1' in a status register 2 at each end of latching and informs a CPU 12 of the readable state of received data. A comparator circuit 27 compares the contents of the buffer 3 with those of a comparing data buffer 28, and when both the contents match each other as the result of comparison, a matching signal is outputted. When plural comparing data exist, these data are compared in order of storage at data in the buffer 28. A comparison control circuit 29 controls timing for sequentially outputting the data of the buffer 28 to the circuit 27 and controls the reading of data from the buffer 3 by the CPU 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to communication control for office automation equipment and the like, and more particularly to a central processing unit (C) for copying machines, printers and the like.
The present invention relates to a serial control circuit for performing mutual communication when a plurality of (PU) are used.

When a microcomputer system is constructed using a plurality of CPUs, signals are communicated between the CPUs. FIG. 3 shows an example of a conventional serial control circuit for performing such signal communication between CPUs.

In the figure, 1 is a control logic circuit, 2 is a status register, 3 is a reception data buffer, 4 is a transmission data buffer, 5 is a control word register,
6 is a synchronous character register, 7 is a transmitter (including a transmission buffer), 8 is a receiver (including a reception buffer), 9 is a modem control circuit, 10 is an internal data bus, 1
1 is a status bus.

The function of each circuit block will be described. The control logic circuit 1 sends a control signal to each of the above blocks based on an external signal or an internal status signal to control the operation. The status register 2 is a register that stores status as a serial control circuit. Error status, data buffer 3,
4 states, general purpose input terminal states, the CPU can read the contents of this register at any time. The reception data buffer 3 stores the data received by the receiver 8, and the CPU receives the reception data by reading the contents of this buffer. In the transmission data buffer 4,
The transmission data written by the CPU is stored, and the transmission data written is transferred from the transmission data buffer 4 to the transmission buffer in the transmitter 7 and output from the TxDATA terminal. In the control word register 5, a control word for designating an operation (a mode word, a sync character and a command word following the mode word for setting the synchronous mode) are transferred internally via this register. The sync character register 6 stores one or two sync characters to be written to the control word register 5 after the mode word in the sync mode. If the writing of data is delayed during transmission and the TxEMP state is reached, the synchronization character stored in this register is output from the TxDATA terminal, and the character transmitted during reception is compared with the synchronization character stored in this register. Synchronization is established when the data match. The contents of the transmission data buffer 4 are transferred to the transmitter, converted from parallel to serial, and output from the TXDATA terminal.
A start bit, a stop bit and a parity bit are also added. The receiver 8 converts serial data input from the RxDATA terminal into parallel data and transfers the parallel data to the reception data buffer 3 so that the CPU can read it. The MODEM control circuit 9 controls the inverted CTS signal terminal, the inverted RTS signal terminal, the inverted DSR signal terminal, and the inverted DTR signal terminal of the four MODEM control terminals.

In the figure, D7 to D0 are 8-bit / 3-state bidirectional data buses, RESET is a reset input terminal, CLK is a clock input terminal, CS is a chip select input terminal, RD is a read strobe input terminal,
Inverted WR is a write strobe input terminal, C / inverted D is a control or data input terminal, inverted DSR is a general input terminal, inverted DTR is a general output terminal, inverted RTS is a general output terminal, inverted CTS is a transmission control input terminal, and TxDA
TA is a serial data transmission terminal.

The TxRDY terminal is an output terminal for notifying the CPU that transmission data can be written, and TxRDY terminal.
The xEMP terminal is an output terminal for indicating that both the transmission data buffer 4 and the transmission buffer in the transmitter 7 are empty, the inverted TxCLK terminal is a reference clock input terminal for determining the transmission rate, and the RxDATA terminal is the serial data. RxRDY terminal is an output terminal for indicating that the reception data is ready to be read, SYNC / BRK terminal is an input / output terminal for synchronous detection or break state detection, and RxCLK terminal is a reception rate. It is a reference clock input terminal for determining. The VDD terminal is connected to the positive power supply terminal, the GND terminal is connected to the 0V terminal of the power supply, and nothing is connected to the IC terminal.

Such a serial control circuit generally has two operation modes, which are roughly classified into a synchronous system and a start-stop synchronization system. In the synchronous mode, the bit length of one character, the number of synchronous characters, and the synchronization detection method are specified. In the asynchronous mode, the communication rate, the bit length of one character, and the stop bit length are specified. Based on this, the parallel data written from the CPU is converted to serial data and output from the TxDATA terminal (transmission operation)
Alternatively, the serial data input from the outside is converted into parallel data so that the CPU 12 can read it (reception operation).

[0008]

In the conventional serial control circuit as described above, an interrupt is issued to the CPU for each reception to request the reading of data, and the CPU processes the signal received by the interrupt. . Since a computer system that requires real-time processing requires many types of interrupts, it is common to prioritize interrupt signals. Therefore, an interrupt is used for a received signal that does not require fast processing, which may reduce the real-time processing capability of the CPU. In the worst case, a malfunction may occur in the case of multiple interrupts.

There is also a method of reading the status of the serial control circuit by polling without using an interrupt, transferring the data to the reception data buffer 3, knowing that the reception data can be read, and reading the data. However, this method cannot be used for signals that require real-time processing because the status is checked at a certain time.

In the present invention, attention is paid to such a problem, and an interrupt signal is generated only for a signal that requires fast processing, and a signal that does not require fast processing is read by polling the status and reading the signal. Therefore, it is an object of the present invention to provide a serial control circuit which enables high-speed real-time processing and effectively uses the CPU processing function.

[0011]

In order to achieve the above object, a serial control device according to the present invention performs signal communication between the central processing units in a microcomputer system using a plurality of central processing units (CPU). A serial control circuit for inputting a serial signal, a means for storing the serial signal, a means for storing preset data to be compared with the content of the serial signal, the serial signal and the It is provided with a means for comparing with preset data, and outputs a coincidence signal when the comparison result by the comparing means is the same.

In order to achieve the above-mentioned object, the serial control device according to the present invention is a microcomputer system using a plurality of central processing units, a means for inputting a serial signal, a means for accommodating the serial signal,
A means for accommodating data to be compared with the contents of the serial signal and a means for comparing the serial signal with the data are provided, and a coincidence signal is output when the comparison result by the comparing means is the same. .

The serial control device according to the present invention may be configured to include means for accommodating a plurality of the serial signals.

A serial control device according to the present invention comprises a plurality of the data storing means, and the comparing means stores the signal stored in the storing means of the serial signal and the plurality of data stored in the data storing means. It can be configured to be compared with each individual.

In the serial control device according to the present invention, the means for accommodating the plurality of serial signals compares the stored serial signals with each of the plurality of data stored in the data storage means. be able to.

In the serial control device according to the present invention, the comparison means may output a coincidence signal corresponding to each comparison data when the comparison results are the same.

[0017]

1 is a block diagram of a serial control circuit according to the present invention. In the figure, the same parts as those of the conventional example are designated by common reference numerals and described. The serial control circuit (unit) 20 of this embodiment is controlled by the CPU (microcomputer) 12 and can be used in either the synchronous system or the start-stop synchronization system as described above, but the start-stop synchronization system will be described below. .

In the serial control circuit 20 of this embodiment, the CP
Based on the contents specified by U12, the parallel data written from the CPU 12 is converted into serial data and output (transmission operation) from the TxDATA terminal, or the serial data input from the outside is converted into parallel data, and the CPU 12 Is configured to be read. When the serial control circuit 20 completes the conversion into parallel data and the CPU 12 is ready to read the data, C
An interrupt signal is output to PU12.

The interrupt signal is a data bus buffer 2 which controls the bidirectional data bus by a read signal (RD), a write signal (WR) and a chip select signal (CS).
It is canceled when the CPU 12 finishes reading the data from 1. The serial control circuit 20 also includes a status register 2 indicating the current state,
By reading the status, the 12 can know the state of the reception data buffer 3 and the transmission data buffer 4, and can also perform data transmission and reception.

Next, the function of each block of this circuit will be described. As the buffer, the reception data buffer 3 and the transmission data buffer 4 are provided as in the conventional example. 2 in the figure
A start bit / stop bit detection circuit 2 detects the start bit of the data by detecting the low (L) level of the data output from the buffer 24 at the cycle of the RxCLK signal from the clock driver 23, and detecting the 8 bits of the RxCLK signal.
After counting, the L level is detected again. When the L level is detected also in this detection again, it is determined to be a start bit, a gate signal for generating 8 clocks is output to the shift register clock generation circuit 25, and 8-bit data is output to the shift register circuit 26. A gate signal for reading is output (signal a in the figure). When the stop bit detects a high (H) level at the 9th clock after counting 8 clocks of the data bit, it determines that the stop bit is detected and outputs a latch signal to the reception data buffer 3 (signal b in the figure). Shift register clock generation circuit 2
When the start bit is detected, the reference numeral 5 thereafter outputs the reception clock (RxCLK) to the shift register 26 every 16th frequency division, and the shift register 26 reads the central data of the data bits.

The reception data buffer 3 is provided with a plurality of 8-bit latch circuits (separated by dotted lines in the figure) and shifts the reception data to the next latch circuit for each latch signal (shifts for each byte). ) Has been configured.
Then, each time the latch is completed, "1" is set in the status register to notify the CPU 12 that the received data can be read. The CPU 12 also checks this status flag by polling and reads the data.

The comparison circuit 27 includes a reception data buffer 3
And a comparison data buffer 28 storing a plurality of comparison data
The contents of are compared, and if the compared results match, a match signal is output. The comparison data buffer may be omitted and the contents to be compared may be fixed. This coincidence signal is reset when the data in the reception data buffer 3 is read by the CPU 12. When there are a plurality of comparison data, all the data are compared, but when there is a plurality of comparison data, the comparison data are compared in the order of being stored in the comparison data buffer 28, and the coincidence signals are output in the order of coincidence. The comparison control circuit 29 connected to the comparison data buffer 28 triggers a status register set signal (a signal indicating that the reception data can be read) from the reception data buffer 3 and compares the data of the comparison data buffer 28 with the comparison circuit 2.
It controls the timing of sequential output to 7, and controls the reading of the data in the reception data buffer 3 by the CPU 12. When the data is read by the CPU 12, the reset signal of the coincidence signal is output to the comparison circuit 27.

Reference numeral 2 in the drawing denotes a status register, which indicates the control state of the serial control circuit and can be read by the CPU 12. Reference numeral 30 is a mode word register for setting transmission / reception conditions (mode) of communication.
It is set by U12 via the data bus 10. A command word register 31 controls transmission / reception operations, which is also set by the CPU 12 via the data bus 10.

The data bus buffer 21 controls the bidirectional data bus by the read signal (RD), the write signal (WR), and the chip select signal (CS) as described above. It controls the read / write of the buffer 21, the status register 2, the mode word register 30, and the command word register 31.

The data bus inputs / outputs D7 to D0 are bidirectional data buses, which are connected to the data bus of the CPU 12 and through which data, commands and statuses are transferred. When the chip select signal CS = 0 and RD or WR is “0”, the chip becomes active, and the other state is high impedance (marking). The input to the reset input terminal RESET is the serial control circuit 2
0 is in standby mode. Clock input terminal CLK
The input to the internal control circuit 20 makes the internal timing of the serial control circuit 20. Regarding the input to the chip select input terminal CS, when CS = 0, the serial control circuit 20 is selected, and when CS = 1, it is not selected. Lead terminal RD
RD = 0 when the data or status information is read from the serial control circuit 20. The input to the write strobe terminal WR is set to WR = 0 when writing data or a control word to the serial control circuit 20. Control or data terminal C /
The input to D defines the type of data when accessing the serial control circuit 20, C / D = 1 defines the control word / status, and C / D = 0 defines the character data. The input to the transmission clock terminal TxCLK is a reference clock input for determining the transmission rate, the input to the reception clock terminal RxCLK is a reference clock input for determining the reception rate, and the transmission control input terminal CTS. As for the input to, the transmission is possible when CTS = 0, and the transmission operation is prohibited when CTS = 1. Further, the reception data terminal RxDATA is a terminal for receiving serial data, the transmission data terminal TxDATA is a terminal for transmitting serial data from the transmission shift register 32 connected to the transmission data buffer 4 via the buffer 33, and the reception control output terminal RTS is , If RTS = 0, reception is possible, RT
When S = 1, reception becomes impossible.

[0026]

The serial control device according to the first aspect of the present invention includes means for inputting a serial signal, means for storing the serial signal, means for storing preset data to be compared with the contents of the serial signal, and the serial signal and the signal beforehand. Since a match signal is output when the comparison result is the same with a means to compare with the set data, it is fixed to only a specific signal, but interrupts only for signals that require fast processing. Since signals can be generated, high-speed real-time processing and CPU processing functions can be effectively and optimally used.

A serial control device according to a second aspect of the present invention includes means for inputting a serial signal, means for storing a serial signal, means for storing data to be compared with the contents of the serial signal, and means for comparing the serial signal with the data. Since the coincidence signal is output when the comparison results are the same, the comparison data can be written from the CPU, the type of real-time processed signal can be changed, and real-time processing of a plurality of signals becomes possible. There is an effect that the data to be compared can be freely changed by software.

Since the serial control device according to the third aspect is provided with means for accommodating a plurality of serial signals,
In addition to the common effects described above, there is an effect that it becomes effective when it is desired to process a plurality of signals quickly after they are transmitted or when one status or data is created by a plurality of bytes (characters).

According to a fourth aspect of the present invention, the serial control device comprises a plurality of data storage means, and the comparison means compares the signal stored in the storage means of the serial signal with each of the plurality of data stored in the data storage means. In addition to the common effects described above, interrupts can be generated for multiple signals, external rewriting is possible, real-time processing can be performed for multiple signals, and the type of interrupt signal can be freely selected. Has the effect of becoming.

In the serial controller according to the fifth aspect of the present invention, the means for accommodating a plurality of serial signals compares the plurality of serial signals accommodated with each of the plurality of data accommodated in the data accommodating means. In addition to the common effects described above, it becomes effective when you want to process multiple signals quickly after sending multiple signals or when you create one status or data with multiple bytes (characters). Is generated, rewriting can be performed from the outside, real-time processing can be performed on a plurality of signals, and the type of interrupt signal can be freely selected.

Since the serial control device according to the sixth aspect outputs the coincidence signal corresponding to each comparison data when the comparison result is the same, in addition to the common effect,
When using multiple interrupts, the system can be controlled with priority according to the type of interrupt signal.
This has the effect of maximizing the performance of the PU.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a serial control circuit according to the present invention.

FIG. 2 is a timing diagram in the circuit of FIG.

FIG. 3 is a block diagram showing an example of a conventional serial control circuit.

[Explanation of symbols]

 1 Control Logic Circuit 2 Status Register 3 Receive Data Buffer 4 Transmission Data Buffer 5 Control Word Register 10 Internal Data Bus 20 Serial Control Circuit 12 CPU 21 Data Bus Buffer 22 Start Bit / Stop Bit Detection Circuit 23 Clock Driver 24 Buffer 25 Shift Register Clock Generation circuit 26 Shift register circuit 27 Comparison circuit 28 Comparison data buffer 29 Comparison control circuit 30 Mode word register 31 Command word register 32 Transmission shift register 33 Buffer

Claims (6)

[Claims] 1. In a microcomputer system using a plurality of central processing units (CPUs), a serial control circuit for performing signal communication between the central processing units, means for inputting a serial signal, and the serial signal. And a means for storing preset data for comparing with the contents of the serial signal, and a means for comparing the serial signal with the preset data. A serial control circuit which outputs a coincidence signal in the same case. 2. A microcomputer system using a plurality of central processing units, means for inputting a serial signal, means for accommodating the serial signal, means for accommodating data to be compared with the contents of the serial signal, A means for comparing the serial signal with the above data is provided,
A serial control circuit which outputs a coincidence signal when the comparison results by the comparison means are the same. 3. The serial control circuit according to claim 1, further comprising means for accommodating a plurality of the serial signals. 4. A plurality of the data storage means are provided, and the comparison means compares the signal stored in the storage means of the serial signal with each of the plurality of data stored in the data storage means. 4. The serial control circuit according to claim 1. 5. The serial device according to claim 4, wherein the means for storing the plurality of serial signals compares the plurality of stored serial signals with each of the plurality of data stored in the data storage means. Control circuit. 6. The serial control circuit according to claim 5, wherein the comparison means outputs a coincidence signal corresponding to each comparison data when the comparison results are the same.