JPH0730244A - Bump electrode, and method of forming bump electrode - Google Patents
Bump electrode, and method of forming bump electrodeInfo
- Publication number
- JPH0730244A JPH0730244A JP5196850A JP19685093A JPH0730244A JP H0730244 A JPH0730244 A JP H0730244A JP 5196850 A JP5196850 A JP 5196850A JP 19685093 A JP19685093 A JP 19685093A JP H0730244 A JPH0730244 A JP H0730244A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- bump
- bump electrode
- solder
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims description 23
- 229910000679 solder Inorganic materials 0.000 claims abstract description 39
- 239000000919 ceramic Substances 0.000 claims abstract description 27
- 239000004020 conductor Substances 0.000 claims abstract description 16
- 239000010931 gold Substances 0.000 claims abstract description 14
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052737 gold Inorganic materials 0.000 claims abstract description 13
- 238000007747 plating Methods 0.000 claims abstract description 13
- 238000002844 melting Methods 0.000 claims abstract description 7
- 230000008018 melting Effects 0.000 claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 14
- 238000007598 dipping method Methods 0.000 claims description 4
- 239000000155 melt Substances 0.000 claims description 4
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 2
- 150000001875 compounds Chemical class 0.000 claims description 2
- 229910052731 fluorine Inorganic materials 0.000 claims description 2
- 239000011737 fluorine Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 25
- 239000011248 coating agent Substances 0.000 abstract description 4
- 238000000576 coating method Methods 0.000 abstract description 4
- 238000007796 conventional method Methods 0.000 description 9
- 238000007665 sagging Methods 0.000 description 5
- 239000006071 cream Substances 0.000 description 4
- 230000004907 flux Effects 0.000 description 4
- 239000010408 film Substances 0.000 description 3
- 238000010304 firing Methods 0.000 description 3
- 150000002222 fluorine compounds Chemical class 0.000 description 3
- 238000007639 printing Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- DKPFZGUDAPQIHT-UHFFFAOYSA-N Butyl acetate Natural products CCCCOC(C)=O DKPFZGUDAPQIHT-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- FUZZWVXGSFPDMH-UHFFFAOYSA-N hexanoic acid Chemical compound CCCCCC(O)=O FUZZWVXGSFPDMH-UHFFFAOYSA-N 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 238000003303 reheating Methods 0.000 description 1
- 102220330774 rs150980372 Human genes 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000003756 stirring Methods 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
- H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Wire Bonding (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、セラミック多層配線基
板上に形成するバンプ電極、及び該バンプ電極の形成方
法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bump electrode formed on a ceramic multilayer wiring board and a method for forming the bump electrode.
【0002】[0002]
【従来の技術】従来、セラミック多層配線基板上に形成
するバンプ電極としては、クリームはんだ、及びはんだ
ボールを用いて形成する方法が一般的であった。2. Description of the Related Art Hitherto, as a bump electrode formed on a ceramic multilayer wiring board, a method of forming it by using cream solder or solder ball has been generally used.
【0003】かかるバンプ電極の形成方法は、先ずセラ
ミック多層配線基板上のバンプ電極形成部に導体パター
ンを形成し、該導体パターン上にクリームはんだを印
刷、或いは塗布し、その面上にはんだボールを搭載して
大気中で加熱溶融する方法であった。In such a bump electrode forming method, first, a conductor pattern is formed on a bump electrode forming portion on a ceramic multilayer wiring substrate, cream solder is printed or applied on the conductor pattern, and a solder ball is formed on the surface. It was a method of mounting and heating and melting in the atmosphere.
【0004】ここで、上記方法により形成されたバンプ
電極は、その大部分がはんだで構成されているため、該
バンプ電極の大きさは、上記クリームはんだの印刷或い
は塗布量、及びはんだボールの大きさによってほぼ決定
され、またバンプ電極の形状は、溶融した際のはんだの
表面張力の影響で、概ね図5に示したような球型の一部
形状を呈したものとなっていた。Since most of the bump electrode formed by the above method is composed of solder, the size of the bump electrode depends on the amount of the cream solder printed or applied and the size of the solder ball. The shape of the bump electrode was almost spherical as shown in FIG. 5 due to the surface tension of the solder when melted.
【0005】[0005]
【発明が解決しようとする課題】しかしながら、上述し
た従来の方法で形成されたバンプ電極101を有するセ
ラミック多層配線基板102を、マザーボード103に
実装する際においては、バンプ電極101は上記したよ
うにその大部分がはんだで構成されているため、マザー
ボード103への実装のための再加熱時にその全体が溶
融し、形状を維持することができないため、接合する両
基板間隔を一定に保つことが非常に困難となり、図6に
示したように、両基板が斜めに接合されることによる隣
接したバンプ電極間のショート、或いは両基板電極間の
接続不良等の問題が、発生し易い構造のものであった。However, when the ceramic multilayer wiring substrate 102 having the bump electrodes 101 formed by the above-described conventional method is mounted on the mother board 103, the bump electrodes 101 are formed as described above. Since most of it is composed of solder, the entire body melts at the time of reheating for mounting on the mother board 103, and the shape cannot be maintained. As shown in FIG. 6, the structure is such that problems such as short-circuiting between adjacent bump electrodes due to oblique joining of the two substrates or poor connection between the two substrate electrodes are likely to occur. It was
【0006】また、上述した従来方法により形成された
バンプ電極は、その大きさ及び形状が、上記したように
クリームはんだの印刷或いは塗布量、及びはんだボール
の大きさによって左右されると共に、はんだの溶融時の
ダレ等によって大きく変化するものであるため、高さ及
び幅の均一なバンプ電極を得ることが困難であり、図7
に示したように、該バンプ電極101を有するセラミッ
ク多層配線基板102と、マザーボード103とが一定
の間隔を保って接合できた場合においても、その高さ及
び幅の不均一性故に隣接したバンプ電極間のショート、
或いは両基板電極間の接続不良等の問題が、依然として
発生し易いものであった。Further, the size and shape of the bump electrode formed by the above-mentioned conventional method depends on the printing or application amount of the cream solder and the size of the solder ball as described above, and It is difficult to obtain a bump electrode having a uniform height and width because it largely changes due to sagging during melting.
As shown in FIG. 3, even when the ceramic multilayer wiring substrate 102 having the bump electrodes 101 and the mother board 103 can be joined with a constant space therebetween, the bump electrodes adjacent to each other due to the unevenness in height and width. Short between,
Alternatively, problems such as connection failure between both substrate electrodes are still likely to occur.
【0007】さらに、上記した問題は、今後さらにセラ
ミック多層配線基板を用いたモジュールの高集積化、及
び高密度化が図られる中で、これらのセラミック多層配
線基板をマザーボードへ実装する際、より顕著に現れ、
製品の歩留りを悪化させることが危惧されていた。Further, the above-mentioned problems are more remarkable when mounting these ceramic multi-layer wiring boards on a mother board in the future as the modules using the ceramic multi-layer wiring boards are highly integrated and highly densified. Appeared in
It was feared that the yield of products would deteriorate.
【0008】本発明は、上述した従来技術が有する課題
に鑑みなされたものであって、その目的は、バンプ電極
を有したセラミック多層配線基板をマザーボードに実装
する際、両基板間隔を一定に保つことが可能で、且つ高
密度なバンプ電極による接続が可能な、セラミック多層
配線基板上に形成する新規なバンプ電極、及び該バンプ
電極の形成方法を提供することにある。The present invention has been made in view of the above-mentioned problems of the prior art, and an object thereof is to keep a constant space between both substrates when mounting a ceramic multilayer wiring substrate having bump electrodes on a mother board. The present invention provides a novel bump electrode formed on a ceramic multilayer wiring substrate that can be connected by a high-density bump electrode, and a method for forming the bump electrode.
【0009】[0009]
【課題を解決するための手段】本発明は、上記目的を達
成するため、セラミック多層配線基板に形成されたバイ
ア導体直上に、該バイア導体と電気的接続が可能で、且
つはんだより融点の高い金属で形成されたコア電極を設
け、該コア電極の表面に、はんだ層を設けたバンプ電極
とした。In order to achieve the above object, the present invention is capable of electrically connecting to a via conductor formed directly on a ceramic multilayer wiring substrate and having a higher melting point than solder. A core electrode formed of a metal was provided, and a solder electrode was provided on the surface of the core electrode to form a bump electrode.
【0010】また、本発明は、所定形状の貫通孔が形成
されたメタルマスクを用いて、セラミック多層配線基板
に形成されたバイア導体直上に、Ag系若しくはCu系
導体ペーストをスクリーン印刷し、その後乾燥、焼成し
て所望のコア電極を形成し、さらに前記コア電極の表面
に、溶融浸漬法にてはんだ層を形成するバンプ電極の形
成方法とした。Further, according to the present invention, an Ag-based or Cu-based conductor paste is screen-printed directly on the via conductor formed on the ceramic multilayer wiring board by using a metal mask having a through hole having a predetermined shape, and then the screen printing is performed. A method of forming a bump electrode is described in which a desired core electrode is formed by drying and firing, and a solder layer is formed on the surface of the core electrode by a melt dipping method.
【0011】上記した本発明にかかるバンプ電極によれ
ば、該バンプ電極を有するセラミック多層配線基板をマ
ザーボードに実装する際、その実装のための加熱温度で
は溶融しないコア電極がスペーサの役割を果たし、両基
板を一定間隔に保った状態で接合することが可能となる
と共に、両基板の接合に寄与するはんだは、上記コア電
極の表面に層として設けられた少量のものであるため、
かなり近接してバンプ電極を形成しても、ショート等の
問題が起きにくい構造となり、高密度なバンプ電極によ
る接続が可能となる。According to the above-mentioned bump electrode of the present invention, when the ceramic multilayer wiring board having the bump electrode is mounted on the mother board, the core electrode which does not melt at the heating temperature for mounting serves as a spacer. It becomes possible to bond both substrates while keeping them at regular intervals, and the solder that contributes to the bonding of both substrates is a small amount provided as a layer on the surface of the core electrode,
Even if the bump electrodes are formed in close proximity to each other, a structure such as a short circuit is unlikely to occur, and a high-density bump electrode can be connected.
【0012】また、上記した本発明にかかるバンプ電極
の形成方法によれば、いわゆる型を使用してコア電極を
形成するものであるため、その形成されるコア電極の高
さ及び幅は均一なものとすることが容易となり、スペー
サとしての信頼性が高いコア電極を有するバンプ電極の
形成が可能となり、また、該コア電極へのはんだ層の形
成は、溶融浸漬法にて行われるため、マザーボードへの
実装時にダレ等の発生が少ない均一な薄膜のはんだ層
を、簡易にコア電極表面上に形成することが可能とな
る。According to the bump electrode forming method of the present invention described above, since the core electrode is formed using a so-called mold, the height and width of the formed core electrode are uniform. It is possible to form a bump electrode having a highly reliable core electrode as a spacer, and a solder layer is formed on the core electrode by a melt dipping method. It is possible to easily form a uniform thin-film solder layer on the surface of the core electrode with less sagging during mounting on the core electrode.
【0013】ここで、上記バイア導体直上に設けるコア
電極の寸法形状としては、高さ50〜500μm、底面
径100〜1000μm、底面径に対する高さのアスペ
クト比0.25〜1.0の範囲内にある台形形状のコア
電極とすることが望ましい。これは、このような寸法形
状のコア電極とすることにより、該コア電極がマザーボ
ードへの実装時にスペーサとしての役割を有効に果たし
得る強度を有するものとなると共に、高密度な接続に対
応可能なコア電極となるためである。Here, the size and shape of the core electrode provided right above the via conductor are such that the height is 50 to 500 μm, the bottom diameter is 100 to 1000 μm, and the aspect ratio of the height to the bottom diameter is 0.25 to 1.0. It is desirable to use a trapezoidal core electrode as described in 1. This is because the core electrode having such a size and shape has such strength that the core electrode can effectively function as a spacer when mounted on a mother board, and can be used for high-density connection. This is because it becomes a core electrode.
【0014】また、上記コア電極の表面に設けられたは
んだ層の面上には、さらに金メッキ層を設けることが望
ましい。これは、金メッキ層がはんだの表面酸化を防ぐ
ことができ、長期間保存しても基板実装時のはんだの濡
れ性を良好に保つことが可能となり、さらに接合の信頼
性の高いバンプ電極を提供できるためである。Further, it is desirable to further provide a gold plating layer on the surface of the solder layer provided on the surface of the core electrode. This is because the gold plating layer can prevent the surface oxidation of the solder, and can maintain good solder wettability when mounting on the board even after long-term storage, and provide a bump electrode with high bonding reliability. Because you can.
【0015】さらに、上記コア電極の形成においては、
アディティブ法によりメタルに形成したコア電極の所望
とする高さの約1.0〜1.3倍の高さを有し、コア電
極の所望とする底面径の約0.8〜1.2倍の径を有す
る貫通孔の加工面に、自己潤滑性を有するフッ素系化合
物の被膜を形成したメタルマスクを用いて行うことが望
ましい。これは、メタルの加工面に施した上記自己潤滑
性を有するフッ素化合物の被膜の存在により、Ag系若
しくはCu系導体ペーストの印刷時のメタルマスク裏面
への該ペーストのダレ込み防止、及びペーストのメタル
マスクからの抜け性について、良好な結果が得られるた
めである。Further, in forming the core electrode,
It has a height of about 1.0 to 1.3 times the desired height of the core electrode formed on the metal by the additive method, and about 0.8 to 1.2 times the desired bottom diameter of the core electrode. It is desirable to use a metal mask in which a film of a fluorine compound having self-lubricating property is formed on the processed surface of the through hole having the diameter of. This is because the presence of the above-mentioned self-lubricating fluorine compound coating on the processed surface of the metal prevents sagging of the paste on the back surface of the metal mask during printing of the Ag-based or Cu-based conductor paste, and This is because good results can be obtained regarding the detachability from the metal mask.
【0016】なお、印刷後および乾燥時のペーストのダ
レは、ペーストのチクソトロピー性を高めることと、ペ
ースト化する際に樹脂系バインダーを使用しないことで
ダレ抑制効果が得られる。Regarding the sagging of the paste after printing and during drying, an effect of suppressing sagging can be obtained by improving the thixotropy of the paste and by not using a resinous binder in forming the paste.
【0017】上記したコア電極の表面に、フラックスを
塗布し、はんだ溶融槽中に浸漬することで均一なはんだ
層をコア電極表面に形成し、また必要に応じて、上記は
んだ層の表面に、さらに無電解金メッキ液に浸漬する方
法にて金メッキ層を形成する。ここでは、一般に市販さ
れているフラックス、はんだ並びに無電解金メッキ液を
使用することができる。Flux is applied to the surface of the core electrode described above, and a uniform solder layer is formed on the surface of the core electrode by immersing it in a solder melting bath, and, if necessary, on the surface of the solder layer, Further, a gold plating layer is formed by a method of immersing it in an electroless gold plating solution. Here, generally commercially available flux, solder and electroless gold plating solution can be used.
【0018】[0018]
【実施例】以下、上記した本発明にかかるバンプ電極、
及びその形成方法の実施例を、図面を参照しながら説明
する。EXAMPLES Hereinafter, the bump electrode according to the present invention described above,
And, an embodiment of the forming method thereof will be described with reference to the drawings.
【0019】ここで、図1は本発明の実施例におけるセ
ラミック多層配線基板上への高密度なバンプ電極形成後
の断面図であり、かかるバンプ電極は、そのバンプ径が
300μm、バンプ高さが250μm、バンプピッチが
500μmに形成されたバンプ電極である。FIG. 1 is a cross-sectional view after forming high-density bump electrodes on a ceramic multilayer wiring substrate according to an embodiment of the present invention. Such bump electrodes have a bump diameter of 300 μm and a bump height of 300 μm. It is a bump electrode having a thickness of 250 μm and a bump pitch of 500 μm.
【0020】図1において、1はセラミック多層配線基
板、2はバイア導体(Ag)、3はコア電極(20%P
d−Ag)、4ははんだ層(62Sn/36Pb/2A
g)、5は金メッキ層である。In FIG. 1, 1 is a ceramic multilayer wiring board, 2 is a via conductor (Ag), 3 is a core electrode (20% P).
d-Ag), 4 is a solder layer (62Sn / 36Pb / 2A)
g) and 5 are gold plating layers.
【0021】上記バンプ電極の形成方法を、以下に説明
する。A method of forming the bump electrode will be described below.
【0022】先ず、コア電極形成用ペースト(20%P
d含有Agペースト、BPM−105:日本セメント株
式会社製)を、図3に示したメタル厚300μm、貫通
孔6の底面径が280μmのアディティブ法で作製した
メタルマスク7を用いて、セラミック多層配線基板に形
成されたバイア導体直上に、硬度70の角スキージを用
いてスクリーン印刷し、70°Cで10分間乾燥後、ベ
ルト焼成炉にて大気中、ピーク温度850°Cで10分
間保持し、且つ全工程が60分のプロファイルで焼成を
行った。なお、上記メタルマスク7の加工面には、フッ
素系化合物の被膜8が形成されている。First, a core electrode forming paste (20% P
d-containing Ag paste, BPM-105: manufactured by Nippon Cement Co., Ltd., using a metal mask 7 made by an additive method with a metal thickness of 300 μm and a bottom diameter of the through hole 6 of 280 μm shown in FIG. Directly on the via conductor formed on the substrate, screen-printed using a square squeegee having a hardness of 70, dried at 70 ° C. for 10 minutes, and then held in a belt baking furnace in the atmosphere at a peak temperature of 850 ° C. for 10 minutes, Moreover, the firing was performed in a profile of 60 minutes in all steps. A film 8 of a fluorine-based compound is formed on the processed surface of the metal mask 7.
【0023】次に、焼成後の上記コア電極表面に、フラ
ックス(R5003:日本アルファメタルズ株式会社
製)を塗布し、150°Cで30秒間予備加熱した後、
230°Cに溶融されたはんだ(62Sn/36Pb/
2Agはんだ、S−2062:千住金属株式会社製)浴
槽中に該コア電極を5秒間浸漬し、コア電極表面にはん
だ層を形成した。上記塗布したフラックス洗浄は、エタ
ノール+酢酸ブチルの混合液中で浸漬攪拌30秒を行う
ことにより実施した。Next, flux (R5003: manufactured by Nippon Alpha Metals Co., Ltd.) was applied to the surface of the core electrode after firing, and preheating was performed at 150 ° C. for 30 seconds,
Solder melted at 230 ° C (62Sn / 36Pb /
2Ag solder, S-2062: Senju Metal Co., Ltd.) The core electrode was immersed in a bath for 5 seconds to form a solder layer on the surface of the core electrode. The above-mentioned applied flux cleaning was carried out by dipping and stirring for 30 seconds in a mixed solution of ethanol + butyl acetate.
【0024】その後、得られたコア電極のはんだ層表面
に、無電解金メッキ(K24N:高純度化学株式会社
製)を用いて、メッキ液温90°C±5°Cで1分間浸
漬することにより、膜厚約100オングストロームの金
メッキ層を形成した。After that, electroless gold plating (K24N: manufactured by Kojundo Chemical Co., Ltd.) was used on the surface of the solder layer of the obtained core electrode, and the plating solution was immersed for 1 minute at a temperature of 90 ° C. ± 5 ° C. A gold plating layer having a film thickness of about 100 angstrom was formed.
【0025】以上、記載した本発明にかかるバンプ電極
の形成方法により得られたバンプ電極の寸法データを、
図4に示す。As described above, the dimensional data of the bump electrode obtained by the bump electrode forming method according to the present invention is
As shown in FIG.
【0026】図4から明らかなように、本発明にかかる
バンプ電極の形成方法によれば、該バンプ電極の径、及
び高さが±5%以内のバラツキ範囲内で形成できること
が判明する。As is clear from FIG. 4, the bump electrode forming method according to the present invention makes it possible to form the bump electrode within a variation range of ± 5% in diameter and height.
【0027】次に、上記した本発明で得られたバンプ電
極と、従来法で得られたバンプ電極との性能を比較する
ため、バンプ径300μm、バンプ高さ250μm、バ
ンプピッチ500μmのバンプ900個を形成したセラ
ミック多層配線基板を、従来法と上記した本発明におけ
る方法で各々30基板作製し、それらの基板をAu電極
が形成されたアルミナ多層配線基板(マザーボード)上
に位置合わせして搭載後、バンプ部のはんだを溶融する
ことで両基板を実装した。Next, in order to compare the performance of the bump electrode obtained in the present invention with the bump electrode obtained by the conventional method, 900 bumps having a bump diameter of 300 μm, a bump height of 250 μm and a bump pitch of 500 μm. After the ceramic multilayer wiring board having the above-mentioned structure was manufactured by the conventional method and the above-described method of the present invention, 30 substrates each were manufactured, and these substrates were aligned and mounted on the alumina multilayer wiring board (motherboard) on which the Au electrode was formed. Both substrates were mounted by melting the solder on the bumps.
【0028】得られた実装基板において、従来法、及び
本発明における方法で作製した基板のバンプ部接続歩留
りを求めたところ、従来法で形成したバンプ電極形成基
板の実装歩留りは67%であり、本発明における方法で
形成したバンプ電極形成基板の実装歩留りは93%であ
った。In the mounting board thus obtained, the yield ratio for connecting bumps of the board manufactured by the conventional method and the method of the present invention was determined, and the mounting yield of the bump electrode-formed substrate formed by the conventional method was 67%. The mounting yield of the bump electrode-formed substrate formed by the method of the present invention was 93%.
【0029】[0029]
【発明の効果】以上、説明した本発明にかかるバンプ電
極、及び該バンプ電極の形成方法によれば、バンプ電極
を有したセラミック多層配線基板のマザーボードへの実
装歩留まりの向上と、高密度なバンプ電極接続に対応可
能なセラミック多層配線基板上のバンプ電極の形成が可
能となる。As described above, according to the bump electrode and the method for forming the bump electrode according to the present invention, the mounting yield of the ceramic multilayer wiring board having the bump electrode on the mother board is improved and the high density bump is provided. It is possible to form bump electrodes on the ceramic multilayer wiring substrate that can be connected to electrodes.
【図1】本発明の実施例におけるバンプ電極を形成した
セラミック多層配線基板の断面図である。FIG. 1 is a cross-sectional view of a ceramic multilayer wiring board having bump electrodes formed thereon according to an embodiment of the present invention.
【図2】本発明の実施例におけるバンプ電極を形成した
セラミック多層配線基板のマザーボードへの実装後の断
面図である。FIG. 2 is a cross-sectional view of a ceramic multilayer wiring board having bump electrodes formed thereon according to an embodiment of the present invention after being mounted on a mother board.
【図3】本発明においてバンプ電極の形成に用いるメタ
ルマスクの断面図である。FIG. 3 is a cross-sectional view of a metal mask used for forming bump electrodes in the present invention.
【図4】本発明の実施例によって得られたバンプ電極の
寸法データを示したグラフである。FIG. 4 is a graph showing dimensional data of bump electrodes obtained according to an example of the present invention.
【図5】従来法におけるバンプ電極を形成したセラミッ
ク多層配線基板の断面図である。FIG. 5 is a cross-sectional view of a ceramic multilayer wiring substrate having bump electrodes formed by a conventional method.
【図6】従来法におけるバンプ電極を形成したセラミッ
ク多層配線基板のマザーボードへの実装後の断面図であ
る。FIG. 6 is a cross-sectional view after mounting a ceramic multilayer wiring substrate on which bump electrodes are formed in a conventional method on a mother board.
【図7】従来法におけるバンプ電極を形成したセラミッ
ク多層配線基板のマザーボードへの実装後の断面図であ
る。FIG. 7 is a cross-sectional view after mounting a ceramic multilayer wiring substrate on which bump electrodes are formed in a conventional method on a mother board.
1 セラミック多層配線基板 2 バイア導体 3 コア電極 4 はんだ層 5 金メッキ層 6 貫通孔 7 メタルマスク 8 フッ素系化合物の被膜 9 マザーボード 1 Ceramic Multilayer Wiring Board 2 Via Conductor 3 Core Electrode 4 Solder Layer 5 Gold Plated Layer 6 Through Hole 7 Metal Mask 8 Fluorine Compound Coating 9 Motherboard
Claims (5)
イア導体直上に、該バイア導体と電気的接続が可能で、
且つはんだより融点の高い金属で形成されたコア電極を
設け、該コア電極の表面に、はんだ層を設けたことを特
徴とするバンプ電極。1. A ceramic multi-layer wiring board is directly above the via conductor, and can be electrically connected to the via conductor,
A bump electrode comprising a core electrode formed of a metal having a melting point higher than that of solder, and a solder layer provided on the surface of the core electrode.
層を設けたことを特徴とする、請求項1記載のバンプ電
極。2. The bump electrode according to claim 1, wherein a gold plating layer is further provided on the surface of the solder layer.
スクを用いて、セラミック多層配線基板に形成されたバ
イア導体直上に、Ag系若しくはCu系導体ペーストを
スクリーン印刷し、その後乾燥、焼成して所望のコア電
極を形成し、さらに前記コア電極の表面に、溶融浸漬法
にてはんだ層を形成したことを特徴とする、バンプ電極
の形成方法。3. An Ag-based or Cu-based conductor paste is screen-printed directly on the via conductor formed on the ceramic multilayer wiring board by using a metal mask having through holes of a predetermined shape formed, and then dried and baked. A bump electrode is formed by forming a desired core electrode by a melt dipping method on the surface of the core electrode.
性を有するフッ素系化合物の被膜が形成されていること
を特徴とする、請求項3記載のバンプ電極の形成方法。4. The method of forming a bump electrode according to claim 3, wherein a film of a fluorine-based compound having self-lubricating property is formed on the processed surface of the metal mask.
メッキ液に浸漬する方法にて金メッキ層を形成すること
を特徴とする、請求項3記載のバンプ電極の形成方法。5. The bump electrode forming method according to claim 3, wherein a gold plating layer is formed on the surface of the solder layer by a method of further immersing the solder layer in an electroless gold plating solution.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19685093A JP3354221B2 (en) | 1993-07-14 | 1993-07-14 | Method of forming bump electrode |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19685093A JP3354221B2 (en) | 1993-07-14 | 1993-07-14 | Method of forming bump electrode |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0730244A true JPH0730244A (en) | 1995-01-31 |
JP3354221B2 JP3354221B2 (en) | 2002-12-09 |
Family
ID=16364702
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Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19685093A Expired - Fee Related JP3354221B2 (en) | 1993-07-14 | 1993-07-14 | Method of forming bump electrode |
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JP (1) | JP3354221B2 (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002164473A (en) * | 2000-11-29 | 2002-06-07 | Sharp Corp | Semiconductor device and method for manufacturing the same |
JP2006269972A (en) * | 2005-03-25 | 2006-10-05 | Mitsumi Electric Co Ltd | Semiconductor device |
JP2006310619A (en) * | 2005-04-28 | 2006-11-09 | Mitsubishi Electric Corp | High-frequency circuit module and its mounting structure |
CN100438725C (en) * | 2003-08-12 | 2008-11-26 | 日本梅克特隆株式会社 | Printing clamp for printing circuit substrate |
JP2009054741A (en) * | 2007-08-27 | 2009-03-12 | Powertech Technology Inc | Semiconductor package |
JP2015126159A (en) * | 2013-12-27 | 2015-07-06 | 三菱マテリアル株式会社 | Core paste for forming sintered core of solder bump |
JP2016018914A (en) * | 2014-07-09 | 2016-02-01 | 三菱マテリアル株式会社 | Semiconductor device and manufacturing method of the same |
-
1993
- 1993-07-14 JP JP19685093A patent/JP3354221B2/en not_active Expired - Fee Related
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002164473A (en) * | 2000-11-29 | 2002-06-07 | Sharp Corp | Semiconductor device and method for manufacturing the same |
CN100438725C (en) * | 2003-08-12 | 2008-11-26 | 日本梅克特隆株式会社 | Printing clamp for printing circuit substrate |
JP2006269972A (en) * | 2005-03-25 | 2006-10-05 | Mitsumi Electric Co Ltd | Semiconductor device |
JP2006310619A (en) * | 2005-04-28 | 2006-11-09 | Mitsubishi Electric Corp | High-frequency circuit module and its mounting structure |
JP4624172B2 (en) * | 2005-04-28 | 2011-02-02 | 三菱電機株式会社 | High frequency circuit module |
JP2009054741A (en) * | 2007-08-27 | 2009-03-12 | Powertech Technology Inc | Semiconductor package |
JP2015126159A (en) * | 2013-12-27 | 2015-07-06 | 三菱マテリアル株式会社 | Core paste for forming sintered core of solder bump |
JP2016018914A (en) * | 2014-07-09 | 2016-02-01 | 三菱マテリアル株式会社 | Semiconductor device and manufacturing method of the same |
Also Published As
Publication number | Publication date |
---|---|
JP3354221B2 (en) | 2002-12-09 |
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