JPH07297309A - Surface mounting type ic - Google Patents
Surface mounting type icInfo
- Publication number
- JPH07297309A JPH07297309A JP6088589A JP8858994A JPH07297309A JP H07297309 A JPH07297309 A JP H07297309A JP 6088589 A JP6088589 A JP 6088589A JP 8858994 A JP8858994 A JP 8858994A JP H07297309 A JPH07297309 A JP H07297309A
- Authority
- JP
- Japan
- Prior art keywords
- groove
- mounting
- surface mount
- chip
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はフラットパッケージの表
面実装型ＩＣに関し、特にパッケージの下面にチップ部
品実装用の溝を有する構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface mount type IC of a flat package, and more particularly to a structure having a groove for mounting a chip component on the lower surface of the package.
【０００２】[0002]
【従来の技術】従来、表面実装型ＩＣは、例えば、特開
平２−２２６７０９号公報に示されるように、プリント
基板の実装面積を小さくするためにＪリード型表面実装
ＩＣの下面とプリント基板上面とで形成される間隙を利
用してＪリード型ＩＣの下に実装することが行われてい
た。2. Description of the Related Art Conventionally, a surface mount type IC is disclosed in, for example, Japanese Patent Laid-Open No. 2-226709. It has been carried out under the J-lead type IC by utilizing the gap formed by.
【０００３】図４は従来の表面実装型ＩＣの一例を示す
正面図である。ＩＣ６はＪリード型表面実装ＩＣで、プ
リント基板２に表面実装される。チップコンデンサ７は
Ｊリード型表面実装ＩＣ６の下面とプリント基板２の上
面とで形成される間隔と同じ厚さを持つチップコンデン
サである。FIG. 4 is a front view showing an example of a conventional surface mount type IC. The IC 6 is a J lead type surface mounting IC, and is surface mounted on the printed circuit board 2. The chip capacitor 7 is a chip capacitor having the same thickness as the interval formed by the lower surface of the J lead type surface mount IC 6 and the upper surface of the printed board 2.
【０００４】この実装方法により、チップコンデンサ７
の実装面積分だけプリント基板の実装面積を小さくして
いた。By this mounting method, the chip capacitor 7
The mounting area of the printed circuit board is reduced by the mounting area.
【０００５】[0005]
【発明が解決しようとする課題】この従来の表面実装型
ＩＣでは、Ｊリード型のの下面とプリント基板上面の間
隙を利用してチップコンデンサを実装しているため、Ｊ
リード型のＩＣに限られており、フラットパッケージの
表面実装型ＩＣではこの実装方法は適用できない問題点
を有していた。In this conventional surface mount type IC, the chip capacitor is mounted by utilizing the gap between the lower surface of the J lead type and the upper surface of the printed circuit board.
This is limited to the lead type IC, and there is a problem that this mounting method cannot be applied to the surface mount type IC of the flat package.
【０００６】[0006]
【課題を解決するための手段】上述した問題点を解決す
るため、本発明の表面実装型ＩＣでは、ＩＣの下面部に
チップ部品実装用の溝を設けている。In order to solve the above-mentioned problems, in the surface mounting type IC of the present invention, a groove for mounting a chip component is provided on the lower surface of the IC.
【０００７】[0007]
【実施例】本発明について図面を参照して説明する。図
１は本発明の表面実装型ＩＣ１の外観図、図２は図１に
示されたＡ−Ａ′面における断面図、図３は図１に示さ
れた表面実装型ＩＣ１の下面図である。図１において、
本ＩＣは、表面実装型ＩＣにおいて標準的に用いられる
フラットパッケージ構造をしている。図１において、Ｉ
Ｃ１はプリント基板２と複数のリード端子３−１〜３−
Ｎにより接続されている。図２の断面図において、ＩＣ
１のリード端子３−１と３−２の間において、ＩＣ１の
下面部に細長い溝４が設けられており、溝４の底面とプ
リント板２との間の間隙部にチップ部品５が装着されて
いる。図３のＩＣ１の下面図において、溝４の形状を詳
述する。溝４の高さは、プリント基板上にチップ部品を
取り付けた場合にチップ部品５の上面部より高くなるよ
うな高さに選ばれている。また、溝４の幅は、チップ部
品５の幅よりも広い寸法としている。図３において、表
面実装型ＩＣ１は、下面部の端子３の間に溝４が入って
いる。ここでは表面実装型ＩＣ１の下面部には溝４がリ
ード端子３−１と３−２の間において１本しか入ってい
ないが、これに限定されるものではない。すなわち、表
面実装型ＩＣ１のデバイス自身はパッケージ内部の中心
部にわずかな部分にしか存在せず、パッケージの大きさ
は端子数で決まってくる。そのため、端子数が多ければ
パッケージも大きくなり、溝４は複数本入れることがで
き、それだけチップ部品を多く実装することができる。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the drawings. 1 is an external view of the surface mount IC 1 of the present invention, FIG. 2 is a cross-sectional view taken along the line AA ′ shown in FIG. 1, and FIG. 3 is a bottom view of the surface mount IC 1 shown in FIG. . In FIG.
This IC has a flat package structure that is standardly used in surface mount type ICs. In FIG. 1, I
C1 is a printed circuit board 2 and a plurality of lead terminals 3-1 to 3-3-
Connected by N. In the sectional view of FIG.
The elongated groove 4 is provided on the lower surface of the IC 1 between the lead terminals 3-1 and 3-2 of FIG. ing. In the bottom view of the IC 1 of FIG. 3, the shape of the groove 4 will be described in detail. The height of the groove 4 is selected to be higher than the upper surface of the chip component 5 when the chip component is mounted on the printed board. Further, the width of the groove 4 is set to be larger than the width of the chip component 5. In FIG. 3, the surface mount IC 1 has a groove 4 between terminals 3 on the lower surface. Here, only one groove 4 is provided between the lead terminals 3-1 and 3-2 on the lower surface of the surface-mounted IC 1, but the invention is not limited to this. In other words, the device itself of the surface mount IC 1 exists only in a small part in the center of the inside of the package, and the size of the package is determined by the number of terminals. Therefore, if the number of terminals is large, the package becomes large, and a plurality of grooves 4 can be provided, so that many chip components can be mounted.
【０００８】次に実装方法を説明する。プリント基板２
上にはリード端子３−１〜３−Ｎに対応してパッドが設
けられている。また、溝４部に取り付けられるチップ部
品５に対応してパッドが設けられている。最初に、溝４
部に取り付けられるチップ部品５を溝４の所定のパッド
の位置に接着する。その後、表面実装型ＩＣ１をプリン
ト基板２にハンダ付け（リフロー）する。Next, a mounting method will be described. Printed circuit board 2
Pads are provided above the lead terminals 3-1 to 3-N. Further, pads are provided corresponding to the chip parts 5 attached to the groove portion 4. First, groove 4
The chip component 5 attached to the part is bonded to the groove 4 at a predetermined pad position. After that, the surface mount type IC 1 is soldered (reflow) to the printed board 2.
【０００９】[0009]
【発明の効果】以上説明したように、本発明は、表面実
装型ＩＣの下面にチップ部品実装用の溝を設けているた
め、フラットパッケージのＩＣにおいて、プリント基板
上にチップ部品の実装面積分だけプリント基板の実装面
積を小さくできる。特に大きな表面実装型ＩＣを複数個
高密度実装する場合、チップ部品の実装面積が大幅に削
減できるため、プリント基板の大幅な小型化がはかられ
る。As described above, according to the present invention, since the surface mounting type IC is provided with the groove for mounting the chip component on the lower surface thereof, in the IC of the flat package, the mounting area of the chip component is mounted on the printed circuit board. Only, the mounting area of the printed circuit board can be reduced. Particularly when a plurality of large surface mount type ICs are mounted at a high density, the mounting area of chip components can be significantly reduced, and thus the printed circuit board can be significantly downsized.
【００１０】また、チップコンデンサを実装する場合、
通常図１において、通常リード端子３−２が電源端子と
なるためそのリード端子に最短距離で取り付けることに
よりデカップリングすることができる等の効果を有す
る。When mounting a chip capacitor,
Usually, in FIG. 1, since the lead terminal 3-2 normally serves as a power supply terminal, there is an effect that decoupling can be performed by attaching the lead terminal 3-2 to the lead terminal at the shortest distance.
【図１】本発明による表面実装型ＩＣの外観図である。FIG. 1 is an external view of a surface mount IC according to the present invention.
【図２】本発明のＩＣのＡ−Ａ′断面図である。FIG. 2 is a sectional view taken along the line AA ′ of the IC of the present invention.
【図３】本発明のＩＣの下面図である。FIG. 3 is a bottom view of the IC of the present invention.
【図４】従来の表面実装型ＩＣの一実装例図である。FIG. 4 is a diagram showing one mounting example of a conventional surface mount type IC.
１ 表面実装型ＩＣ ２ プリント基板 ３−１〜３−Ｎ 端子 ４ チップ部品実装用溝 ５ チップ部品 ６ Ｊリード型表面実装ＩＣ ７ チップコンデンサ 1 Surface Mount Type IC 2 Printed Circuit Board 3-1 to 3-N Terminal 4 Chip Component Mounting Groove 5 Chip Component 6 J Lead Type Surface Mount IC 7 Chip Capacitor
Claims (2)
トパッケージの表面実装型ＩＣの底面部において、相対
するリード端子間に細長い溝を設け、前記溝と前記プリ
ント基板の間隙にチップ部品を取り付けることを特徴と
する表面実装型ＩＣ。1. An elongated groove is provided between opposing lead terminals on a bottom surface portion of a surface mount type IC of a flat package mounted on a printed circuit board, and a chip component is mounted in a gap between the groove and the printed circuit board. Surface mount type IC.
ら前記溝の底面部の高さが、前記チップ部品の上面部よ
り高く、前記溝の幅は、前記チップ部品の幅よりも広い
ことを特徴とする表面実装型ＩＣ。2. The groove according to claim 1, wherein a height of a bottom surface portion of the groove from the printed board is higher than an upper surface portion of the chip component, and a width of the groove is wider than a width of the chip component. A surface mount type IC characterized in that
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6088589A JPH07297309A (en) | 1994-04-26 | 1994-04-26 | Surface mounting type ic |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6088589A JPH07297309A (en) | 1994-04-26 | 1994-04-26 | Surface mounting type ic |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07297309A true JPH07297309A (en) | 1995-11-10 |
Family
ID=13947028
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6088589A Pending JPH07297309A (en) | 1994-04-26 | 1994-04-26 | Surface mounting type ic |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07297309A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6033457B2 (en) * | 1981-09-22 | 1985-08-02 | カワサキ機工株式会社 | Tea processing method and tea processing device |
-
1994
- 1994-04-26 JP JP6088589A patent/JPH07297309A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6033457B2 (en) * | 1981-09-22 | 1985-08-02 | カワサキ機工株式会社 | Tea processing method and tea processing device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19970114 |