JPH07254277A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor storage device, in which the column addrsses of a large quantity of data can be changed at a time and data on one line can be moved in a short time. CONSTITUTION:Bit lines BL1-BLn, to which a plurality of memory cells are connected, and sense amplifiers SA1-SAn for reading the data of the memory cells are provided. Switching elements P10, P11-Pn0, Pn1-/P10, /P11-/Pn0 and /Pn1 shifting the sense amplifier from a bit line having a corresponding column address to a bit line having a column address before or after the column address by one or more and connecting the sensor amplifier at the time of a specific mode are mounted. The states of connection at a time when data are read from the bit lines and at a time when data are written to the bit lines are made different.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having switching elements for switching and connecting bit lines and sense amplifiers.

[0002]

2. Description of the Related Art In a conventional semiconductor memory device, reading and writing of data are performed as follows. That is, data is sent from the memory cell corresponding to the word line selected as the bit line, and the data is read by the sense amplifier. If necessary, the data is written back from the sense amplifier to the cell.

However, in this method, in order to change the address of a certain group of data in the column direction, that is, to move the data to another bit line as it is, they are read out one by one outside the sense amplifier, Had to be written back to another column. Specifically, for example, in the signal processing in the image memory, when the data of one line is moved to another line as it is, in order to read the data of one line outside the sense amplifier and write it back to another line, It takes a lot of time.

[0004]

As described above, conventionally, in order to change the address of a certain group of data in the column direction, it is necessary to read them one by one outside the sense amplifier and write them back to another column. However, there is a problem that this operation takes a lot of time.

The present invention has been made in consideration of the above circumstances, and an object thereof is to change a column address of a large amount of data at a time and to move data of one line in a short time. Another object of the present invention is to provide a semiconductor memory device that can be carried out.

[0006]

In order to solve the above problems, the present invention employs the following configurations. That is, the present invention (claim 1) provides a semiconductor memory device having a plurality of bit lines to which a plurality of memory cells are connected and a plurality of sense amplifiers for reading the data of the memory cells, in a specific mode. A switching element for shifting and connecting the sense amplifier from a bit line having a predetermined column address to a bit line having one or more column addresses before or after the column address is provided to read data from the bit line. It is characterized in that the connection state when writing data to the bit line is changed.

The present invention (claim 2) is a semiconductor memory device having a plurality of bit lines to which a plurality of memory cells are connected and a plurality of sense amplifiers for reading data from the memory cells. A node is provided for each amplifier, and in a specific mode, a sense amplifier is connected by shifting from a sense amplifier node having a predetermined column address to a sense amplifier node having one or more column addresses before or after the column address. It is characterized in that a switching element is provided and the connection state at the time of reading data from the bit line and at the time of writing data to the bit line is changed.

Here, the following are preferred embodiments of the present invention. (1) One sense amplifier is formed for one bit line, and a switching element is provided for selectively connecting the sense amplifier to one bit line corresponding to this sense amplifier and another one bit line. thing. (2) One sense amplifier is formed for n bit lines, and the sense amplifier corresponds to any one of the n bit lines corresponding to the sense amplifier or n corresponding to another sense amplifier.
The switching element that shifts and connects to one of the bit lines of the book is provided. (3) The switching element is
In the case of the one connected to the first sense amplifier, the bit line having a predetermined column address is shifted and connected to the adjacent bit line in position, and in the other cases, the bit line having a predetermined column address is moved in position. The second bit line is shifted to the second bit line and connected. In the folded bit line system, the bit line adjacent to the bit line having the predetermined column address is two bits next to the bit line having the predetermined column address in the case of connecting to the first sense amplifier. Connected by shifting to a line, and otherwise, positionally 4 from the bit line with a given column address
Must be shifted to the second bit line and connected. (4) In the open bit line system, the switching element selects one of the nth bit line and the 1st bit line from the end in the sense amplifier which is the first from the end, and the kth from the end (k =
In the sense amplifiers 2 to n), one of the k-1th and kth bit lines from the end is selected. (5) In the folded bit line system, the switching element is 1 from the end in the sense amplifier which is the first from the end.
Select one of the 2nd and 2n-1th bit lines, or the 2nd and 2nth bit lines from the end, and select the kth (k = 2 to 2)
In the n) sense amplifier, the 2k−1th and 2k−ths from the end are provided.
One of the third bit lines and one of the 2k-th and 2k-2nd bit lines from the end should be selected. (6) The sense amplifier node having a predetermined column address is made to correspond to the second sense amplifier node in position from the sense amplifier node having the column address. (7) The node provided for each sense amplifier must have a temporary storage register that can store the data of the memory cell. (8) The sense amplifier must have a temporary storage register that can store the data of the memory cell. (9) Control switching elements by external signals.

[0009]

According to the present invention (Claim 1), the connection state of the bit line and the sense amplifier is controlled by a connection state control circuit or the like which controls the connection state of the switching element connecting the bit line and the sense amplifier by an external signal. The shift can be performed when reading data from the line to the sense amplifier and when writing data read by the sense amplifier to the bit line. Therefore, the following effects can be obtained. That is, conventionally, in order to perform parallel movement of column addresses of N pieces of data having different column addresses, one piece of N pieces of data each is taken out of the sense amplifier and connected to a bit line to be moved. I had to write it back into the existing sense amplifier, which took time. On the other hand, in the present invention, a switching element that shifts and connects one or more sense amplifiers to a plurality of bit lines each having an adjacent address is provided, and thus a group of data is not extracted to the outside of the sense amplifiers, but a column is operated at a time. Addresses can be shifted.

When shifting data between the bit lines having the first and last column addresses, a bit line having a predetermined column address and one or more column addresses before or after the column address are provided. In the open bit line system, a bit line is made to correspond to a bit line having a predetermined column address and a bit line second in position from the bit line having the column address. In the folded bit line system, a predetermined column is used. Positionally 4 from the bit line having the address and the bit line having the column address
The second bit line is shifted to the sense amplifier for connection. Further, in the open bit line system, a bit line having a predetermined column address and a bit line having one or more column addresses before or after the column address are the second from the end in the sense amplifier which is the second from the end. In the folded bit line system, the second-from-end sense amplifier corresponds to the 1st-end and the 3rd-from the end, the 2nd-from-the-end and the 4th-from-the-end, respectively. Corresponds to the bit line. As a result, the length of the wiring that connects the bit line and the sense amplifier can be shortened to be most uniform for each bit line.

Further, according to the present invention (claim 2), a connection state control circuit or the like for controlling the connection state of an independent node provided for each sense amplifier and a switching element connecting the sense amplifier by an external signal, The connection state between an independent node provided for each sense amplifier and the sense amplifier can be shifted when reading data from the sense amplifier node to the sense amplifier and when writing data read by the sense amplifier to the sense amplifier node. Therefore, similarly to (Claim 1), the column address can be changed at a time without taking out a group of data to the outside of the sense amplifier. Further, in this method, compared with the method described in (claim 1), data can be transferred faster because the bit line is not directly driven.

Further, when the data is shifted in the sense amplifier node having the first and last column addresses, the sense amplifier node having a predetermined column address and one or more column addresses before or after are added. The sense amplifier node has a sense amplifier node having a predetermined column address and a sense amplifier node having a position second from the sense amplifier node having the column address. Since the second sense amplifier node and the first sense amplifier node are associated with each other, the length of the wiring connecting the sense amplifier node and the sense amplifier can be shortened to be most uniform for each bit line.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 is a block diagram showing a schematic configuration of a semiconductor memory device according to a first embodiment of the present invention.

In FIG. 1, 1 is a memory cell array composed of a dynamic RAM, and 3 is a sense amplifier (also an equalizing gate). A switching element (transfer gate) 2 shifts and connects the sense amplifier 3 to a plurality of bit lines in the array 1 corresponding to one or more column addresses before and after. A signal for performing parallel movement of the column address is received by the address movement signal reception circuit 11 and sent to the transfer order control circuit 13. The transfer order control circuit 13 receives the signal for controlling the φt gate sent from the address movement signal receiving circuit 11 and the φt gate control circuit 12 to read the data from the bit line to the φt gate of the switching element 2 and to the bit line. Operates to shift the connection status when writing data.

FIG. 2 is a diagram showing the circuit configuration of this embodiment. BL1 to BLn are bit lines connected to a plurality of cells, and / BL1 to / BLn are complementary bit lines thereof. SA1 to SAn are sense amplifiers for reading and writing the data output to the bit lines.
P10, P11, ~ Pn0, Pn1, / P10, / P11, ~ / Pn
0, / Pn1 is an nMOS transistor and is a sense amplifier S
A switching element that connects A and the bit line, Pk
0, / Pk0 (k = 1 to n) is activated by φt0, / φt0, and Pk1, / Pk1 (k = 1 to n) is φt1,
Activated by / φt1. BLk and / BLk (k = 1 to n) are SA when φt0 and / φt0 are "H".
connected to k (k = 1 to n) and BLk and / BLk (k = 1 to n-1) are S when φt1 and / φt1 are "H".
It is connected to Ak + 1 (k = 1 to n-1). BLn is connected to BL1.

WLm is one of the word lines that select cells connected to the bit lines. The circles in the figure are
It is a memory cell. DWL is a word line that selects a dummy cell connected to the bit line.

Although the open bit line structure is shown in FIG. 2, the same can be realized in the folded bit line structure. This is shown in FIG. / WLm, /
DWL is a cell connected to / BL, a word line for selecting a dummy cell, and a dummy word line.

Next, the operation of this embodiment will be described with reference to FIGS. 4 to 6, when the data stored in the cell corresponding to WLm is "H" in BL1, "L" in BL2, "H" in BL3, "H" in BL4 ... "L" in BLn. Is shown.

FIG. 4 shows a timing chart during normal operation. After activating WLm, φt0,
/ Φt0 is set to "H", and BLk, / BLk (k = 1 to 1
The data sent to n) is sent to SAk (k = 1 to n). Thereafter, φt0 and / φt0 are set to "L" in order to disconnect the sense amplifier from the bit line. After that, the sense amplifier is driven to read the data output to BLk, / BLk (k = 1 to n) to SAk (k = 1 to n). After that, .phi.t0 and /.phi.t0 are set to "H", and the data read to SAk is read to BLk and / BLk. Then W
Lm is deactivated and the bit line and the complementary bit line are equalized.

As described above, since the data of BLk (k = 1 to n) is read by SAk and written in BLk (k = 1 to n), the address of the data in the column direction does not move.

FIGS. 5 and 6 show the case where the column address of data is moved. FIG. 5 shows a case where the data of BLk (k = 1 to n) is moved to BLk-1 (k = 1 to n) (data of BL1 is moved to BLn), and FIG. 6 is BLk (k
= 1 to n) is moved to BLk + 1 (k = 1 to n) (BLn data is moved to BL1).

In FIG. 5, after activating WLm, φt0
, / Φt0 to "H", BLk, / BLk (k = 1
To n) are sent to SAk (k = 1 to n). Thereafter, φt0 and / φt0 are set to "L" in order to disconnect the sense amplifier from the bit line. After that, the sense amplifier is driven to read the data output to BLk, / BLk (k = 1 to n) to SAk (k = 1 to n). Thereafter, .phi.t1 and /.phi.t1 are set to "H" and the data read to SAk is read to BLk-1 (the data of SA0 is read to BLn). Then, WLm is deactivated and the bit line and the complementary bit line are equalized.

In this way, the data of BLk (k = 2 to n) is read by SAk and BLk-1 (k = 1 to n).
-1) will be written (the data of BL1 is B
Move to Ln).

In FIG. 6, after activating WLm, φt1
, / Φt1 to "H", and BLk, / BLk (k = 1
To n) are sent to SAk + 1 (k = 1 to n) (BLn data is sent to SA1). After that, in order to disconnect the sense amplifier from the bit line, φt
Set 1, / φt1 to "L". After that, the sense amplifier is driven to read the data output to BLk, / BLk (k = 1 to n) to SAk + 1 (k = 1 to n) (the data of BLn is read to SA1). After that, φt0 is set to "H" and the data read to SAk + 1 is BLk + 1.
(The data read to SA1 is read to BL1). Then, WLm is deactivated and the bit line and the complementary bit line are equalized.

In this way, the data of BLk (k = 1 to n) is read by SAk + 1 and BLk + 1 (k = 1 to 1).
n will be written to (the data of BLn is BL
Move to 1).

As described above, according to the present embodiment, the bit line BLk (k = 1 to n) and the sense amplifier SAk (k = 1).
~ N + 1), the connection state of the switching element,
By shifting between the time of reading the data from the bit line to the sense amplifier and the time of writing the data read by the sense amplifier to the bit line, the address in the column direction of the group of data can be shifted one by one.

The present invention is not limited to the above embodiment. In the embodiment, it is considered that the switching element connected to the two bit lines adjacent to each other by shifting is provided. However, the number of bit lines shifted to and connected to one sense amplifier is set to three or more. Good. This has the advantage that the address of the data in the column direction can be moved even after reading the data. Further, the number of shifts is not limited to one next to each other, but n (n> 1) or adjacent ones can shift n addresses in the column direction of data at a time. In addition, various modifications can be made without departing from the scope of the present invention. (Embodiment 2) FIG. 7 shows a circuit configuration of a semiconductor memory device according to a second embodiment of the present invention, in which one sense amplifier is shared by four bit lines. This is an example.

In FIG. 7, BL10 to BLn3 are bit lines to which a plurality of cells are connected, and / BL10 to / BLn3.
Is the complementary bit line. BLkl, / BLkl (l = 0
3) are bit lines connected to the same sensor amplifier SAk.

SA1 to SAn are sense amplifiers for reading and writing the data output to the bit lines. SAk (k = 1 to n) also includes register cells RCk0 to RCk3 for temporarily storing the read data. P10 to Pn4 and / P10 to / Pn4 are switching elements for connecting the sense amplifier and the bit line with nMOS transistors, and Pkm and / Pkm (k = 1 to n) (m = 0.
3) is activated by φtm and / φtm.

When φt0 is "H", BLk0, / BL
k0 (k = 1 to n) is connected to SAk (k = 1 to n),
When φt1 is "H", BLk1, / BLk1 (k = 1 to 1
n) is connected to SAk (k = 1 to n), and BLk2 and / BLk2 (k = 1 to n) are S when φt2 is "H".
When .phi.t3 is "H", BLk3 and / BLk3 (k = 1 to n) are connected to Ak (k = 1 to n) and SAk (k = 1).
~ N), and when φt4 is "H", BLk3,
/ BLk3 (k = 1 to n) is connected to SAk + 1 (k = 1 to n).

WLm is one of the word lines for selecting cells connected to the bit lines. The circles in the figure are memory cells. DWL is a word line that selects a dummy cell connected to the bit line. In this embodiment, an open bit line structure is shown, but the same can be realized with a folded bit line structure.

Next, the operation of this embodiment will be described with reference to FIGS. In FIGS. 8 to 10, the data stored in the cell corresponding to WLm is “H” in BL10, “L” in BL11, “H” in BL12, “L” in BL13, “H” in BL20 ... BLn3. It shows when it is "L".

FIG. 8 shows a timing chart during normal operation. After activating WLm, φt0,
/ Φt0 is set to "H", and BLk1, / BLk1 (k = 1 to 1
The data sent to n) is sent to SAk (k = 1 to n). Thereafter, φt0 and / φt0 are set to "L" in order to disconnect the sense amplifier from the bit line. Then, the sense amplifier is driven to read the data output to BLk0 and / BLk0 (k = 1 to n) to SAk (k = 1 to n). Then, the data is stored in the restore cell RCk0, and the bit line in the sense amplifier and the complementary bit line are equalized.

Thereafter, φt1, / φt1 to φt3, / φ
The same operation is performed for t3, and BLk1, / BLk1 ...
The data output to BLk3, / BLk3 (k = 1 to n) is S
The data is stored in the restore cells RCk1 to RCk3 of Ak (k = 1 to n). After that, .phi.t0 to .phi.t4 are set to "H" to equalize all the bit lines. After that, the data stored in RCk3 is read by SAk, φt3, / φt3 is set to "H", and written in BLK3, / BLK3, φt3,
Set / φt3 to "L". After that, φt2, / φt2 ~
Similar operations are performed for φt0 and / φt0, and RCk2
Data from ~ RCk0 to BLk2, / BLk2 ~ BLk0, / BL
Write back to k0 (k = 1 to n).

In this way, BLk0 to BLk3, / BL
The data of k0 to BLk3 (k = 1 to n) is read by SAk and written to BLk0 to BLk3, / BLk0 to BLk3, so the address of the data in the column direction does not move.

FIGS. 9 and 10 show the case where the column address of data is moved. FIG. 9 shows BLk (k = 1 to n)
This is the case of moving the data of BLk-1 to BLk-1 (moving the data of BL10 to BLn4).
This is the case of moving to k + 1 (moving the data of BLn4 to BL10).

In FIG. 9, after activating WLm, φt0
, / Φt0 to "H", BLk1, / BLk1 (k = 1
To n) are sent to SAk (k = 1 to n). Thereafter, φt0 and / φt0 are set to "L" in order to disconnect the sense amplifier from the bit line. Then, the sense amplifier is driven to read the data output to BLk0 and / BLk0 (k = 1 to n) to SAk (k = 1 to n). Then, the data is stored in the restore cell RCk0, and the bit line in the sense amplifier and the complementary bit line are equalized.

After that, φt1, / φt1 to φt3, / φ
The same operation is performed for t3, and BLk1, / BLk1 ...
The data output to BLk3, / BLk3 (k = 1 to n) is S
The data is stored in the restore cells RCk1 to RCk3 of Ak (k = 1 to n). After that, .phi.t0 to .phi.t4 are set to "H" to equalize all the bit lines. After that, the data stored in RCk3 is read by SAk, φt2, / φt2 is set to "H", and written in BLk2, / BLk2, φt3,
Set / φt3 to "L". After that, the data stored in RCk2 is read, the same operation is performed for φt1 and / φt1, and the data stored in RCk1 is read to obtain φ
The same operation is performed for t0 and / φt0. When the data stored in RCk0 is read out, φt4, / φt
The same operation is performed for 4.

In this way, BLk0 to BLk3, / BL
The data of k0 to BLk3 (k = 1 to n) is read by SAk, and BLk-13, BLk0 to BLk2, / BLk-13, BLk0.
Written to ~ BLk2.

In FIG. 10, after activating WLm, φt
4, / φt4 is set to "H" and BLk1, / BLk1 (k = 1
To n) are sent to SAk-1 (k = 1 to n). Thereafter, φt4 and / φt4 are set to "L" in order to disconnect the sense amplifier from the bit line. After that, drive the sense amplifier to BLk3, / BLk3 (k = 1 to n)
Then, the data output to Sk + 1 (k = 1 to n) is read. After that, the data is stored in the restore cell RCk0,
The bit lines in the sense amplifier and the complementary bit lines are equalized.

After that, φt0, / φt0 to φt2, / φ
The same operation is performed for t2, and BLk1, / BLk1 ...
The data output to BLk3, / BLk3 (k = 1 to n) is S
The data is stored in the restore cells RCk1 to RCk3 of Ak (k = 1 to n). After that, .phi.t0 to .phi.t4 are set to "H" to equalize all the bit lines. After that, the data stored in RCk3 is read by SAk, φt3, / φt3 is set to "H", and written in BLk3, / BLk3, φt3,
Set / φt3 to "L". After that, φt2, / φt2 ~
The same operation is performed for φt0 and / φt0, and RC
The data stored in k2 to RCk0 is read by SAk and B
Write to Lk2 to BLk0, / BLk2 to BLk0.

In this way, BLk-13, BLk0 to BLk
The data of k2, / BLk-13, BLk0 to BLk2 (k = 1 to n) is read out by SAk, and BLk0 to BLk3, / BLk0.
To BLk3.

As described above, according to the present embodiment, the bit line BLk (k = 1 to n) and the sense amplifier SAk (k = 1).
.About.n + 1) by shifting the connection state of the switching elements between when the data is read from the bit line to the sense amplifier and when the data read by the sense amplifier is written to the bit line. The addresses can be shifted one by one.

The present invention is not limited to the above embodiment. In the embodiment, it is considered that the switching element connected to the two bit lines adjacent to each other by shifting is provided. However, the number of bit lines shifted to and connected to one sense amplifier is set to three or more. Good. This has the advantage that the address of the data in the column direction can be moved even after reading the data. Further, the number of shifts is not limited to one next to each other, but n (n> 1) or adjacent ones can shift n addresses in the column direction of data at a time. In addition, various modifications can be made without departing from the scope of the present invention. (Embodiment 3) FIG. 11 shows a circuit configuration of a semiconductor memory device according to a third embodiment of the present invention. As with the second embodiment, one sense amplifier is composed of four bit lines. This is an example in the case of sharing.

In FIG. 11, BL10 to BLn3 are bit lines to which a plurality of cells are connected, and / BL10 to / BL.
n3 is its complementary bit line. BLkl, / BLkl (l =
0 to 3) are bit lines connected to the same sensor amplifier SAk.

SA1 to SAn are sense amplifiers for reading and writing the data output to the bit lines. SAk (k = 1 to n) also includes register cells RCk0 to RCk3 for temporarily storing the read data. P04, P05, P10 to Pn4, / P04, / P05, /
P10 to / Pn4 are switching elements for connecting the sense amplifier and the bit line with nMOS transistors, and Pkm,
/ Pkm (k = 0 to n) (m = 0 to 3) is φtm, / φ
Activated by tm.

When φt4 is "H", BLkl, / BL
kl (k = 1 to n) (l = 0 to 3) is SAk-1 (k = 1 to 1)
n) and φt5 is "H", BLkl, /
BLkl (k = 1 to n) (l = 0 to 3) is SAk (k = 1)
~ N). BLk when φt1 is "H"
l, / BLkl (k = 1 to n) (l = 0 to 3) are connected to the sense amplifier.

WLm is one of the word lines for selecting cells connected to the bit lines. The circles in the figure are memory cells. DWL is a word line that selects a dummy cell connected to the bit line. In this embodiment, an open bit line structure is shown, but the same can be realized with a folded bit line structure.

Next, the operation of this embodiment will be described. The timing chart during normal operation is the same as in Fig. 4,
.phi.t5 is "H" and .phi.t4 is "L". FIG. 12 shows a case of performing a move to decrease the column address of data by two.
Shown in. That is, BLk (k = 1 to n) data is BLk-
This is the case of moving to 2 (k = 1 to n). The data stored in the cell corresponding to WLm is “H” in BL10, BL
11 is "L", BL12 is "H", BL13 is "L", BL20
"L", BL21 is "H", BL22 is "L", and BL23 is "H".

At the same time that WLm is activated, φt5 is set to "H" and φt4 is set to "L" to set BLkl, / BLkl (k
= 1 to n) (l = 0 to 3) are connected to SAk (k = 1 to n). Thereafter, .phi.t0 and /.phi.t0 are set to "H", and the data output to BLk1 and / BLk1 (k = 1 to n) are sent to SAk (k = 1 to n). afterwards,
To disconnect the sense amplifier from the bit line φt0, /
φt0 is set to "L". Then, the sense amplifier is driven to read the data output to BLk0 and / BLk0 (k = 1 to n) to SAk (k = 1 to n). Then, the data is stored in the restore cell RCk0, and the bit line in the sense amplifier and the complementary bit line are equalized.

Thereafter, φt1, / φt1 to φt3, / φ
The same operation is performed for t3, and BLk1, / BLk1 ...
The data output to BLk3, / BLk3 (k = 1 to n) is S
The data is stored in the restore cells RCk1 to RCk3 of Ak (k = 1 to n). After that, .phi.t0 to .phi.t5 are set to "H" to equalize all bit lines.

After that, φt5 is set to "H" and φt4 is set to "L" again, and BLkl, / BLkl (k = 1 to n) (l = 0
3) are connected to SAk (k = 1 to n). After that, the data stored in RCk3 is read by SAk, φt1 and / φt1 are set to "H", and BLk2 and / B are set.
Write to Lk2 and set φt1 and / φt1 to "L". After that, the data stored in RCk2 is read and φt0,
The same operation is performed for / φt0. After this, φt5
To "L" and φt4 to "H" to set BLkl, / BLkl
(K = 1 to n) (l = 0 to 3) is SAk-1 (k = 1 to 1)
n). After that, the data stored in RCk1 is read and the same operation is performed for φt3 and / φt3. When the data stored in RCk0 is read, the same operation is performed for φt2 and / φt2.

In this way, BLk0 to BLk3, / BL
The data of k0 to BLk3 (k = 1 to n) is read by SAk, and BLk-12, BLk-13, BLk0, BLk1, / BLk-.
Written to 12, / BLk-13, / BLk0, / BLk1.

In the present embodiment, the case where the data column address is decreased by two has been described, but φt4 and φt5 are described.
By changing "H" and "L" of the above, it is possible to increase or decrease the address in the column direction up to the number of bit lines sharing one sense amplifier.

In this way, the bit lines BLk (k = 1 to 1
n) and the sense amplifier SAk (k = 1 to n + 1), the connection state of the switching element is shifted between when the data is read from the bit line to the sense amplifier and when the data read by the sense amplifier is written to the bit line. This makes it possible to shift the column-direction address of one group of data up to the number of bit lines sharing one sense amplifier at a time.

The present embodiment has an advantage that the added φt gate enables movement of various column addresses, although it is small compared to the embodiments of FIGS. 2 and 7, but one bit line is used. It also has a drawback that the number of φt gates connected to is increased.

The present invention is not limited to the above embodiment. In the embodiment, one adjacent sense amplifier 2
Although it has been considered that the switching elements are provided so as to be shifted and connected to each other, a switching element capable of shifting between two or more sense amplifiers may be provided. This has the advantage that the address of the data in the column direction can be moved even after reading the data. Also,
The number of shifts is not limited to one next to each other, but n (n> 1) or next to each other so that the address in the column direction of the data is n * at one time (the number of bit lines sharing one sense amplifier).
You can shift them individually. In addition, various modifications can be made without departing from the scope of the present invention. (Embodiment 4) FIG. 13 is a diagram showing a circuit configuration of a semiconductor memory device according to a fourth embodiment of the present invention.

In FIG. 13, BL1 to BLn are bit lines to which a plurality of cells are connected, and / BL1 to / BL.
n is its complementary bit line. SA1 to SAn are sense amplifiers for reading and writing the data output to the bit lines. P10 to Pn2, / P10 to / Pn2 are
A switching element that connects a sense amplifier and a bit line with an nMOS transistor. Pkm, / Pkm (k = 1 to
n) (m = 0, 1) is activated by φtm, / φtm.

Φt0, φt1 and BL1 to BLn, / BL
The connection relationship between 1- / BLn and SA is the same as in FIG. The difference from FIG. 2 is that the bit lines having the preceding and succeeding column addresses correspond to the two bit lines that are two adjacent in position.
With respect to the bit line at the bottom end of the first bit line, bit lines having preceding and succeeding column addresses are made to correspond to the bit line adjacent in position and two bit lines adjacent to each other. By doing this, when shifting data between the bit lines having the first and last column addresses, the length of the wiring connecting the bit line and the sense amplifier is shortened, and the difference due to the column address is the most important. Can be reduced.

In this embodiment, the open bit line structure is shown, but the same can be realized with the folded bit line structure. (Embodiment 5) FIG. 14 is a diagram showing a circuit configuration of a semiconductor memory device according to a fifth embodiment of the present invention.

In FIG. 14, BL1 to BLn are bit lines to which a plurality of cells are connected, and / BL1 to / BL
n is its complementary bit line. SA1 to SAn are sense amplifiers for reading and writing the data output to the bit lines. SN1 to SNn, / SN1 to SNn
Are independent nodes in the sense amplifier. This sense amplifier node has a temporary storage register cell for storing data, and its word line is RW.
L and / RWL.

P10, P11, ~ Pn0, Pn1, / P10, / P
11, ~ / Pn0, / Pn1 are switching elements for connecting sense amplifiers and independent nodes in the sense amplifiers with nMOS transistors, and Pk0, / Pk0 (k = 1 to n)
Is activated by φt0 and / φt0, and Pk1 and / Pk1
(K = 1 to n) is activated by φt1 and / φt1. When φt0 and / φt0 are "H", SNk and / S
Nk (k = 1 to n) is connected to SAk (k = 1 to n), and when φt1 and / φt1 are "H", SNk and /
SNk (k = 1 to n) is connected to SAk-1 (k = 1 to n).

P12 to Pn2 and / P12 to Pn2 are switching elements for connecting the bit line and the sense amplifier node by nMOS transistors, and BL is set when φt2 is set to "H".
k (k = 1n) and SNk are connected.

Although the open bit line structure is shown in FIG. 14, the same can be realized by the folded bit line structure. Next, the operation of this embodiment will be described with reference to FIG. In FIG. 15, the data stored in the cell corresponding to WLm is “H” in BL1, “L” in BL2, and B.
"H" for L3, "L" for BL4 ... "H" for BL2l + 1, B
L2l + 2 indicates the case of "L" (l = 1 to 1
n). FIG. 15 shows the data of BLl (l = 1 to n) as BL
This is the case when moving to lk.

After activating WLm, φt0 and / φt0
Is set to "H", and the data sent to BLk1, / BLk1 (k = 1 to n) is sent to SAk (k = 1 to n). After that, in order to disconnect the sense amplifier from the bit line, φt2
, / Φt2 to "H", and BLk1, / BLk1 (k = 1
To n) are sent to SAk (k = 1 to n). Φt to disconnect the sense amplifier from the bit line
2, / φt2 is set to "L". Then, the sense amplifier is driven to read the data output to BLk0 and / BLk0 (k = 1 to n) to SAk (k = 1 to n). After driving SAk, RWL is raised and lowered to store data in the restore cell RCk (k = 1 to n).

Thereafter, φt0, φt1, / φt0, / φ
By setting t1 to "H", the bit lines in all the sense amplifiers and the complementary bit lines are equalized. By the operation up to this point, BLk data is read by SAk (k = 1 to n), and
Stored in a restore register with Nk. After that, the following operation is repeated k ′ times, whereby SNk ″ (k ″ = 1 to
n) shifts the data stored in SNk "-k '. This operation is marked as A in FIG.

First, φt0 and / φt0 are set to "L", φt1
, / Φt1 is "H", RWL and / RWL are raised, and then φt1 and / φt1 are set to "L" to drive the sense amplifier. After that, RWL and / RWL are lowered and φt1
, / Φt1, φt0, / φt0 are set to "H" and EQL
To "H" to equalize the bit lines in the sense amplifier.

Up to this point is the operation A, and this operation causes S
The data of Nl (l = 1 to n) is read by SAl, and S
Written to Nl + 1 restore register. By repeating this operation k'times, the data of SNl can be shifted to SNl-k. After repeating this operation,
φt0 and / φt0 are set to "H", φt1 and / φt1 are set to "L", φt2 and / φt2 are set to "H", and SN is set.
Write the data of l to BLl.

As described above, according to this embodiment, the sense amplifier internal node SNk (k = 1 to n) and the sense amplifier S are connected.
Shifting the connection state of the switching element that connects Ak (k = 1 to n + 1) between when the data is read from the sense amplifier internal node to the sense amplifier and when the data read by the sense amplifier is written to the sense amplifier internal node. By this, it is possible to shift some addresses of a group of data in the column direction without charging and discharging the bit lines. It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be carried out without departing from the scope of the invention.

[0070]

As described above in detail, the present invention (Claim 1)
According to the method, the connection state of the switching element that connects the bit line and the sense amplifier can be determined by reading the data from the bit line to the sense amplifier and writing the data read by the sense amplifier to the bit line by an external signal or the like. Can be shifted. As a result, the column address can be changed at a time without taking out a group of data to the outside of the sense amplifier.

Further, the bit lines corresponding to the preceding and succeeding column addresses are positionally made into two bit lines, and the bit line corresponding to the preceding and succeeding column addresses is made into the bit line adjacent to the last two. By doing so, the bit line corresponding to the largest column address and the bit line corresponding to the smallest column address can be two, and the bit lines corresponding to the preceding and succeeding column addresses can be connected, Moreover, when connecting the bit lines corresponding to the largest column address and the smallest column address, the wiring distance can be made uniform and the smallest.

According to the present invention (claim 2), the connection state of the switching element for connecting the sense amplifier internal node and the sense amplifier is determined when data is read from the sense amplifier internal node to the sense amplifier by an external signal or the like. When,
It is possible to shift the time when writing the data read by the sense amplifier to the node inside the sense amplifier. As a result, the column address can be changed at a time without taking out a group of data to the outside of the sense amplifier and charging / discharging the bit line.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a semiconductor memory device according to a first embodiment.

FIG. 2 is a circuit configuration diagram showing an example in which the first embodiment is configured with an open bit line structure.

FIG. 3 is a circuit configuration diagram showing an example in which the first embodiment is configured with a folded bit line structure.

FIG. 4 is a timing chart for explaining the operation of the first embodiment.

FIG. 5 is a timing chart for explaining the operation of the first embodiment.

FIG. 6 is a timing chart for explaining the operation of the first embodiment.

FIG. 7 is a diagram showing a circuit configuration of a semiconductor memory device according to a second embodiment.

FIG. 8 is a timing chart for explaining the operation of the second embodiment.

FIG. 9 is a timing chart for explaining the operation of the second embodiment.

FIG. 10 is a timing chart for explaining the operation of the second embodiment.

FIG. 11 is a diagram showing a circuit configuration of a semiconductor memory device according to a third embodiment.

FIG. 12 is a timing chart for explaining the operation of the third embodiment.

FIG. 13 is a diagram showing a circuit configuration of a semiconductor memory device according to a fourth embodiment.

FIG. 14 is a diagram showing a circuit configuration of a semiconductor memory device according to a fifth embodiment.

FIG. 15 is a timing chart for explaining the operation of the fifth embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Memory cell array 2 ... Switching element (transfer gate) 3 ... Sense amplifier (also equalize gate) 11 ... Address movement signal receiving circuit 12 ... φt gate control circuit 13 ... Transfer sequence control circuit BL1, ..., BLn ... Bit line / BL1 , ~, / BLn ... Complementary bit lines SA1, ~, SAn ... Sense amplifiers P10, ~, Pn1, / P10, ~, / Pn1 ... nMOS transistor WLm ... Word line DWL ... Dummy word line

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kenichi Maeda No. 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Within the Corporate Research and Development Center, Toshiba Corporation (72) Mitsuo Saito Komukai-Toshiba, Saiwai-ku, Kawasaki-shi, Kanagawa Town No. 1 Toshiba Corporation Research & Development Center

Claims (2)

[Claims] 1. A semiconductor memory device having a plurality of bit lines to which a plurality of memory cells are connected, and a plurality of sense amplifiers for reading data from the memory cells, wherein the sense amplifier is used in a specific mode, A semiconductor memory device comprising: a switching element that shifts and connects a bit line having a predetermined column address to a bit line having one or more column addresses before or after the column address. 2. A semiconductor memory device having a plurality of bit lines to which a plurality of memory cells are connected and a plurality of sense amplifiers for reading data of the memory cells, wherein a node is provided for each sense amplifier. A switching element is provided which shifts and connects the sense amplifier in a specific mode from a sense amplifier node having a predetermined column address to a sense amplifier node having a column address before or after one or more column addresses. A semiconductor memory device characterized by the above.