JPH07245567A - Viterbi decoding arithmetic unit - Google Patents

Abstract

PURPOSE:To simplify the configuration and to increase the speed by normalizing plural branchmetric values and adding the result to a pathmetric value so as to obtain a succeeding pathmetric value. CONSTITUTION:An ACS(adder comparison selection) section 11 is made up of a branchmetric calculation circuit 14, a normalizing circuit 15, and an ACS circuit 16 to generate a pathmetric and a path selection signal depending on input data. The branchmetric calculation circuit 14 generates a branchmetric based on input data (envelope information) and reliability information. Furthermore, the normalization circuit 15 implements normalizing by subtracting a minimum value from the branchmetric supplied from the branchmetric calculation circuit 14. Then an ACS circuit 16 adds the result to the received normalizing branchmetric to obtain a pathmetric for a next stage. Furthermore, an MLD (maximum discrimination) circuit 13 decodes data based on the pathmetric fed from the ACS circuit 16 and the content of a path memory circuit 12 to provide an output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Viterbi decoding arithmetic unit, and more particularly to a soft decision type Viterbi decoding arithmetic unit.

The Viterbi algorithm has attracted attention as a method for performing error correction decoding. The Viterbi algorithm has a hard decision method and a soft decision method. Among them, the soft decision method that enables high-level decision is attracting attention.
There is a demand for implementation in a DSP (Digital Signal Processor) or the like. However, in the soft decision method of the Viterbi algorithm, the dynamic range of the value to be processed is large, which makes it difficult to realize LSI and DSP.

Therefore, in order to make the soft decision method of the Viterbi algorithm into LSI or DSP, it is necessary to reduce the dynamic range of the processed data.

[0004]

2. Description of the Related Art FIG. 9 shows a block diagram of a conventional Viterbi decoding circuit. The conventional Viterbi decoding circuit mainly includes an ACS (addition / comparison / selection) unit 31, a path memory circuit 32, and an MLD circuit 33.

The ACS unit 31 comprises a branch metric calculation circuit 34, an ACS circuit 35, etc., and calculates a path metric. The branch metric calculation circuit 34 calculates a branch metric based on the input data and supplies it to the ACS circuit 35.

The ACS circuit 35 adds (adds) the branch metric calculated by the branch metric calculation circuit 34 to the path metric calculated one clock before, compares the added metric, and selects the optimum path ( select) is performed to supply the path metric to the MLD circuit 33 and the path memory circuit 33.
The path selection signal is stored in. The path metric and the path selection signal stored from the path memory circuit 32 are supplied to the MLD circuit 33, and the MLD circuit 33 performs trace back based on these signals to estimate the original data and restore the original data. Output.

At this time, the branch metric calculation circuit 3
In 4, the metric values MX 'and MY' are calculated based on the received data C and the data reliability BX 'and BY'. In this case, MX ', MY' is obtained by the ^{MX '= BX' * C 2} ··· (1) MY '= BY' * C 2 ··· (2).

FIG. 10 shows a diagram for explaining the reliability information. The reliability BX ′, BY ′ is composed of, for example, 3 bits, and the larger the value, the higher the reliability.

The reliability information BX, BY is the received code X
(“1”), Y (“0”), reliability BX ′, B
Y'is added.

Accordingly, the metrics MX 'and MY' in the equations (1) and (2) indicate that the larger the value, the higher the reliability.

In the hard decision system, the received signal X
The reliability of the data was determined only by ("1") and Y ("0").

As described above, conventionally, the larger the branch metric value is, the higher the reliability is, and it is necessary to sequentially add the branch metric to the path metric. At this time, a large path metric value is set as the optimum path. It is necessary to make selections, and therefore, the value to be processed becomes large, and processing with double precision was required.

[0013]

However, in the conventional soft-decision type Viterbi decoding arithmetic unit, it is said that the reliability expression is high in a large value and low in a small value. Finally, the metric value is calculated and the branch metric values are sequentially added to find the one with the largest path metric value. This is used as the optimum path metric value, so a large bit width and double precision value can be stored. A complicated accumulator is required, which complicates the configuration. Further, since the calculation is performed based on this data, it is necessary to perform processing such as double-precision loading and double-precision saving for each calculation, and these processing become enormous as the constraint length and the received signal sequence increase,
Therefore, the processing time increases and the configuration becomes complicated.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a Viterbi decoding arithmetic device having a relatively simple structure and capable of performing arithmetic operations at high speed.

[0015]

FIG. 1 shows a block diagram of the principle of the present invention. The branch metric calculation means 1 calculates a branch metric value according to the received signal sequence. The normalizing means 2 normalizes the branch metric value calculated by the branch metric calculating means 1 based on the minimum value of the calculated branch metric values, and supplies it to the path metric calculating means. The path metric calculation unit 3 calculates a path metric value based on the branch metric value normalized by the normalization unit 2. The decoding means 4 restores the received signal by sequentially selecting a highly reliable path metric value from the path metric values calculated by the path metric calculation means 3.

[0016]

The branch metric value calculated by the branch metric calculating means is normalized by the normalizing means on the basis of the minimum branch metric value, and then supplied to the path metric calculating means. Therefore, it is possible to suppress the increase of the branch metric value and accordingly suppress the increase of the path metric value.

Therefore, an increase in the size of the constituent circuit can be suppressed, and the time required for loading and saving values can be reduced, so that the speed can be increased.

[0018]

FIG. 2 shows a block diagram of an embodiment of the present invention. In the figure, 11 is an ACS (addition comparison selection) unit, 12
Is a path memory circuit, and 13 is a maximum determination (MLD) circuit.

The ACS unit 11 is composed of a branch metric calculation circuit 14, a normalization circuit 15, and an ACS circuit 16, and generates a path metric and a path selection signal according to input data. The branch metric calculation circuit 14 generates a branch metric from input data (envelope information) and reliability information.

First, as in the conventional case, the metrics MX 'and MY' are obtained from the reliability levels BX 'and BY' and the input data C by the equations (1) and (2). If this condition is left as it is, the dynamic range is widened, so in the present embodiment, the differences KX and KY from the maximum value MAX of the metrics MX ′ and MY ′ are next.
Ask for.

KX = MAX−MX ′ (3) KY = MAX−MY ′ (4) The differences KX and KY change from MAX to 0, and the metric M
The relationship of reliability is reversed from that of X ′ and MY ′. The larger KX and KY, the lower the reliability, and the smaller the value, the higher the reliability.

Next, a branch metric is calculated based on KX and KY. The branch metric is obtained from the reference data and the received signals X and Y.

FIG. 3 is an explanatory diagram of the method of calculating the metric value.
Show. The branch metric value is "0" when the received signal is
When the reference data is "0", K_Y, Receive
The signal is "0" and the reference data is "1"
When (MAX-K_Y), The received signal is "1",
When the reference data is “0”, (MAX-K
_X), The received signal is "1" and the reference data
When is “1”, K_XBecomes By the above
And the metric value is determined. In this embodiment, it is shown in FIG.
The branch metric is based on the metric value calculation method
It is calculated.

FIG. 4 shows the branch metric calculation circuit 14
The operation | movement explanatory drawing is shown. The received sequence is the received code
The data string is an array of reference data.
The branch metric value corresponding to the received sequence
Each received code and the corresponding reference code
The metric value calculated based on Fig. 3 according to the data
It is calculated by adding In FIG. 4, the bra
Ntimetric value BR ₀Indicates the minimum value.

The branch metric value calculated by the branch metric calculation circuit 14 is supplied to the normalization circuit 15 for normalization. The normalization circuit 15 receives the branch metric value BR ₀ supplied from the branch metric calculation circuit 14.
Normalization is performed by subtracting the minimum value BR ₀ from ˜BR ₃ .

FIG. 5 shows an operation explanatory diagram of the normalization circuit. Positive
The normalization circuit 15 uses the branch metric value BR shown in FIG.₀
~ BR₃To the minimum value of BR₀The value obtained by subtracting
Branch metric value BR₀’～ BR₃Output as'
To do. Therefore, the minimum value BR ₀'Is always "0",
Normalized branch metric value BR₀’～ BR₃’Is regular
Unbranched branch metric value BR₀~ BR₃Yo
Can be made smaller.

The branch metric values BR ₀ ′ to BR ₃ ′ normalized by the normalization circuit 15 are supplied to the ACS circuit 16. The ASC circuit 16 adds the supplied normalized branch metric value to the corresponding path metric value to obtain the path metric value of the next stage.

At this time, since the branch metric value is calculated so that the smaller value has higher reliability,
Smaller values are sequentially clipped, and the minimum path metric value is finally obtained.

FIG. 6 is a diagram for explaining the path metric updating operation. FIG. 7 shows an example in which the path metric has 32 states.

In the (m-1) thus far obtained, 32 of each path metric pathz (m-1) are ASC circuits 16
It is stored inside.

In Viterbi decoding, path metric values are obtained for the number of reception sequences. Path metric path00000 (m-1), path100 of a certain m-1
PATH0: path00000 (m-1) + BRX (5) PATH1: path10000 (m-1) + BRY (6) PATH0: path00000 (m-1) + BRX (5) Show.

The minimum value is selected from the path metric values obtained by the equations (5) and (6), and the path000 at m is selected.
The state is transited to 000 (m).

FIG. 7 shows an operation explanatory diagram of the state transition. The data Z indicating the state is held in the shift register, for example. path00000 (m-1) to path000
The state transition to 00 (m) is performed by the data Z "0000 indicating the state held in the shift register as shown in FIG.
Input "0" from the lower side of "0." The contents of the shift register shift to the left, but "0" is input and "0" is only ejected and does not change.

As for the state transition from path10000 (m-1) to path00000 (m), as shown in FIG. 7B, data indicating the state held in the shift register is read from the lower side of "10000" to "0". By inputting "", "1" is pushed out to the upper side and "00000" is obtained.

As described above, there are two types of transition sources for all transitions to each state.

The ACS circuit 16 supplies the generated path metric value to the MLD circuit 13 and updates the path memory circuit 12 in which the data indicating the surviving path is stored.

The MLD circuit 13 restores the data from the path metric value supplied from the ACS circuit 16 and the contents of the path memory circuit 12, and outputs it.

FIG. 8 shows an operation explanatory diagram of one embodiment of the present invention. When performing Viterbi decoding, first, the circuit is initialized and the contents of the register, memory, etc. are cleared (step S1).

After the initialization, the received data is taken into the branch metric calculation circuit 1 and the branch metric is calculated based on the received data as described later (step S2).

Next, the branch metric calculated in step S2 is normalized as described later (step S
3).

The normalized branch metric normalized in step S3 is supplied to the ASC circuit 16 and added to the path metric calculated in the previous calculation in the ASC circuit 16 to calculate the current path metric, and the MLD circuit 13 is calculated. (Step S4).

Next, the minimum path metric is calculated from the path metric calculated in step 4, and a selection signal is generated as an optimum path and stored in the path memory circuit 12 (step S5).

Steps S2 to S5 are performed N times (N: number of states)
It is executed (step S6), and is executed M times (M = (the number of encoded decoded data) + L [L: N = 2 ^{L in the} number of stages of the number of states]) (step S7).

Next, the MLD circuit 13 performs traceback based on the path metric and the minimum path determination data obtained above to reproduce the original data and output it (step S8).

As described above, according to this embodiment, since the branch metric is normalized, it is possible to suppress an increase in the path metric value generated by adding the branch metric,
As a result, the dynamic range can be set small, and therefore the circuit scale can be made small.

Further, due to the reduction of the dynamic range, the processing such as loading and saving of data from the memory or the like can be performed at high speed, and therefore the entire processing of Viterbi decoding can be performed at high speed.

Furthermore, even if the minimum value of the path metric is determined and the path is calculated to be the optimum path, even if the value overflows during the calculation of the path metric, this does not become the optimum path. If this is done, it will not affect the characteristics at all.

Further, since the calculation value does not increase due to the normalization and the judgment with the minimum value, the calculation with the single precision value becomes possible, and the application to LSI, DPS, etc. becomes easy.

[0049]

As described above, according to the present invention, since a plurality of branch metric values are normalized and then added to the path metric value to obtain the next path metric value, an increase in the path metric value can be suppressed. Therefore, the processing can be performed easily, the configuration can be simplified, and the speed can be increased.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a block diagram of an embodiment of the present invention.

FIG. 3 is a diagram for explaining a metric calculation method according to an embodiment of the present invention.

FIG. 4 is an operation explanatory diagram of a branch metric calculation circuit according to an embodiment of the present invention.

FIG. 5 is an operation explanatory diagram of a normalization circuit according to an embodiment of the present invention.

FIG. 6 is an explanatory diagram of a path metric updating operation.

FIG. 7 is a diagram for explaining state transitions.

FIG. 8 is an operation explanatory diagram of the embodiment of the present invention.

FIG. 9 is a configuration diagram of a conventional example.

FIG. 10 is a diagram for explaining reliability information.

[Explanation of Codes] 1 branch metric calculation means 2 path metric calculation means 3 selection means 4 normalization means

Claims (2)

[Claims] 1. A branch metric calculating means (1) for calculating a branch metric value according to a received signal sequence, and the branch metric value calculated by the branch metric calculating means (1) is a minimum value of the branch metric values. The path metric value is calculated according to the normalization means (2) supplied to the path metric calculation means (3) and the branch metric value normalized by the normalization means (2). Path metric calculating means (3), and decoding means (4) for restoring the received signal by sequentially selecting a highly reliable path metric value from the path metric values calculated by the path metric calculating means (3). A Viterbi decoding operation device comprising: 2. The branch metric calculation means (1)
Calculates the branch metric value so that the value with high reliability becomes the minimum, and the decoding means (4) selects the minimum value of the path metric values calculated by the path metric calculation means (3). The Viterbi decoding arithmetic unit according to claim 1, wherein the received signal is restored by performing the above.