JPH07245316A - Heterojunction bipolar transistor and its manufacture - Google Patents

Abstract

PURPOSE:To provide an HBT which is high in operating speed, low in power consumption, and has excellent element characteristics by reducing the thickness of an intrinsic base layer under high controllability and reducing the sheet resistance and contact resistance of an external base layer. CONSTITUTION:A p<+>-type GaAs intrinsic base layer 22, n-type Al0.25Ga0.75As emitter layer 24, etc., are successively formed on the central part of an n-type GaAs collector layer 14. In addition, a p<+>-type GaAs external base layer 18 is formed on the collector layer 14 around the base layer 22 with an n-type InGaP etching stopper layer 16 in between. The base layer 22, emitter layer 24, etc., etc., are regrown on the collector layer 14 exposed by selectively etching the base layer 18 by utilizing the etching stopper layer 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a hetero-junction bipolar transistor.
HBT) and the manufacturing method thereof.

[0002]

2. Description of the Related Art An HBT that uses a semiconductor with a wide bandgap as an emitter has high emitter injection efficiency and high current gain, and can maintain a high current gain while reducing the base resistance. It is excellent and enables ultra-high-speed digital processing that could not be achieved with conventional semiconductor devices. In the field of ultra-high-speed communication, its high performance has already been demonstrated, and its practical application is expected.

However, when considering application to an integrated circuit, power consumption becomes a problem, and how to miniaturize the device, operate the device with a small current, and bring out its high speed further is a problem. Regarding miniaturization, the current HB
Since T has a mesa structure, it is difficult to process the emitter width of 1 μm or less, and further miniaturization is difficult. As for high speed, the HBT can set the base concentration higher by about one digit than the normal bipolar transistor.
It is possible to achieve both the reduction of the base running time and the reduction of the base resistance due to the thin base layer, which are usually in a trade-off relationship. For this reason, it has a high speed, but there is a limit to increasing the concentration of the base, and it is difficult to further increase the speed with the current structure.

Therefore, H using regrowth is one means for solving these technical problems of the present structure.
BT is drawing attention. Hereinafter, a method for manufacturing an HBT using regrowth as an external base will be described with reference to FIG. On a semi-insulating GaAs substrate 50, n ⁺ -GaAs subcollector layer 52, n-GaAs collector layer 54, p-GaA
s base layer 56, n-AlGaAs emitter layer 58, n
⁺ −GaAs emitter cap layer 60, WSi layer 62,
And the SiO ₂ layer 64 are sequentially formed.

Subsequently, a resist film is applied on the SiO ₂ layer 64 and then patterned into a predetermined shape. Then, using this patterned resist film as a mask,
SiO ₂ layer 64, WSi layer 62, n ⁺ -GaAs emitter cap layer 60, and n-AlGaAs emitter layer 5
8 is mesa-etched to expose the n-AlGaAs emitter layer 58. After that, the resist film is removed (see FIG. 13A).

Next, the remaining n-AlGaAs emission
The plasma layer 58 and the p-GaAs base layer 56 by mesa etching.
To expose the n-GaAs collector layer 54. Continued
And the entire surface is SiO₂After depositing layer 66, selectively
The remaining n-AlGaAs EMI is obtained by performing isotropic etching.
The surface of the solder layer 58 is exposed and the mesa-like SiO ₂
Layer 64, WSi layer 62, n⁺-GaAs emitter cap
Side of the n-AlGaAs emitter layer 58
SiO on the wall and on the n-GaAs collector layer 54₂layer
66 is left (see FIG. 13 (b)).

Then, the SiO ₂ layer 64 and the SiO ₂ layer 6 are formed.
N-AlGaAs emitter layer 58 and p-GaAs base layer 56 are selectively etched using 6 as a mask,
The GaAs collector layer 54 is exposed. Then, p ⁺ -GaA is formed on the exposed n-GaAs collector layer 54.
s The external base layer 68 is selectively regrown. And this p ⁺
A Ti / Pt / Au base electrode 70 is formed on the GaAs extrinsic base layer 68. Also, by H ion implantation,
A device isolation region 72 is formed to reach the semi-insulating GaAs substrate 50 from the n-GaAs collector layer 54 to perform device isolation (see FIG. 13C).

Then, the SiO ₂ layer 66 and n-GaAs are formed.
By selectively etching the collector layer 54, n ⁺ -GaAs
After exposing the sub-collector layer 52, the exposed n ⁺
-On the GaAs subcollector layer 52, AuGe / Ni /
The Au collector electrode 74 is formed. Subsequently, after depositing a SiO ₂ layer 76 as a passivation film on the entire surface, W
The SiO ₂ layer 76 and the SiO ₂ layer 64 on the Si layer 62 are selectively etched to form Ti / Ti on the exposed WSi layer 62.
A Pt / Au emitter electrode 78 is formed (FIG. 13D).
reference). Thus, the HBT is completed.

As described above, by selectively re-growing the p ⁺ -GaAs extrinsic base layer 68, the p ⁺ -G is independent of the characteristics of the intrinsic base region of the p-GaAs base layer 56.
The aAs external base layer 68 can be set thick and highly concentrated. Therefore, p-G that forms the intrinsic base region
Even if the aAs base layer 56 is thinned, the sheet resistance of the p ⁺ -GaAs extrinsic base layer 68 does not increase, and p
^{Even if} the concentration of the ⁺ -GaAs external base layer 68 is increased to the limit, the current gain or the like is not affected at all. Therefore, the reduction of the base running time and the reduction of the base resistance can be achieved at the same time.

However, even in the above-mentioned conventional HBT in which the p ⁺ -GaAs extrinsic base layer 68 is regrown, since it has a mesa structure, there is a certain limit to miniaturization. Therefore, an HBT using regrowth for the emitter has been proposed (see Japanese Patent Laid-Open No. 2-168629). Less than,
A method of manufacturing this HBT will be described with reference to FIG. n
^{On the +} -GaAs substrate 80, the n ⁺ -GaAs buffer layer 82, the n-GaAs collector layer 84, and the p-GaAs are provided.
The base layer 86 is sequentially formed (see FIG. 14A).

Next, after forming the PAS film 88 on the entire surface, an opening is formed by selective etching. The p-GaAs base layer 86 in this opening is etched to a predetermined depth. Subsequently, the exposed p-GaAs base layer 86 is heated by raising the temperature to 720 ° C. or higher while irradiating As.
The surface is thermally etched to form a clean base layer surface (see FIG. 14 (b)).

Next, an n-AlGaAs emitter layer 90 and an n ⁺ -GaAs emitter cap layer 92 are sequentially regrown on the entire surface. At this time, the p-GaAs base layer 90
The upper recrystallized crystal becomes a single crystal, and the recrystallized crystal on the PAS film 88 becomes a high resistance polycrystal (see FIG. 14C). Then, after removing the high-resistance polycrystal on the PAS film 88, a photolithography technique and a lift-off technique are used to n.
^An emitter electrode 94 is formed on the ⁺ -GaAs emitter cap layer 92, and a base electrode 96 is formed on the p-GaAs base layer 86.
A collector electrode 98 on the n-GaAs collector layer 84.
Are respectively formed (see FIG. 14D). Thus, the HBT is completed.

Thus, the n ⁺ -GaAs buffer layer 8
2 to a p-GaAs base layer 86 having a large layer thickness in this order, the portion to be an emitter region is etched to thin the p-GaAs base layer 86, and the p-GaAs base layer 86 is thinned.
By regrowth of the n-AlGaAs emitter layer 90 on the s base layer 86, the intrinsic base region of the p-GaAs base layer 86 can be thinned and the extrinsic base region can be thickened. Therefore, it is possible to achieve the reduction of the base running time and the reduction of the base resistance at the same time, and it is possible to increase the speed exceeding the limit of the current structure. Further, since this structure is not a mesa structure, it is advantageous for miniaturization.

[0014]

However, in the conventional HBT using the regrowth for the above-mentioned emitter, as shown in FIG.
As shown in (b), since the thickness of the p-GaAs base layer 86 is controlled by etching, controllability and reproducibility are poor, and therefore, there is a problem that the thinning of the base is limited and speeding up is hindered. there were.

In the regrowth of the emitter, p-
Since the n-AlGaAs emitter layer 90 is regrown on the GaAs base layer 86, the emitter / base junction coincides with the regrown interface, so that the contamination of the regrown interface has a great influence on the device characteristics, such as current gain. However, there is a problem that the device characteristics are deteriorated. Therefore, in view of the above problems, the present invention thins the intrinsic base layer with good controllability, reduces the sheet resistance and contact resistance of the external base layer, and is excellent in high speed and low power consumption, and good. An object is to provide an HBT having device characteristics.

[0016]

SUMMARY OF THE INVENTION The above-described problems are formed on a collector layer, an intrinsic base layer formed on the collector layer, and the collector layer around the intrinsic base layer via an etching stopper layer. And a extrinsic base layer and an emitter layer formed on the intrinsic base layer and having a larger bandgap than the intrinsic base layer.

Further, the above problem is that a collector layer, a base layer formed on the collector layer, an intrinsic base layer formed on the base layer, and the base layer around the intrinsic base layer are provided. An external base layer formed via an etching stopper layer, and formed on the intrinsic base layer,
And an emitter layer having a bandgap larger than that of the intrinsic base layer.

Further, the above problem is that a collector layer, a base layer formed on the collector layer, an emitter layer formed on the base layer and having a bandgap larger than that of the base layer, and the periphery of the emitter layer. And a extrinsic base layer formed on the base layer via an etching stopper layer.

Further, the above heterojunction bipolar transistor is achieved by a heterojunction bipolar transistor characterized in that a sidewall layer is formed on a sidewall of the external base layer. Further, the above-mentioned problem is that a step of sequentially growing an etching stopper layer and an external base layer on a collector layer, a step of forming a mask layer patterned in a predetermined shape on the external base layer, and a mask of the mask layer. As a step of selectively etching the external base layer until the etching stopper layer is reached, and then selectively etching the exposed etching stopper layer to expose the collector layer; and And a step of sequentially growing an intrinsic base layer and an emitter layer having a bandgap larger than that of the intrinsic base layer.

Further, the above-mentioned problem is that a step of sequentially growing a base layer, an etching stopper layer and an external base layer on the collector layer, and a step of forming a mask layer patterned in a predetermined shape on the external base layer. And, using the mask layer as a mask, selectively etching the external base layer until reaching the etching stopper layer, and then selectively etching the exposed etching stopper layer to expose the base layer, And a step of sequentially growing an intrinsic base layer and an emitter layer having a bandgap larger than that of the intrinsic base layer on the exposed base layer.

Further, the above-mentioned problem is that a step of sequentially growing a base layer, an etching stopper layer and an external base layer on a collector layer, and a step of forming a mask layer patterned in a predetermined shape on the external base layer. And, using the mask layer as a mask, selectively etching the external base layer until reaching the etching stopper layer, and then selectively etching the exposed etching stopper layer to expose the base layer, A step of growing an emitter layer having a bandgap larger than that of the base layer on the exposed base layer, the method of manufacturing a heterojunction bipolar transistor.

In the method for manufacturing a heterojunction bipolar transistor, the sidewall layer is formed on the sidewall of the external base layer after selectively etching the external base layer. It is achieved by the manufacturing method of.
Further, in the above-described method for manufacturing a heterojunction bipolar transistor, it is desirable that the sidewall layer be formed before the etching stopper layer is selectively etched.

[0023]

In the present invention, the etching stopper layer is provided between the collector layer or the base layer and the external base layer, and the selective etching of the external base layer is forcibly stopped by the etching stopper layer and then exposed. By sequentially re-growing the intrinsic base layer and the emitter layer on the collector layer or the base layer, the thickness of the intrinsic base region is controlled not by etching but by crystal growth. Is dramatically improved, and it becomes possible to make the intrinsic base layer as thin as possible.

Further, since the regrowth interface becomes the base / collector junction surface or the base and is not the emitter / base junction surface which has a great influence on the device characteristics, the contamination of the regrowth interface due to the regrowth causes the emitter / base junction. It is possible to realize good device characteristics without affecting even the above. Also, the emitter-base junction area is determined not by the mesa structure but by the size of the opening formed by selective etching of the external base layer, which allows miniaturization of the device and low power consumption. It is advantageous for electricity conversion.

Further, by forming a sidewall layer on the side wall of the external base layer in the opening, the size of the opening for re-growing the intrinsic base layer and the emitter layer can be controlled, so that the emitter-base junction area can be controlled. Can be further miniaturized. Thus, according to the present invention,
HBT that can be miniaturized and has excellent high frequency characteristics
Can be easily obtained.

[0026]

EXAMPLES The present invention will be specifically described below with reference to illustrated examples. FIG. 1 shows an HB according to a first embodiment of the present invention.
It is sectional drawing which shows T. On a semi-insulating GaAs substrate 10, a 500 nm thick n ⁺ -GaAs subcollector layer 1 is formed.
2 and an n-GaAs collector layer 14 having a thickness of 500 nm is formed. And this n-GaAs collector layer 1
At the center of the 4 has a thickness of 20 nm p ⁺ -GaAs intrinsic base layer 22 is formed, on the p ⁺ -GaAs intrinsic base layer 22, n-Al _0.25 thickness 200nm
Ga _0.75 As emitter layer 24, n ⁺ -A with a thickness of 50 nm
A l _X Ga _1-X As (x = 0 to 0.25) graded layer 26 and an n ⁺ -GaAs emitter contact layer 28 having a thickness of 100 nm are sequentially formed.

A thickness of 4 nm is formed on the n-GaAs collector layer 14 around the p ⁺ -GaAs intrinsic base layer 22.
Through the n-InGaP etching stopper layer 16 of
A p ⁺ -GaAs extrinsic base layer 18 having a thickness of 500 nm and a doping concentration of about 1 × 10 ²⁰ cm ⁻³ is formed. Further, on the n ⁺ -GaAs emitter contact layer 28,
For example, an emitter electrode 30 made of AuGe / Au is formed in ohmic contact, and a base electrode 32 made of Cr / Au is formed on the p ⁺ -GaAs external base layer 18.
Is formed in ohmic contact, and a collector electrode 34 made of AuGe / Au, for example, is formed in ohmic contact on the n ⁺ -GaAs subcollector layer 12.

Also, the n ⁺ -GaAs subcollector layer 12
To the semi-insulating GaAs substrate 10, the element isolation region 36 in which ions such as O are implanted is formed, and the HBT is formed.
Element isolation. Next, a method for manufacturing the HBT of FIG. 1 will be described with reference to the process drawings shown in FIGS.

A thickness of 500 nm is formed on the semi-insulating GaAs substrate 10 by a crystal growth method such as MBE or MOCVD.
N ⁺ -GaAs subcollector layer 12, thickness 500 nm
N-GaAs collector layer 14, 4 nm thick n-In
GaP etching stopper layer 16 and thickness 500n
m, p ⁺ -GaA with a doping concentration of about 1 × 10 ²⁰ cm ^-3
s External base layer 18 is sequentially epitaxially grown (see FIG. 2A).

Then, the p ⁺ -GaAs external base layer 18 is formed.
After the SiN mask layer 20 is formed thereon, it is patterned into a predetermined shape. And this patterned SiN
Using the mask layer 20 as an etching mask, p ⁺ -GaA
s The external base layer 18 is selectively etched until it reaches the n-InGaP etching stopper layer 16 to form an opening. At this time, the n-InGaP etching stopper layer 16 functions as a stopper for selective etching of the p ⁺ -GaAs external base layer 18.

Then, the exposed n-In in the opening is exposed.
The GaP etching stopper layer 16 is selectively removed by etching to expose the n-GaAs collector layer 14 (see FIG. 2B). Then, the exposed n- in the opening
ALE (Atomic Layer E) is formed on the GaAs collector layer 14.
thickness is 20 nm by isotropic crystal growth method such as pitaxy)
The p ⁺ -GaAs intrinsic base layer 22 is selectively regrown.
Then, on the p ⁺ -GaAs intrinsic base layer 22, M
BE (Molecular Beam Epitaxy) or MOCVD (Meta
l Organic Chemical Vapor Deposition) and other crystal growth methods to obtain 200 nm thick n-Al _0.25 Ga _0.75 A
s emitter layer 24, n ⁺ -Al _x Ga _1-with a thickness of 50 nm
_X As graded layer 26, and 100 nm thick n ⁺
The GaAs emitter contact layer 28 is selectively regrown in sequence (see FIG. 3C).

Then, an emitter electrode 30 made of AuGe / Au, for example, is formed on the n ⁺ -GaAs emitter contact layer 28 by ohmic contact, and p
^{On the +} -GaAs external base layer 18, for example, Cr / Au
The base electrode 32 made of is formed in ohmic contact. Subsequently, the p ⁺ -GaAs external base layer 18 and the n-I
The upper surfaces of the nGaP etching stopper layer 16, the n-GaAs collector layer 14, and the n ⁺ -GaAs subcollector layer 12 are mesa-etched by wet etching or the like,
The n ⁺ -GaAs subcollector layer 12 is exposed, and a collector electrode 34 made of AuGe / Au, for example, is formed on the exposed n ⁺ -GaAs subcollector layer 12 by ohmic contact.

Then, by ion implantation of O or the like, n ⁺ -
Element isolation regions 36 are formed from the GaAs subcollector layer 12 to the semi-insulating GaAs substrate 10 to perform element isolation (see FIG. 3D). Thus, the HBT shown in FIG.
Is obtained. Thus, according to this example, n-GaA
An n-InGaP etching stopper layer 16 is provided between the s collector layer 14 and the p ⁺ -GaAs external base layer 18, and the p ⁺ -GaAs external base layer 18 is selectively etched by using the n-InGaP etching stopper layer 16. By selectively re-growing the p ⁺ -GaAs intrinsic base layer 22 on the exposed n-GaAs collector layer 14, the thickness of the p ⁺ -GaAs intrinsic base layer 22 is not controlled by etching. , ALE
Controllability and reproducibility are dramatically improved because they are controlled by crystal growth by the method. Therefore, no matter how thin the thickness is, it does not affect other processes such as the formation of the base electrode 32, and it is possible to reduce the thickness to the limit of device physics such as punch-through, thereby reducing the base transit time to the limit. You can

In addition, the p ⁺ -GaAs external base layer 18
Is a p ⁺ -GaAs intrinsic base layer 22 and n-Al _0.25 G
for a in terms _{of 0.75} can be doped at a high concentration regardless of the characteristics of the pn junction between the As emitter layer 24, no effect on the base transit time no matter how thick, p ⁺ -
Both the sheet resistance of the GaAs extrinsic base layer 18 and the contact resistance with the base electrode 32 can be minimized.

Further, p is formed on the n-GaAs collector layer 14.
^{Since the +} -GaAs intrinsic base layer 22 and the like are regrown and the emitter / base junction surface, which has a great influence on the device characteristics, is not used as the regrown interface, some contamination may occur at the regrown interface. Even if it occurs, it does not significantly affect the emitter-base junction, and good device characteristics can be realized.

Further, the emitter-base junction area is not determined by the mesa structure, but the SiN mask layer 2 is used.
Since it is determined by the size of the opening formed by selective etching of the p ⁺ -GaAs external base layer 18 using 0 as an etching mask, fine processing with an emitter width of 1 μm or less is easy. Therefore, the element can be miniaturized, which is advantageous in reducing power consumption.

Next, the HBT according to the second embodiment of the present invention.
Will be described with reference to FIG. FIG. 4 is a sectional view showing an HBT according to the second embodiment. The HBT shown in FIG.
The same components as those in FIG.
On the semi-insulating GaAs substrate 10, an n ⁺ -GaAs subcollector layer 12, an n-GaAs collector layer 14, and a 15-nm-thick p ⁺ -GaAs base layer 38 are sequentially formed. At the center of the p ⁺ -GaAs base layer 38, a p ⁺ -GaAs intrinsic base layer 22 having a thickness of 15 nm is formed. On the p ⁺ -GaAs intrinsic base layer 22, n-Al is formed. _0.25 Ga _0.75 As Emitter layer 2
4, an n ⁺ -Al _X Ga _{1 -X} As graded layer 26, and an n ⁺ -GaAs emitter contact layer 28 are sequentially formed.

On the p ⁺ -GaAs base layer 38 around the p ⁺ -GaAs intrinsic base layer 22, n-InG is formed.
p ⁺ -GaA via the aP etching stopper layer 16
The external base layer 18 is sequentially formed. Also, n ⁺
On the -GaAs emitter contact layer 28, an emitter electrode 30 is formed in ohmic contact with p ⁺ -GaA.
A base electrode 32 is formed on the external base layer 18 in ohmic contact with the n ⁺ -GaAs subcollector layer 1.
A collector electrode 34 is formed on the electrode 2 in ohmic contact.

Also, the n ⁺ -GaAs subcollector layer 12
To the semi-insulating GaAs substrate 10, the element isolation region 36 in which ions such as O are implanted is formed, and the HBT is formed.
Element isolation. As described above, the HBT according to the present embodiment has the n-GaA of the HBT according to the first embodiment.
While the n-InGaP etching stopper layer 16 is provided between the s collector layer 14 and the p ⁺ -GaAs external base layer 18, the p ⁺ -GaAs base layer 38 and the p ⁺ -GaAs base layer 38 are provided.
It is characterized in that the n-InGaP etching stopper layer 16 is provided between the GaAs external base layer 18 and the base layer in a broad sense.

Next, a method for manufacturing the HBT shown in FIG. 4 will be described with reference to the process charts shown in FIGS. The same components as those of the HBT shown in FIGS. 2 and 3 are designated by the same reference numerals and the description thereof will be omitted. N on the semi-insulating GaAs substrate 10
⁺ -GaAs subcollector layer 12, n-GaAs collector layer 14, and p ⁺ -GaAs base layer 3 having a thickness of 15 nm
8, n-InGaP etching stopper layer 16, and p
^{The +} -GaAs external base layer 18 is epitaxially grown in order (see FIG. 5A).

Next, the p ⁺ -GaAs external base layer 18 is formed.
Using the patterned SiN mask layer 20 as an etching mask, the p ⁺ -GaAs external base layer 18 is n −.
Selective etching is performed until reaching the InGaP etching stopper layer 16 to form an opening. Then, the exposed n-InGaP etching stopper layer 16 in the opening is formed.
Is selectively removed by etching to expose the p ⁺ -GaAs base layer 38 (see FIG. 5B).

Then, exposed p ⁺ -GaA in the opening is formed.
On the s base layer 38, a 15 nm-thick p ⁺ -GaAs intrinsic base layer 22, n-Al _0.25 Ga _0.75 As emitter layer 24, n ⁺ -Al _X Ga _{1 -X} As graded layer 26,
Then, the n ⁺ -GaAs emitter contact layer 28 is selectively regrown in sequence (see FIG. 6C). Then this n ⁺ −
Emitter electrode 3 on the GaAs emitter contact layer 28
0 is formed on the p ⁺ -GaAs external base layer 18 by ohmic contact with the base electrodes 32, respectively. Then, p ⁺ -GaAs external base layer 18 and n-InGaP
Etching stopper layer 16, p ⁺ -GaAs base layer 3
8, n-GaAs collector layer 14, and n ⁺ -GaAs
The upper surface of the sub-collector layer 12 is mesa-etched to n ⁺ -G
The aAs subcollector layer 12 is exposed, and the exposed n
^{+ −} Collector electrode 34 on the GaAs subcollector layer 12
Are formed in ohmic contact.

Subsequently, the n ⁺ -GaAs subcollector layer 1
An element isolation region 36 extending from 2 to the semi-insulating GaAs substrate 10 is formed to perform element isolation (see FIG. 6D).
In this way, the HBT shown in FIG. 4 is obtained. As described above, according to the present embodiment, the p ⁺ -GaAs base layer 38 and the p ⁺ -type base layer 38 are formed.
An n-InGaP etching stopper layer 16 is provided between the n-InGaP etching stopper layer 16 and the GaAs extrinsic base layer 18, that is, in the base layer in a broad sense, and by selective etching of the p ⁺ -GaAs extrinsic base layer 18 using the n-InGaP etching stopper layer 16. By selectively re-growing the p ⁺ -GaAs intrinsic base layer 22 on the exposed p ⁺ -GaAs base layer 38, the p ⁺ -GaAs base layer 38 and the p ⁺ -GaAs intrinsic base layer forming the intrinsic base region are formed. That the thickness of 22 is controlled by crystal growth, that the p ⁺ -GaAs extrinsic base layer 18 can be heavily doped, p ⁺ -
The p ⁺ -GaAs intrinsic base layer 22 is regrown on the GaAs base layer 38 and the emitter-base junction surface is not used as a regrown interface, and the emitter-base junction area is p ⁺ -Ga.
Since it is determined by the size of the opening formed in the As external base layer 18, the same effect as in the case of the first embodiment can be obtained.

Next, the HBT according to the third embodiment of the present invention.
Will be described with reference to FIG. FIG. 7 is a sectional view showing an HBT according to the third embodiment. The HBT shown in FIG.
The same components as those in FIG.
An n ⁺ -GaAs subcollector layer 12, an n-GaAs collector layer 14, and a p ⁺ -GaAs base layer 38 having a thickness of 20 nm are sequentially formed on a semi-insulating GaAs substrate 10. In the central portion of the p ⁺ -GaAs base layer 38, the n-Al _0.25 Ga _0.75 As emitter layer 24,
n ⁺ -Al _X Ga _{1 -X} As graded layer 26, and n
^{A +} -GaAs emitter contact layer 28 is sequentially formed.

On the p ⁺ -GaAs base layer 38 around the n-Al _0.25 Ga _0.75 As emitter layer 24, n is formed.
-P ⁺ via the InGaP etching stopper layer 16
-A GaAs extrinsic base layer 18 is sequentially formed. Further, on the n ⁺ -GaAs emitter contact layer 28,
The emitter electrode 30 is formed in ohmic contact with p ⁺
A base electrode 32 is formed in ohmic contact on the -GaAs external base layer 18, and a collector electrode 34 is formed in ohmic contact on the n ⁺ -GaAs subcollector layer 12.

Also, the n ⁺ -GaAs subcollector layer 12
To the semi-insulating GaAs substrate 10, the element isolation region 36 in which ions such as O are implanted is formed, and the HBT is formed.
Element isolation. Next, a method for manufacturing the HBT of FIG. 7 will be described with reference to the process drawings shown in FIGS.
The same components as those of the HBT shown in FIGS. 8 and 9 are designated by the same reference numerals, and the description thereof will be omitted.

On the semi-insulating GaAs substrate 10, n ⁺ -G
aAs sub-collector layer 12, n-GaAs collector layer 1
4, p ⁺ -GaAs base layer 38 having a thickness of 20 nm, n-
InGaP etching stopper layer 16 and p ⁺ -Ga
The As external base layer 18 is sequentially epitaxially grown (see FIG. 8A). Then, using the SiN mask layer 20 patterned on the p ⁺ -GaAs external base layer 18 as an etching mask, the p ⁺ -GaAs external base layer 1 is formed.
8 is selectively etched until it reaches the n-InGaP etching stopper layer 16 to form an opening. Subsequently, the exposed n-InGaP etching stopper layer 16 in the opening is selectively removed by etching to obtain p ⁺ -GaA.
The s base layer 38 is exposed (see FIG. 8B).

Then, exposed p ⁺ -GaA in the opening is formed.
The n-Al _0.25 Ga _0.75 As emitter layer 24 and the n ⁺ -Al _X Ga _1-X As graded layer 2 are formed on the s base layer 38.
6 and n ⁺ -GaAs emitter contact layer 28 are selectively regrown in sequence (see FIG. 9C). Then this n
^An emitter electrode 30 is formed on the ⁺ -GaAs emitter contact layer 28, and a base electrode 32 is formed on the p ⁺ -GaAs external base layer 18 in ohmic contact with each other.
Then, p ⁺ -GaAs external base layer 18, n-InG
aP etching stopper layer 16, p ⁺ -GaAs base layer 38, n-GaAs collector layer 14, and n ⁺ -Ga
The top surface of the As subcollector layer 12 is mesa-etched to n ⁺
The -GaAs subcollector layer 12 is exposed, and the collector electrode 34 is formed on the exposed n ⁺ -GaAs subcollector layer 12 by ohmic contact.

Subsequently, the n ⁺ -GaAs subcollector layer 1
A device isolation region 36 is formed from 2 to the semi-insulating GaAs substrate 10 to perform device isolation (see FIG. 9D).
In this way, the HBT shown in FIG. 7 is obtained. As described above, according to the present embodiment, the p ⁺ -GaAs base layer 38 and the p ⁺ -type base layer 38 are formed.
An n-InGaP etching stopper layer 16 is provided between the n-InGaP etching stopper layer 16 and the GaAs extrinsic base layer 18, that is, in the base layer in a broad sense, and by selective etching of the p ⁺ -GaAs extrinsic base layer 18 using the n-InGaP etching stopper layer 16. By selectively re-growing the n-Al _0.25 Ga _0.75 As emitter layer 24 on the exposed p ⁺ -GaAs base layer 38, p ⁺ -Ga forming the intrinsic base region is formed.
The thickness of the As base layer 38 is controlled by crystal growth, the p ⁺ -GaAs extrinsic base layer 18 can be highly doped, and the emitter-base junction area is p ⁺ −.
Since it is determined by the size of the opening formed in the GaAs extrinsic base layer 18, it is possible to obtain substantially the same effect as in the case of the second embodiment.

However, n is formed on the p ⁺ -GaAs base layer 38.
Since the -Al _0.25 Ga _0.75 As emitter layer 24 is regrown and the emitter / base junction surface is used as a regrowth interface, the contamination of the regrowth interface has a great influence on the device characteristics, and the device characteristics such as the current gain are affected. The problem of lowering is not solved. Next, an HBT according to the fourth embodiment of the present invention will be described with reference to FIG.

FIG. 10 is a sectional view showing an HBT according to the fourth embodiment. Incidentally, the same components as those of the HBT shown in FIG. Semi-insulating Ga
An n ⁺ -GaAs subcollector layer 12 is formed on the As substrate 10.
And the n-GaAs collector layer 14 are sequentially formed. A p ⁺ -GaAs intrinsic base layer 22 is formed in the center of the n-GaAs collector layer 14, and an n-type is formed on the p ⁺ -GaAs intrinsic base layer 22.
Al _0.25 Ga _0.75 As emitter layer 24, n ⁺ -Al _X G
An a _1-X As graded layer 26 and an n ⁺ -GaAs emitter contact layer 28 are sequentially formed.

On the p ⁺ -GaAs base layer 38 around the p ⁺ -GaAs intrinsic base layer 22, n-InG is formed.
p ⁺ -GaA via the aP etching stopper layer 16
The external base layer 18 is sequentially formed. The present embodiment is characterized in that the SiN sidewall layer 40 is formed on the sidewall of the p ⁺ -GaAs external base layer 18.

An emitter electrode 30 is formed in ohmic contact on the n ⁺ -GaAs emitter contact layer 28, and a base electrode 32 is formed in ohmic contact on the p ⁺ -GaAs external base layer 18. , N ⁺ -G
A collector electrode 34 is formed on the aAs sub-collector layer 12 in ohmic contact. In addition, n ⁺ -Ga
From the As subcollector layer 12 to the semi-insulating GaAs substrate 10
The inter-element isolation region 36 is formed to reach up to (3) to perform the element isolation of the HBT.

Next, the manufacturing method of the HBT shown in FIG.
It demonstrates using the process drawing shown in FIG. 1 and FIG. The same components as those of the HBT shown in FIGS. 2 and 3 are designated by the same reference numerals and the description thereof will be omitted. The n ⁺ -GaAs subcollector layer 12 and the n-GaAs are formed on the semi-insulating GaAs substrate 10 in substantially the same manner as the steps shown in FIGS.
The collector layer 14, the n-InGaP etching stopper layer 16, and the p ⁺ -GaAs external base layer 18 are epitaxially grown in this order. Then, using the SiN mask layer 20 patterned on the p ⁺ -GaAs external base layer 18 as an etching mask, the p ⁺ -GaAs external base layer 1 is formed.
8 is selectively etched until it reaches the n-InGaP etching stopper layer 16 to form an opening (FIG. 11).
(See (a)).

Next, after depositing a SiN film on the entire surface, R
Perform IE (Reactive Ion Etching) and p ⁺ in the opening
-The SiN film is left only on the sidewall of the GaAs external base layer 18 to form the SiN sidewall layer 40 (FIG. 11).
(See (b)). Then, n-InG exposed in the opening
The aP etching stopper layer 16 is selectively removed by etching to expose the n-GaAs collector layer 14 (see FIG. 12C).

The formation of the SiN sidewall layer 40 on the sidewall of the p ⁺ -GaAs external base layer 18 is performed by n-InG.
This may be performed after the aP etching stopper layer 16 is selectively removed by etching, but the already exposed n-Ga
Since there is a high risk of contamination occurring on the surface of the As collector layer 14, as described above, the n-InG in the opening is
It is desirable that the aP etching stopper layer 16 be selectively etched and removed before the n-GaAs collector layer 14 is exposed.

Then, the process shown in FIGS. 3 (c) to 3 (d) is performed.
In the same manner as described above, the exposed n-GaAs collector layer 14
On top, p⁺-GaAs intrinsic base layer 22, n-Al_0.25
Ga _0.75As emitter layer 24, n⁺-Al_XGa_1-XA
s graded layer 26, and n⁺-GaAs emitter
The contact layer 28 is selectively regrown in sequence. Then, this n
⁺-Emitter charge on the GaAs emitter contact layer 28
Pole 30, p⁺-Base on GaAs external base layer 18
The electrodes 32 are formed in ohmic contact with each other.
Furthermore, p⁺-GaAs external base layer 18, n-InGa
P etching stopper layer 16, p⁺-GaAs base layer
38, n-GaAs collector layer 14, and n⁺-GaA
The upper surface of the s subcollector layer 12 is mesa-etched to⁺−
The GaAs subcollector layer 12 is exposed, and this exposed
n⁺-Collector electrode 3 on GaAs subcollector layer 12
4 is formed in ohmic contact.

Subsequently, the n ⁺ -GaAs subcollector layer 1
An element isolation region 36 extending from 2 to the semi-insulating GaAs substrate 10 is formed to perform element isolation (see FIG. 12D). In this way, the HBT shown in FIG. 4 is obtained. Thus, according to this embodiment, the p ⁺ -GaAs external base layer 1 is formed.
The HBT is the same as the HBT according to the first embodiment except that the SiN sidewall layer 40 is formed on the eight side walls, and therefore the same effect as in the case of the first embodiment can be obtained.

Further, by forming the SiN sidewall layer 40 on the sidewall of the p ⁺ -GaAs external base layer 18, the p ⁺ -GaAs intrinsic base layer 22 and n- are formed therein.
It is possible to reduce the Al _{0. 25} Ga _0.75 As the size of the opening to be regrown emitter layer 24, etc., it is possible to further refine the emitter-base junction area. By controlling the thickness of the SiN sidewall layer 40, the degree of miniaturization can be easily controlled.

In the present embodiment, the case where the SiN sidewall layer 40 is formed on the sidewall of the p ⁺ -GaAs external base layer 18 of the HBT according to the first embodiment has been described. A SiN sidewall layer may be formed on the sidewall of the p ⁺ -GaAs external base layer 18 of the HBT according to the embodiment. In the first to fourth embodiments, the AlGaAs / GaAs system HBT is used.
Although the present invention is applied to the above, the present invention is not limited to this, and the present invention is also applicable to an HBT using another compound semiconductor such as InP / InGaAs system or GaAs / Ge system.

[0061]

As described above, according to the present invention,
An etching stopper layer is provided between the collector layer or base layer and the external base layer, and the etching stopper layer forcibly stops the selective etching of the external base layer. By sequentially regrowing the intrinsic base layer and the emitter layer, the thickness of the intrinsic base region is controlled not by etching but by crystal growth, so that the controllability and reproducibility are dramatically improved, It is possible to make the intrinsic base layer as thin as possible.

Since the regrowth interface is at the base-collector junction surface or in the base and is not the emitter-base junction surface which has a great influence on the device characteristics, contamination of the regrowth interface due to regrowth causes Good element characteristics can be realized without affecting the base junction. The emitter-base junction area is
Since it is determined not by the mesa structure but by the size of the opening formed by the selective etching of the external base layer, the device can be miniaturized, which is advantageous for low power consumption.

Further, by forming a sidewall layer on the sidewall of the external base layer, the size of the opening for re-growing the intrinsic base layer and the emitter layer therein can be controlled, so that the emitter-base junction area can be controlled. Can be further miniaturized. Therefore, it is possible to easily obtain an HBT having excellent high speed, low power consumption, and good device characteristics, and it is possible to greatly contribute to high performance of an integrated circuit of the HBT.

[Brief description of drawings]

FIG. 1 is a sectional view showing an HBT according to a first embodiment of the present invention.

FIG. 2 is a process diagram (1) for explaining the method for manufacturing the HBT in FIG. 1.

FIG. 3 is a process diagram (No. 2) for explaining the method for manufacturing the HBT in FIG. 1.

FIG. 4 is a sectional view showing an HBT according to a second embodiment of the present invention.

5A to 5C are process diagrams (No. 1) for explaining the method for manufacturing the HBT in FIG.

FIG. 6 is a process diagram (No. 2) for explaining the method for manufacturing the HBT in FIG.

FIG. 7 is a sectional view showing an HBT according to a third embodiment of the present invention.

FIG. 8 is a process diagram (1) for explaining the method for manufacturing the HBT in FIG. 7.

FIG. 9 is a process view (No. 2) for explaining the method for manufacturing the HBT in FIG. 7.

FIG. 10 is a sectional view showing an HBT according to a fourth embodiment of the present invention.

FIG. 11 is a process drawing (1) for explaining the method for manufacturing the HBT in FIG. 10.

FIG. 12 is a process diagram (part 2) for explaining the method for manufacturing the HBT in FIG. 10.

FIG. 13 is a process chart for explaining a conventional HBT manufacturing method using regrowth on an external base.

FIG. 14 is a process chart for explaining a conventional HBT manufacturing method using re-growth for an emitter.

[Explanation of symbols]

10 ... Semi-insulating GaAs substrate 12 ... n ⁺ -GaAs subcollector layer 14 ... n-GaAs collector layer 16 ... n-InGaP etching stopper layer 18 ... p ⁺ -GaAs external base layer 20 ... SiN mask layer 22 ... p ⁺ - GaAs intrinsic base layer 24 ... n-Al _0.25 Ga _0.75 As emitter layer 26 ... n ⁺ -Al _X Ga _1-X As graded layer 28 ... n ⁺ -GaAs emitter contact layer 30 ... Emitter electrode 32 ... Base electrode 34 ... Collector Electrode 36 ... Element isolation region 38 ... p ⁺ -GaAs base layer 40 ... SiN sidewall layer 50 ... semi-insulating GaAs substrate 52 ... n ⁺ -GaAs subcollector layer 54 ... n-GaAs collector layer 56 ... p-GaAs base layer 58 ... n-AlGaAs emitter layer 60 ... n ⁺ -GaAs emitter cap layer 62 WSi layer 64 ... SiO ₂ layer 66 ... SiO ₂ layer 68 ... p ⁺ -GaAs external base layer 70 ... Ti / Pt / Au base electrode 72 ... device isolation region 74 ... AuGe / Ni / Au collector electrode 76 ... SiO ₂ layer 78 ... Ti / Pt / Au emitter electrode 80 ... n ⁺ -GaAs substrate 82 ... n ⁺ -GaAs buffer layer 84 ... n-GaAs collector layer 86 ... p-GaAs base layer 88 ... PAS film 90 ... n-AlGaAs emitter layer 92 ... n ⁺ -GaAs emitter cap layer 94 ... emitter electrode 96 ... base electrode 98 ... collector electrode

Claims (9)

[Claims] 1. A collector layer, an intrinsic base layer formed on the collector layer, an external base layer formed on the collector layer around the intrinsic base layer via an etching stopper layer, and the intrinsic base layer. A heterojunction bipolar transistor formed on a base layer, the emitter layer having a bandgap larger than that of the intrinsic base layer. 2. A collector layer, a base layer formed on the collector layer, an intrinsic base layer formed on the base layer, and an etching stopper layer on the base layer around the intrinsic base layer. A heterojunction bipolar transistor, comprising: an external base layer formed through the base layer; and an emitter layer formed on the intrinsic base layer and having a bandgap larger than that of the intrinsic base layer. 3. A collector layer, a base layer formed on the collector layer, an emitter layer formed on the base layer and having a bandgap larger than that of the base layer, and the base layer around the emitter layer. A heterojunction bipolar transistor having thereon an external base layer formed via an etching stopper layer. 4. The heterojunction bipolar transistor according to claim 1, wherein a sidewall layer is formed on a sidewall of the external base layer. 5. A step of sequentially growing an etching stopper layer and an external base layer on the collector layer, a step of forming a mask layer patterned in a predetermined shape on the external base layer, and using the mask layer as a mask. A step of selectively etching the external base layer until reaching the etching stopper layer, and then selectively etching the exposed etching stopper layer to expose the collector layer; and a step of exposing the collector layer on the exposed collector layer. And a step of sequentially growing an intrinsic base layer and an emitter layer having a bandgap larger than that of the intrinsic base layer. 6. A step of sequentially growing a base layer, an etching stopper layer and an external base layer on the collector layer, a step of forming a mask layer patterned in a predetermined shape on the external base layer, and the mask layer. A step of selectively etching the external base layer until the etching stopper layer is reached by using the as a mask, and then selectively etching the exposed etching stopper layer to expose the base layer; A step of sequentially growing an intrinsic base layer and an emitter layer having a bandgap larger than that of the intrinsic base layer on the layer. 7. A step of sequentially growing a base layer, an etching stopper layer, and an external base layer on the collector layer; a step of forming a mask layer patterned in a predetermined shape on the external base layer; and the mask layer. A step of selectively etching the external base layer until the etching stopper layer is reached by using the as a mask, and then selectively etching the exposed etching stopper layer to expose the base layer; A step of growing an emitter layer having a bandgap larger than that of the base layer on the layer, the method of manufacturing a heterojunction bipolar transistor. 8. The method for manufacturing a heterojunction bipolar transistor according to claim 5, wherein a sidewall layer is formed on a sidewall of the external base layer after selectively etching the external base layer. A method of manufacturing a heterojunction bipolar transistor characterized by the above. 9. The heterojunction bipolar transistor according to claim 8, wherein the sidewall layer is formed before the etching stopper layer is selectively etched. Manufacturing method.