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JPH0722951A - Noise shaper - Google Patents

Noise shaper

Info

Publication number
JPH0722951A
JPH0722951A JP31588291A JP31588291A JPH0722951A JP H0722951 A JPH0722951 A JP H0722951A JP 31588291 A JP31588291 A JP 31588291A JP 31588291 A JP31588291 A JP 31588291A JP H0722951 A JPH0722951 A JP H0722951A
Authority
JP
Japan
Prior art keywords
zero
quantizer
noise shaper
constant
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP31588291A
Other languages
Japanese (ja)
Other versions
JP2822734B2 (en
Inventor
Toshiyuki Okamoto
俊之 岡本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3315882A priority Critical patent/JP2822734B2/en
Publication of JPH0722951A publication Critical patent/JPH0722951A/en
Application granted granted Critical
Publication of JP2822734B2 publication Critical patent/JP2822734B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To always set the output signal to be zero when a non-signal is inputted by setting the sign of a constant so as to be negative, positive, or zero when a storage data before one sample delay is positive, negative, or zero. CONSTITUTION:A difference signal between the output signal of a quantizer C delayed by a delay D and an input signal is inputted to an integrator S1, and integrated. Also, a difference signal between the output signal of the integrator S1 and the two-fold signal of the output of the quantizer C delayed by the delay D and amplified by an amplifier A is inputted to an integrator S2, integrated, and inputted to the quantizer C. The quantizer C outputs '+1' when the input is more than +1/2, outputs '0' when the input is between -1/2 and +1/2, and outputs '-1' when the input is less than -1/2. When the non- signal is inputted, and the initial values of the integrators S1 and S2 are zero, the output code is zero, and when the initial value of the integrator S1 is a constant value except zero, the absolute value is gradually decreased by the addition of the fixed constant for controlling the sign by the sign of the storage data, and finally turned to zero. Therefore, the output of the noise shaper can be always set to be zero.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は特に入力信号が無信号の
時は出力信号も零になり、低周波数領域に雑音を生じな
いノイズシェイパに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a noise shaper that outputs no output signal when no input signal is present and does not generate noise in a low frequency region.

【0002】[0002]

【従来の技術】従来の3値を出力とするノイズシェイパ
は、例えば図6に示す様な構成になっている。即ち、第
1及び第2の積分器S1,S2と、第2の積分器の出力
を入力とし、3値の信号を出力とする量子化器Cと、量
子化器の出力を第1及び第2の積分器S1,S2に帰還
する遅延器Dを有する帰還回路とで構成されている。第
1の積分器S1の出力は増幅器Aで2倍に増幅された遅
延器Dの出力と減算されて第2の積分器に入力されてい
る。また、積分器はディジタル回路によって構成され、
図7に示す回路によって実現されている。
2. Description of the Related Art A conventional noise shaper that outputs three values has a structure as shown in FIG. 6, for example. That is, the first and second integrators S1 and S2, the quantizer C that receives the output of the second integrator as an input and outputs a ternary signal, and the output of the quantizer to the first and second integrators. And a feedback circuit having a delay device D that feeds back to the two integrators S1 and S2. The output of the first integrator S1 is subtracted from the output of the delay device D doubled by the amplifier A and input to the second integrator. Also, the integrator is composed of a digital circuit,
This is realized by the circuit shown in FIG.

【0003】次に、図6を用いて従来のノイズシェイパ
の動作を説明する。第1段目の積分器S1には、遅延器
Dで遅延された量子化器Cの出力信号と入力信号との差
信号が入力され積分される。また、第1段目の積分器S
1の出力信号と遅延器Dで遅延された量子化器Cの出力
信号の2倍との差信号が、第2段目の積分器S2に入力
され積分される。第2段目の積分器S2の出力は、量子
化器Cに入力される。この時、+1/2より大きい時は
出力は+1に、−1/2から+1/2の間場合は0が、
また−1/2よりも小さい時は−1が出力される。この
様な構成を持つ事によって、量子化器Cで発生する量子
化雑音をQとすると、ノイズシェイパ入力信号Xと出力
信号Yの間には次式に示す関係がある。
Next, the operation of the conventional noise shaper will be described with reference to FIG. The difference signal between the output signal of the quantizer C delayed by the delay device D and the input signal is input to the first-stage integrator S1 and integrated. In addition, the first-stage integrator S
The difference signal between the output signal of 1 and the doubled output signal of the quantizer C delayed by the delay device D is input to the second-stage integrator S2 and integrated. The output of the second-stage integrator S2 is input to the quantizer C. At this time, the output is +1 when it is larger than +1/2, and 0 when it is between -1/2 and +1/2.
When it is smaller than -1/2, -1 is output. With such a configuration, assuming that the quantization noise generated in the quantizer C is Q, the noise shaper input signal X and the output signal Y have the relationship shown in the following equation.

【0004】 Y(z)=X(z)+(1−z-12 ・Q(Z) …… (1) 従って、ノイズシェイパの出力スペクトラムは、ノイズ
シェイパの入力に量子化雑音を2階微分した信号を重畳
したスペクトラムを有する事になる。即ち、量子化雑音
が高周波領域にシェイピングされて重畳されるため、信
号帯域内における雑音総和を大幅に減少する。
Y (z) = X (z) + (1-z −1 ) 2 · Q (Z) (1) Therefore, the output spectrum of the noise shaper is the second derivative of the quantization noise at the input of the noise shaper. It will have a spectrum in which the generated signal is superimposed. That is, since the quantization noise is shaped and superimposed in the high frequency region, the total noise in the signal band is significantly reduced.

【0005】ところで、このノイズシェイパに無信号が
入力された場合を考える。図7に示すように積分器S
1,S2を構成する遅延器D1,D2のデータが、初期
状態で零であると出力信号は零になる事は明らかであ
る。一方、積分器S1,S2を構成する遅延器D1,D
2のデータが初期状態で零ではなく、例えば第1段目の
積分器S1の初期値が0.5であると仮定する。この
時、ノイズシェイパの出力は、+1及び−1を繰り返
し、零にはならない。また、第1段目の積分器S1の初
期値が0.5よりも小さく、例えば0.1の場合は、+
1、−1、8回連続零、+1、−1、8回連続零・・を
定常的に繰り返す。これらの事から、第1段目の積分器
S1の初期値が零ではない場合、ノイズシェイパの出力
は零にはならない事がわかる。また、第1段目の積分器
S1の初期値が小さい程、+1、−1の次に続く0の回
数が増え、従って、出力に含まれるスペクトラムに低周
波成分が現われる。
Now, consider the case where no signal is input to this noise shaper. As shown in FIG.
It is clear that the output signal becomes zero when the data of the delay devices D1 and D2 forming 1, S2 are zero in the initial state. On the other hand, the delay devices D1 and D that form the integrators S1 and S2
It is assumed that the data of 2 is not zero in the initial state and the initial value of the integrator S1 of the first stage is 0.5, for example. At this time, the output of the noise shaper repeats +1 and -1, and does not become zero. If the initial value of the integrator S1 of the first stage is smaller than 0.5, for example, 0.1, +
It repeats -1, -1, and 8 consecutive zeros, +1, -1, and 8 consecutive zeros steadily. From these, it can be seen that the output of the noise shaper does not become zero when the initial value of the integrator S1 of the first stage is not zero. In addition, the smaller the initial value of the integrator S1 of the first stage, the more the number of 0s following +1 and -1 increases, so that a low frequency component appears in the spectrum included in the output.

【0006】[0006]

【発明が解決しようとする課題】図6に示す上述した従
来のノイズシェイパでは、無信号が入力された場合で第
1段目の積分器S1の初期値が小さければ小さい程、出
力信号に含まれるスペクトラムにより低周波成分が現わ
れる問題があった。
In the above-mentioned conventional noise shaper shown in FIG. 6, the smaller the initial value of the integrator S1 of the first stage is, the more the noise is included in the output signal when no signal is input. There was a problem that low frequency components appeared due to the spectrum.

【0007】[0007]

【課題を解決するための手段】本発明によれば、1段以
上の積分回路と、0及び±1を出力とする3値量子化器
と帰還回路とで構成されるノイズシェイパにおいて、ノ
イズシェイパの入力信号と前記帰還回路の1つ以上の出
力信号とを前記積分回路に入力する接続と、前記積分回
路の出力信号を前記量子化器に入力する接続と、前記量
子化器とノイズシェイパの出力端子との接続とを有し、
少なくとも1つ以上の積分回路の積分動作が1サンプル
遅延前の蓄積データと現データと絶対値が一定値あるい
は零である定数との加算によって実現される不完全積分
動作であって、前記1サンプル遅延前の蓄積データの符
号に応じて定数の符号を制御する手段を有したノイズシ
ェイパを得る。
According to the present invention, a noise shaper comprising one or more stages of integrating circuits, a ternary quantizer having 0 and ± 1 as outputs, and a feedback circuit is used as the input of the noise shaper. A connection for inputting a signal and one or more output signals of the feedback circuit to the integrator circuit; a connection for inputting the output signal of the integrator circuit to the quantizer; and output terminals of the quantizer and noise shaper. With connections of
The integration operation of at least one or more integrator circuits is an incomplete integration operation realized by adding the accumulated data before one sample delay, the present data and a constant whose absolute value is a constant value or zero, A noise shaper having means for controlling the sign of a constant according to the sign of accumulated data before delay is obtained.

【0008】[0008]

【実施例】次に、本発明について図面を参照して説明す
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

【0009】図1は本発明の一実施例である。S1は第
1段目の積分器、S2は第2段目の積分器、Cは±0.
5をしきい値として3値のレベルを出力する量子化器、
Dは遅延器、Aは増幅率2の増幅器である。第1段目の
積分器S1には、遅延器Dで遅延された量子化器Cの出
力信号と入力信号との差信号が入力され積分される。ま
た、第1段目の積分器S1の出力信号と遅延器Dで遅延
された後増幅器Aで増幅された量子化器Cの出力信号の
2倍との差信号が、第2段目の積分器S2に入力され、
積分される。第2,段目の積分器S2の出力は、量子化
器Cに入力される。量子化器Cにおいては、入力が+1
/2より大きい時は出力は+1に、−1/2から+1/
2の間場合は0が、また−1/2よりも小さい時は−1
が出力される。また、積分器S1,S2は、例えば図2
に示すように構成することができる。図2に示す様に、
第1段目の積分器S1は、1サンプル遅延前の蓄積デー
タと現データと固定定数(±2-18 )との加算を行う。
この時、固定定数の符号は、1サンプル遅延前の蓄積デ
ータが正の時は負に、1サンプル遅延前の蓄積データが
負の時は正に、1サンプル遅延前の蓄積データが零の時
は固定定数を零に符号制御回路CONT1で制御され
る。また第2段目の積分器S2は、1サンプル遅延前の
蓄積データと現データとの加算によって実現される完全
積分器である。
FIG. 1 shows an embodiment of the present invention. S1 is a first-stage integrator, S2 is a second-stage integrator, and C is ± 0.
A quantizer that outputs a ternary level with 5 as a threshold,
D is a delay device, and A is an amplifier with an amplification factor of 2. The difference signal between the output signal of the quantizer C delayed by the delay device D and the input signal is input to the first-stage integrator S1 and integrated. Further, the difference signal between the output signal of the integrator S1 at the first stage and twice the output signal of the quantizer C delayed by the delay device D and then amplified by the amplifier A is the integration signal of the second stage. Input to the vessel S2,
Integrated. The output of the second-stage integrator S2 is input to the quantizer C. In the quantizer C, the input is +1
When it is larger than / 2, the output is +1 and from -1/2 to + 1 /
0 between 2 and -1 when less than -1/2
Is output. Further, the integrators S1 and S2 are, for example, as shown in FIG.
Can be configured as shown in. As shown in FIG.
The first-stage integrator S1 adds the accumulated data before one sample delay, the current data, and the fixed constant (± 2 -18 ).
At this time, the sign of the fixed constant is negative when the accumulated data before one sample delay is positive, positive when the accumulated data before one sample delay is negative, and is zero when the accumulated data before one sample delay is zero. Is controlled by the sign control circuit CONT1 so that the fixed constant becomes zero. The second-stage integrator S2 is a perfect integrator realized by adding the accumulated data before one sample delay and the current data.

【0010】この様な構成を持つ事によって、量子化器
Cで発生する量子化雑音をQとすると、ノイズシェイパ
入力信号Xと出力信号Yの間にはおおむね次式に示す関
係がある。
With such a configuration, assuming that the quantization noise generated by the quantizer C is Q, the relationship between the noise shaper input signal X and the output signal Y is approximately expressed by the following equation.

【0011】 Y(z)=z-1・X(z)/P(z)+(1−z-12 ・Q(z)…(2) 従って、ノイズシェイパの出力スペクトラムは、ノイズ
シェイパの入力に量子化雑音を殆ど2階微分した信号を
重畳したスペクトラムを有する事になる。即ち、量子化
雑音が高周波領域にシェイピングされて重畳されるた
め、従来のノイズシェイピングの特性をそれ程劣化させ
ることなく信号帯域内における雑音総和は大幅に減少す
る。
Y (z) = z −1 · X (z) / P (z) + (1−z −1 ) 2 · Q (z) (2) Therefore, the output spectrum of the noise shaper is the input of the noise shaper. It has a spectrum in which a signal obtained by almost second-order differentiation of the quantization noise is superimposed on. That is, since the quantization noise is shaped and superimposed in the high frequency region, the total noise in the signal band is significantly reduced without deteriorating the characteristics of the conventional noise shaping.

【0012】以上示した動作において、ノイズシェイパ
に無信号が入力された場合を考える。今、第1段目,第
2段目の積分器S1,S2の初期値が零の場合は出力コ
ードは零になる事は明かである。次に第1段目の積分器
S1の初期値が零以外の一定の値の場合は、蓄積データ
の符号によって符号が制御される一定定数の加算によっ
て次第に絶対値が小さくなりやがては零になる。従っ
て、ノイズシェイパの出力は常に零になる。
Consider the case where no signal is input to the noise shaper in the operation described above. Now, it is clear that the output code becomes zero when the initial values of the integrators S1 and S2 of the first and second stages are zero. Next, when the initial value of the integrator S1 of the first stage is a constant value other than zero, the absolute value gradually decreases by addition of a constant constant whose sign is controlled by the sign of the accumulated data, and eventually becomes zero. . Therefore, the output of the noise shaper is always zero.

【0013】次に、本発明の第二の実施例について説明
する。第一の実施例では、第1段目の積分器S1を図2
に示す回路で実現した。図3に第二の実施例に用いた積
分器の回路図を示す。図3に示す様に、1段目の積分器
S1は、1サンプル遅延前の蓄積データと現データと固
定定数(±2-16 )との加算を行う。この時、固定定数
の符号は、1サンプル遅延前の蓄積データが正の時は負
に、1サンプル遅延前の蓄積データが負の時は正に、1
サンプル遅延前の蓄積データが零の時は固定定数を零に
符号制御回路CONT2で制御される。また第2段目の
積分器S2は、1サンプル遅延前の蓄積データと現デー
タとの加算によって実現される完全積分器である。
Next, a second embodiment of the present invention will be described. In the first embodiment, the first stage integrator S1 is shown in FIG.
It was realized by the circuit shown in. FIG. 3 shows a circuit diagram of the integrator used in the second embodiment. As shown in FIG. 3, the first-stage integrator S1 adds the accumulated data before the delay of one sample, the current data, and the fixed constant (± 2 −16 ). At this time, the sign of the fixed constant is negative when the accumulated data before one sample delay is positive, and is positive when the accumulated data before one sample delay is negative.
When the accumulated data before the sample delay is zero, the fixed constant is controlled to zero by the sign control circuit CONT2. The second-stage integrator S2 is a perfect integrator realized by adding the accumulated data before one sample delay and the current data.

【0014】この様な構成を持つ事によって、量子化器
Cで発生する量子化雑音をQとすると、ノイズシェイパ
入力信号Xと出力信号Yの間にはおおむね次式に示す関
係がある。
With such a configuration, assuming that the quantization noise generated in the quantizer C is Q, the relationship between the noise shaper input signal X and the output signal Y is shown by the following equation.

【0015】 Y(z)=z-1・X(z)/P(z)+(1−z-12 ・Q(z)…(3) 従って、ノイズシェイパの出力スペクトラムは、ノイズ
シェイパの入力に量子化雑音を殆ど2階微分した信号を
重畳したスペクトラムを有する事になる。即ち、量子化
雑音が高周波領域にシェイピングされて重畳されるた
め、従来のノイズシェイパの特性をそれ程劣化させるこ
となく信号帯域内における雑音総和は大幅に減少する。
Y (z) = z −1 · X (z) / P (z) + (1−z −1 ) 2 · Q (z) (3) Therefore, the output spectrum of the noise shaper is the input of the noise shaper. It has a spectrum in which a signal obtained by almost second-order differentiation of the quantization noise is superimposed on. That is, since the quantization noise is shaped and superimposed in the high frequency region, the total noise in the signal band is significantly reduced without degrading the characteristics of the conventional noise shaper.

【0016】以上に示した動作において、ノイズシェイ
パに無信号が入力された場合を考える。今、第1段目,
第2段目の積分器S1,S2の初期値が零の場合は出力
コードは零になる事は明かである。次に第1段目の積分
器S1の初期値が零以外の一定の値の場合は、蓄積デー
タの符号によって符号が制御される一定定数の加算によ
って次第に絶対値が小さくなりやがては零になる。従っ
て、ノイズシェイパの出力は常に零になる。
Consider the case where no signal is input to the noise shaper in the above-described operation. Now, the first stage,
It is obvious that the output code becomes zero when the initial values of the second-stage integrators S1 and S2 are zero. Next, when the initial value of the integrator S1 of the first stage is a constant value other than zero, the absolute value gradually decreases by addition of a constant constant whose sign is controlled by the sign of the accumulated data, and eventually becomes zero. . Therefore, the output of the noise shaper is always zero.

【0017】次に、第三の実施例について説明する。図
4は第三の実施例を示す回路図である。図4において、
S1は第1段目の積分器、S2は第2段目の積分器、C
は±0.5をしきい値として3値のレベルを出力する量
子化器、Dは遅延器である。第1段目の積分器S1に
は、遅延器Dで遅延された量子化器Cの出力信号と入力
信号との差信号が入力され積分される。また、第1段目
の積分器S1の出力信号と遅延器Dで遅延された量子化
器Cの出力信号との差信号が、第2段目の積分器S2に
入力され、積分される。第2段目の積分器S2の出力
は、量子化器Cに入力される。この時、+1/2より大
きい時は出力は+1に、−1/2から+1/2の間場合
は0が、また−1/2よりも小さい時は−1が出力され
る。また、積分器S1,S2は、例えば図5に示すよう
に構成することができる。図5に示す様に、1段目の積
分器S1は、1サンプル遅延前の蓄積データと現データ
と固定定数(±2-18 )との加算を行う。この時、固定
定数の符号は、1サンプル遅延前の蓄積データが正の時
は負に、1サンプル遅延前の蓄積データが負の時は正
に、1サンプル遅延前の蓄積データが零の時は固定定数
を零に符号制御回路3で制御される。また第2段目の積
分器は、1サンプル遅延前の蓄積データと現データとの
加算によって実現される完全積分器である。
Next, a third embodiment will be described. FIG. 4 is a circuit diagram showing the third embodiment. In FIG.
S1 is a first stage integrator, S2 is a second stage integrator, C
Is a quantizer that outputs ternary levels with ± 0.5 as a threshold value, and D is a delay device. The difference signal between the output signal of the quantizer C delayed by the delay device D and the input signal is input to the first-stage integrator S1 and integrated. Further, a difference signal between the output signal of the integrator S1 of the first stage and the output signal of the quantizer C delayed by the delay device D is input to the integrator S2 of the second stage and integrated. The output of the second-stage integrator S2 is input to the quantizer C. At this time, the output is +1 when it is larger than +1/2, 0 is output when it is between -1/2 and +1/2, and -1 is output when it is smaller than -1/2. Further, the integrators S1 and S2 can be configured as shown in FIG. 5, for example. As shown in FIG. 5, the first-stage integrator S1 adds the accumulated data before the delay of one sample, the current data, and the fixed constant (± 2 -18 ). At this time, the sign of the fixed constant is negative when the accumulated data before one sample delay is positive, positive when the accumulated data before one sample delay is negative, and is zero when the accumulated data before one sample delay is zero. Is controlled by the sign control circuit 3 so that the fixed constant becomes zero. The second-stage integrator is a perfect integrator which is realized by adding the accumulated data before one sample delay and the current data.

【0018】この様な構成を持つ事によって、量子化器
Cで発生する量子化雑音をQとすると、ノイズシェイパ
入力信号Xと出力信号Yの間にはおおむね次式に示す関
係がある。
With such a configuration, assuming that the quantization noise generated in the quantizer C is Q, the relationship between the noise shaper input signal X and the output signal Y is shown by the following equation.

【0019】 Y(z)=z-1・X(z)/P(z)+(1−z-12 ・Q(z)…(4) 従って、ノイズシェイパの出力スペクトラムは、ノイズ
シェイパの入力に量子化雑音を殆ど2階微分した信号を
重畳したスペクトラムを有する事になる。即ち、量子化
雑音が高周波領域にシェイピングされて重畳されるた
め、従来のノイズシェイピングの特性をそれ程劣化させ
ることなく信号帯域内における雑音総和は大幅に減少す
る。
Y (z) = z −1 · X (z) / P (z) + (1−z −1 ) 2 · Q (z) (4) Therefore, the output spectrum of the noise shaper is the input of the noise shaper. It has a spectrum in which a signal obtained by almost second-order differentiation of the quantization noise is superimposed on. That is, since the quantization noise is shaped and superimposed in the high frequency region, the total noise in the signal band is significantly reduced without deteriorating the characteristics of the conventional noise shaping.

【0020】以上に示した動作において、ノイズシェイ
パに無信号が入力された場合を考える。今、第1段目、
第2段目の積分器S1,S2の初期値が零の場合は出力
コードは零になる事は明かである。次に第1段目の積分
器S1の初期値が零以外の一定の値の場合は、蓄積デー
タの符号によって符号が制御される一定定数の加算によ
って次第に絶対値が小さくなりやがては零になる。従っ
て、ノイズシェイパの出力は常に零になる。
Consider the case where no signal is input to the noise shaper in the above-described operation. Now, the first stage,
It is obvious that the output code becomes zero when the initial values of the second-stage integrators S1 and S2 are zero. Next, when the initial value of the integrator S1 of the first stage is a constant value other than zero, the absolute value gradually decreases by addition of a constant constant whose sign is controlled by the sign of the accumulated data, and eventually becomes zero. . Therefore, the output of the noise shaper is always zero.

【0021】以上に示した第一〜第三の実施例の、不完
全積分を実現するための1サンプル遅延前の蓄積データ
によって符号を制御された一定定数の加算において、1
サンプル遅延前の蓄積データが零の時に零を加算するの
ではなく、正、あるいは負の一定定数を加算しても動作
上殆ど相違なく、無信号入力時の出力は零になる事は明
かである。
In the addition of constant constants whose sign is controlled by the accumulated data before one sample delay for realizing incomplete integration in the first to third embodiments shown above,
It is obvious that the output is zero when there is no signal input, even if a positive or negative constant constant is added instead of adding zero when the accumulated data before sample delay is zero. is there.

【0022】[0022]

【発明の効果】以上説明したように、本発明のノイズシ
ェイパでは、S/N特性を損なう事なく、無信号が入力
された場合は出力信号を零にする事ができる。
As described above, in the noise shaper of the present invention, the output signal can be made zero when no signal is input without impairing the S / N characteristic.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第一の実施例の回路図。FIG. 1 is a circuit diagram of a first embodiment of the present invention.

【図2】本発明の第一の実施例を構成する積分器の回路
図。
FIG. 2 is a circuit diagram of an integrator that constitutes the first embodiment of the present invention.

【図3】本発明の第二の実施例を構成する積分器の回路
図。
FIG. 3 is a circuit diagram of an integrator which constitutes a second embodiment of the present invention.

【図4】本発明の第三の実施例の回路図。FIG. 4 is a circuit diagram of a third embodiment of the present invention.

【図5】本発明の第三の実施例を構成する積分器の回路
図。
FIG. 5 is a circuit diagram of an integrator which constitutes a third embodiment of the present invention.

【図6】従来のノイズシェイパの回路図。FIG. 6 is a circuit diagram of a conventional noise shaper.

【図7】従来のノイズシェイパを構成する積分器の回路
図。
FIG. 7 is a circuit diagram of an integrator that constitutes a conventional noise shaper.

【符号の説明】[Explanation of symbols]

S1 第1の積分器 S2 第2の積分器 D,D1,D2 遅延器 C 量子化器 A 増幅器 S1 First integrator S2 Second integrator D, D1, D2 Delay device C Quantizer A Amplifier

─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───

【手続補正書】[Procedure amendment]

【提出日】平成4年3月26日[Submission date] March 26, 1992

【手続補正1】[Procedure Amendment 1]

【補正対象書類名】図面[Document name to be corrected] Drawing

【補正対象項目名】図5[Name of item to be corrected] Figure 5

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【図5】 [Figure 5]

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 1段以上の積分回路と、0及び±1を出
力とする3値量子化器と帰還回路とで構成されるノイズ
シェイパにおいて、ノイズシェイパの入力信号と前記帰
還回路の1つ以上の出力信号とを前記積分回路に入力す
る接続と、前記積分回路の出力信号を前記量子化器に入
力する接続と、前記量子化器とノイズシェイパの出力端
子との接続とを有し、前記積分回路の少なくとも1つ以
上の積分動作が、1サンプル遅延前の蓄積データと現デ
ータと絶対値が一定値あるいは零である定数との加算に
よって実現される不完全積分動作であって、前記1サン
プル遅延前の蓄積データが正の時は前記定数の符号を負
とし、前記1サンプル遅延前の蓄積データが負の時は前
記定数の符号を正とし、前記1サンプル遅延前の蓄積デ
ータが零の時は前記定数を零とする符号制御回路を有す
る事を特徴とするノイズシェイパ。
1. A noise shaper comprising one or more stages of an integrating circuit, a ternary quantizer which outputs 0 and ± 1 and a feedback circuit, wherein an input signal of the noise shaper and one or more of the feedback circuits are provided. And a connection for inputting an output signal to the integrating circuit, a connection for inputting an output signal of the integrating circuit to the quantizer, and a connection between the quantizer and an output terminal of a noise shaper. Is an incomplete integration operation realized by adding the accumulated data before one sample delay, the current data, and a constant whose absolute value is a constant value or zero, and the one sample delay When the previous accumulated data is positive, the sign of the constant is negative, when the accumulated data before the one sample delay is negative, the sign of the constant is positive, and when the accumulated data before the one sample delay is zero. Is the above Noise shaper, characterized in that it has a sign control circuit with zero number.
【請求項2】 1段以上の積分回路と、0及び±1を出
力とする3値量子化器と帰還回路とで構成されるノイズ
シェイパにおいて、ノイズシェイパの入力信号と前記帰
還回路の1つ以上の出力信号とを前記積分回路に入力す
る接続と、前記積分回路の出力信号を前記量子化器に入
力する接続と、前記量子化器とノイズシェイパの出力端
子との接続とを有し、前記積分回路の少なくとも1つ以
上の積分動作が、1サンプル遅延前の蓄積データと現デ
ータと絶対値が一定値の定数との加算によって実現され
る不完全積分動作であって、前記1サンプル遅延前の蓄
積データが正あるいは零の時は前記定数の符号を負と
し、前記1サンプル遅延前の蓄積データが負の時は前記
定数の符号を正とする符号制御回路を有する事を特徴と
するノイズシェイパ。
2. A noise shaper comprising one or more stages of an integrating circuit, a ternary quantizer which outputs 0 and ± 1 and a feedback circuit, wherein an input signal of the noise shaper and one or more of the feedback circuits are provided. And a connection for inputting an output signal to the integrating circuit, a connection for inputting an output signal of the integrating circuit to the quantizer, and a connection between the quantizer and an output terminal of a noise shaper. Is an incomplete integration operation realized by adding the accumulated data before one sample delay, the current data and a constant whose absolute value is a constant value, and the accumulation before the one sample delay A noise shaper comprising a sign control circuit for making the sign of the constant negative when the data is positive or zero and for making the sign of the constant positive when the accumulated data before the one-sample delay is negative.
【請求項3】 1段以上の積分回路と、0及び±1を出
力とする3値量子化器と帰還回路とで構成されるノイズ
シェイパにおいて、ノイズシェイパの入力信号と前記帰
還回路の1つ以上の出力信号とを前記積分回路に入力す
る接続と、前記積分回路の出力信号を前記量子化器に入
力する接続と、前記量子化器とノイズシェイパの出力端
子との接続とを有し、前記積分回路の少なくとも1つ以
上の積分動作が、1サンプル遅延前の蓄積データと現デ
ータと絶対値が一定値の定数との加算によって実現され
る不完全積分動作であって、前記1サンプル遅延前の蓄
積データが正の時は前記定数の符号を負とし、前記1サ
ンプル遅延前の蓄積データが負あるいは零の時は前記定
数の符号を正とする符号制御回路を有する事を特徴とす
るノイズシェイパ。
3. A noise shaper comprising one or more stages of integrating circuits, a ternary quantizer having 0 and ± 1 as outputs, and a feedback circuit, wherein an input signal of the noise shaper and one or more of the feedback circuits are provided. And a connection for inputting an output signal to the integrating circuit, a connection for inputting an output signal of the integrating circuit to the quantizer, and a connection between the quantizer and an output terminal of a noise shaper. Is an incomplete integration operation realized by adding the accumulated data before one sample delay, the current data and a constant whose absolute value is a constant value, and the accumulation before the one sample delay A noise shaper comprising a sign control circuit for making the sign of the constant negative when the data is positive and for making the sign of the constant positive when the accumulated data before the one-sample delay is negative or zero.
JP3315882A 1991-11-29 1991-11-29 Noise shaper Expired - Lifetime JP2822734B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3315882A JP2822734B2 (en) 1991-11-29 1991-11-29 Noise shaper

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3315882A JP2822734B2 (en) 1991-11-29 1991-11-29 Noise shaper

Publications (2)

Publication Number Publication Date
JPH0722951A true JPH0722951A (en) 1995-01-24
JP2822734B2 JP2822734B2 (en) 1998-11-11

Family

ID=18070739

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3315882A Expired - Lifetime JP2822734B2 (en) 1991-11-29 1991-11-29 Noise shaper

Country Status (1)

Country Link
JP (1) JP2822734B2 (en)

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Publication number Priority date Publication date Assignee Title
WO1999026596A1 (en) 1997-11-21 1999-06-03 The Procter & Gamble Company Fluid delivery system
WO2003093127A1 (en) 2002-04-30 2003-11-13 Yoshino Kogyosho Co.,Ltd. Dispensing container
JP2009088924A (en) * 2007-09-28 2009-04-23 Fujitsu Ltd Method and device for modulating signal, electronic device and signal modulating program

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JPS5911027A (en) * 1982-07-10 1984-01-20 Fujitsu Ltd Adaptive differential pcm system
JPS6119230A (en) * 1984-07-05 1986-01-28 Nec Corp Method and apparatus of over sample coding
JPS6184914A (en) * 1984-10-03 1986-04-30 Sony Corp Noise shaping filter
JPS63238724A (en) * 1987-03-26 1988-10-04 Nippon Precision Saakitsutsu Kk D/a converter
JPS648729A (en) * 1987-07-01 1989-01-12 Sony Corp Da converting circuit
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WO1999026596A1 (en) 1997-11-21 1999-06-03 The Procter & Gamble Company Fluid delivery system
WO2003093127A1 (en) 2002-04-30 2003-11-13 Yoshino Kogyosho Co.,Ltd. Dispensing container
US7104426B2 (en) 2002-04-30 2006-09-12 Yoshino Kogyosho Co., Ltd. Dispensing container
JP2009088924A (en) * 2007-09-28 2009-04-23 Fujitsu Ltd Method and device for modulating signal, electronic device and signal modulating program

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