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JPH0722579A - Input protective circuit - Google Patents

Input protective circuit

Info

Publication number
JPH0722579A
JPH0722579A JP14629093A JP14629093A JPH0722579A JP H0722579 A JPH0722579 A JP H0722579A JP 14629093 A JP14629093 A JP 14629093A JP 14629093 A JP14629093 A JP 14629093A JP H0722579 A JPH0722579 A JP H0722579A
Authority
JP
Japan
Prior art keywords
resistor
semiconductor substrate
potential
input terminal
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14629093A
Other languages
Japanese (ja)
Inventor
Toru Kawashima
亨 川島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP14629093A priority Critical patent/JPH0722579A/en
Publication of JPH0722579A publication Critical patent/JPH0722579A/en
Pending legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To improve a dielectric strength between a semiconductor substrate and a resistor without increasing the thickness of an insulating film by a method wherein the resistor is formed above an electrically independent impurity region with the insulating film therebetween. CONSTITUTION:An electrically independent island-shaped P-type impurity region 15 is formed on the surface region of an N-type semiconductor substrate 10 and a resistor 17 is formed on the semiconductor substrate 10 above the P-type impurity region 15 with an insulating film there-between. A first conducting line 19 which is connected to the one end of the resistor 17 and continued to an input terminal and a second conducting line 20 which is connected to the other end of the resistor 17 and continued to an inner circuit are provided. Further, source/drain regions 14 whose one side ends are connected to the first or second conducting line 19 and 20 and other side ends are connected to a power supply potential or an earth potential and a gate electrode 13 which is laid across the source/drain regions 14 and to which a certain potential is applied are provided. With this constitution, a dielectric strength between the resistor 17 connected to the input terminal and the semiconductor substrate 10 can be improved.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体集積回路装置の
入力端子部分に設けられる入力保護回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input protection circuit provided at an input terminal portion of a semiconductor integrated circuit device.

【0002】[0002]

【従来の技術】半導体メモリ装置等の集積回路装置にお
いては、過剰な電圧または電流を内部回路に伝えないよ
うにする入力保護回路を設けることにより、内部回路を
保護するようにしている。図3は、抵抗とダイオードと
を用いた入力保護回路の回路図である。
2. Description of the Related Art In an integrated circuit device such as a semiconductor memory device, an internal circuit is protected by providing an input protection circuit for preventing excessive voltage or current from being transmitted to the internal circuit. FIG. 3 is a circuit diagram of an input protection circuit using a resistor and a diode.

【0003】入力端子1は、装置の基板上に形成される
アルミニウム電極で構成され、この電極に接続されるリ
ードを介して外部装置からの信号を取り込む。入力端子
1には、保護抵抗2が直列に接続され、この保護抵抗2
に内部回路が接続されることにより、入力信号が保護抵
抗2を介して内部回路に伝えられる。保護抵抗2の内部
回路側には、一対のダイオード3、4が電源電位及び接
地電位に対してそれぞれ逆方向接続され、入力信号のレ
ベルを電源電位と接地電位との間に補償するようにして
いる。即ち、入力端子1の電位が電源電位より高くなっ
たときにダイオード3を通して電流I1を流して電位を
引き下げ、逆に接地電位より低くなったときにダイオー
ド4を通して電流I2を流して電位を引き上げること
で、入力端子1の電位を接地電位と電源電位との間に収
めるようにしている。このような入力保護回路による
と、ノイズ等の影響により入力端子1の電位が一時的に
高く(低く)なりずぎた場合でも、その電位変動が内部
回路に影響を及ぼすことがなくなる。
The input terminal 1 is composed of an aluminum electrode formed on the substrate of the device, and takes in a signal from an external device via a lead connected to this electrode. A protection resistor 2 is connected in series to the input terminal 1, and the protection resistor 2
By connecting the internal circuit to the internal circuit, the input signal is transmitted to the internal circuit via the protection resistor 2. On the internal circuit side of the protection resistor 2, a pair of diodes 3 and 4 are reversely connected to the power supply potential and the ground potential, respectively, so that the level of the input signal is compensated between the power supply potential and the ground potential. There is. That is, when the potential of the input terminal 1 becomes higher than the power source potential, the current I 1 is made to flow through the diode 3 to lower the potential, and conversely, when it becomes lower than the ground potential, the current I 2 is made to flow through the diode 4 and the potential is made lower. By pulling up, the potential of the input terminal 1 is set between the ground potential and the power supply potential. According to such an input protection circuit, even if the potential of the input terminal 1 temporarily becomes high (low) due to the influence of noise or the like, the potential fluctuation does not affect the internal circuit.

【0004】ところで、上述の如き入力保護回路が設け
られた集積回路装置において、動作電源の低電圧化が図
られると、従来の電圧で動作する装置と接続される際、
入力保護回路を構成するダイオードに定常的な電流が流
れて誤動作するおそれがある。例えば、入力保護回路が
形成される装置の電源が3Vに設定された場合、5Vの
電源で動作する装置が接続されると、入力端子1に与え
られる信号も5Vの波形となる。このため、正常な信号
が与えられているにも拘わらず入力端子1から電源側に
定常的に電流I1が流れて電源電位が上昇し、内部回路
を誤動作させることになる。
By the way, in the integrated circuit device provided with the input protection circuit as described above, if the operating power source is lowered in voltage, when it is connected to a device operating at a conventional voltage,
There is a risk that a steady current will flow through the diode that constitutes the input protection circuit, causing a malfunction. For example, when the power supply of the device in which the input protection circuit is formed is set to 3V and the device that operates with the power supply of 5V is connected, the signal applied to the input terminal 1 also has a waveform of 5V. Therefore, although the normal signal is given, the current I 1 constantly flows from the input terminal 1 to the power supply side, the power supply potential rises, and the internal circuit malfunctions.

【0005】そこで、動作電源の低電圧化が図られる集
積回路装置では、図4に示すようなトランジスタを用い
た入力保護回路が採用される。この入力保護回路は、図
3の入力保護回路のダイオード3、4を一対のMOSト
ランジスタ5、6に置き換えたもので、保護抵抗2の内
部回路側と電源電位及び接地電位との間にそれぞれMO
Sトランジスタ5、6を接続して構成される。MOSト
ランジスタ5、6については、ゲート電位の固定により
定常的にオフ状態とされるもので、Nチャネル型の場
合、図4の如くゲートは接地電位に固定される。このよ
うな入力保護回路においては、入力端子1の電位と接地
電位との電位差がMOSトランジスタ6のソース/ドレ
イン間の耐圧を越えたときにパンチスルー動作によって
接地側に電流が流れ、その結果入力端子1の電位が引き
下げられる。このため、入力端子1の電位がMOSトラ
ンジスタ6の耐圧を越えない範囲で高くなったとしても
入力保護回路は動作せず、動作電源の異なる装置の出力
を入力端子1に受けることが可能となる。一方、入力端
子1の電位の低下に対しては、接地電位よりもMOSト
ランジスタ5の閾値分だけ低くなったときにMOSトラ
ンジスタ5がオン状態となり、電源側から入力端子1に
電流が流れ込んで入力端子1の電位が引き上げられる。
但し、入力端子1の電位が上昇して接地電位との差がM
OSトランジスタ5の閾値電圧より小さくなると、MO
Sトランジスタ5はオフ状態となり、電位の上昇は止ま
る。
Therefore, in an integrated circuit device in which the operating power supply voltage can be lowered, an input protection circuit using a transistor as shown in FIG. 4 is adopted. This input protection circuit is obtained by replacing the diodes 3 and 4 of the input protection circuit of FIG. 3 with a pair of MOS transistors 5 and 6, and is provided between the internal circuit side of the protection resistor 2 and the power supply potential or the ground potential.
It is configured by connecting the S transistors 5 and 6. The MOS transistors 5 and 6 are constantly turned off by fixing the gate potential. In the case of the N-channel type, the gates are fixed to the ground potential as shown in FIG. In such an input protection circuit, when the potential difference between the potential of the input terminal 1 and the ground potential exceeds the withstand voltage between the source / drain of the MOS transistor 6, a current flows to the ground side by the punch-through operation, resulting in the input. The potential of terminal 1 is lowered. Therefore, even if the potential of the input terminal 1 rises within a range that does not exceed the withstand voltage of the MOS transistor 6, the input protection circuit does not operate, and the input terminal 1 can receive the output of a device having a different operating power supply. . On the other hand, with respect to the decrease in the potential of the input terminal 1, the MOS transistor 5 is turned on when it becomes lower than the ground potential by the threshold value of the MOS transistor 5, and a current flows from the power supply side to the input terminal 1 The potential of terminal 1 is raised.
However, the potential of the input terminal 1 rises and the difference from the ground potential is M
If it becomes smaller than the threshold voltage of the OS transistor 5, MO
The S transistor 5 is turned off, and the potential rise stops.

【0006】[0006]

【発明が解決しようとする課題】以上の入力保護回路に
おいては、保護抵抗2を半導体基板上に積層した抵抗体
によって形成しているため、半導体基板と抵抗体との間
の耐圧の確保が課題となっている。耐圧の確保は、半導
体基板と抵抗体との間に介在する絶縁膜の膜厚を厚くす
ることにより対応可能であるが、膜厚を厚くすることは
ステップカバレッジを低下させることから、回路パター
ンを微細化する際には製造歩留まりを低下させる要因と
なる。
In the above-mentioned input protection circuit, since the protection resistor 2 is formed by the resistor body laminated on the semiconductor substrate, it is a problem to secure the breakdown voltage between the semiconductor substrate and the resistor body. Has become. The withstand voltage can be ensured by increasing the film thickness of the insulating film interposed between the semiconductor substrate and the resistor, but increasing the film thickness lowers the step coverage. When miniaturizing, it becomes a factor that reduces the manufacturing yield.

【0007】そこで本発明は、絶縁膜の膜厚を厚くする
ことなく半導体基板と抵抗体との耐圧を確保することを
目的とする。
Therefore, an object of the present invention is to secure the breakdown voltage between the semiconductor substrate and the resistor without increasing the thickness of the insulating film.

【0008】[0008]

【課題を解決するための手段】本発明は上述の課題を解
決するために成されたもので、その特徴とするところ
は、入力端子と内部回路との間に保護抵抗が直列に接続
され、この保護抵抗の一端に保護トランジスタが接続さ
れる入力保護回路において、一導電型の半導体基板の表
面領域に電気的に独立して島状に形成された逆導電型の
不純物領域と、この不純物領域と対応して上記半導体基
板上に絶縁膜を介して形成される抵抗体と、この抵抗体
の一端に接続されて上記入力端子に連続する第1の導電
線と、上記抵抗体の他端に接続されて上記内部回路につ
ながる第2の導電線と、上記半導体基板の表面領域に形
成され、一方が上記第1あるいは第2の導電線に接続さ
れて他方が電源電位あるいは接地電位に接続される少な
くとも一対のソース/ドレイン領域と、これらソース/
ドレイン領域の間に跨って上記半導体基板上に形成され
て一定の電位が与えられる少なくとも1つのゲート電極
と、を備えることにある。
The present invention has been made to solve the above-mentioned problems, and is characterized in that a protection resistor is connected in series between an input terminal and an internal circuit, In an input protection circuit in which a protection transistor is connected to one end of the protection resistor, an impurity region of opposite conductivity type electrically isolated from the surface region of a semiconductor substrate of one conductivity type and formed in an island shape, and the impurity region Corresponding to, a resistor formed on the semiconductor substrate via an insulating film, a first conductive line connected to one end of the resistor and connected to the input terminal, and the other end of the resistor on the other end. A second conductive line connected to the internal circuit and formed on a surface region of the semiconductor substrate, one of which is connected to the first or second conductive line and the other of which is connected to a power supply potential or a ground potential. At least a pair of sauces And the drain region, these source /
At least one gate electrode formed on the semiconductor substrate and provided with a constant potential across the drain region.

【0009】[0009]

【作用】本発明によれば、電気的に独立した不純物領域
上に絶縁膜を介して抵抗体を形成することで、絶縁膜の
膜厚に加えて、不純物領域の深さの分だけ抵抗体と半導
体基板との実質的な距離が拡がるため、半導体基板と抵
抗体との間の耐圧が高くなる。
According to the present invention, the resistor is formed on the electrically independent impurity region via the insulating film, so that the resistor is formed by the depth of the impurity region in addition to the film thickness of the insulating film. Since the substantial distance between the semiconductor substrate and the semiconductor substrate is increased, the breakdown voltage between the semiconductor substrate and the resistor is increased.

【0010】[0010]

【実施例】図1は、本発明の入力保護回路の構造を示す
平面図で、図2は、そのX−X線の断面図である。N型
の半導体基板10の表面領域には、素子形成領域となる
電位固定されたP型の拡散層11が形成され、この拡散
層11上に薄い酸化膜12を介して多結晶シリコンから
なるゲート電極13が形成される。拡散層11内におい
ては、ゲート電極12をマスクとしてN型の不純物が注
入されたソース/ドレイン領域14が形成され、ゲート
電極13と共にNチャンネル型のMOSトランジスタが
構成される。また、拡散層11に隣接する半導体基板1
0の表面領域には、電気的に独立したP型の拡散層15
が形成され、この拡散層15上に選択酸化法によって厚
く形成された酸化膜16を介して多結晶シリコンからな
る抵抗体17が形成される。この抵抗体17は、半導体
基板10に形成される拡散層15の範囲内に収まるよう
に形成される。なお、拡散層15及び抵抗体17は、素
子形成領域の拡散層11及びMOSトランジスタのゲー
ト電極13とそれぞれ同一のものであり、同一工程によ
って形成される。
1 is a plan view showing the structure of an input protection circuit of the present invention, and FIG. 2 is a sectional view taken along line XX of FIG. A potential-fixed P-type diffusion layer 11 serving as an element formation region is formed in the surface region of the N-type semiconductor substrate 10, and a gate made of polycrystalline silicon is formed on the diffusion layer 11 via a thin oxide film 12. The electrode 13 is formed. In diffusion layer 11, source / drain regions 14 into which N-type impurities have been implanted are formed using gate electrode 12 as a mask, and N-channel type MOS transistor is formed together with gate electrode 13. In addition, the semiconductor substrate 1 adjacent to the diffusion layer 11
In the surface region of 0, an electrically independent P-type diffusion layer 15 is formed.
Is formed, and a resistor 17 made of polycrystalline silicon is formed on the diffusion layer 15 through an oxide film 16 thickly formed by a selective oxidation method. The resistor 17 is formed so as to be within the range of the diffusion layer 15 formed on the semiconductor substrate 10. The diffusion layer 15 and the resistor 17 are the same as the diffusion layer 11 in the element formation region and the gate electrode 13 of the MOS transistor, and are formed by the same process.

【0011】そして、ゲート電極13及び抵抗体17を
被うようにして半導体基板10上に層間絶縁膜18が形
成され、この層間絶縁膜18上に各種のアルミニウム配
線19〜22が形成される。入力端子を成すアルミニウ
ム配線19は、コンタクトホール23を通して抵抗体1
7の一端に接続され、入力端子に与えられる信号を抵抗
体17に印加する。内部回路につながるアルミニウム配
線20は、コンタクトホール24を通して抵抗体17の
他端に接続されて入力端子から入力される信号を内部回
路に伝えると共に、コンタクトホール25を通して、保
護用のMOSトランジスタのソース/ドレイン領域14
に接続される。接地電位が印加されるアルミニウム配線
21は、コンタクトホール26及び27を通してMOS
トランジスタのソース/ドレイン領域14の一方及びゲ
ート電極13に接続され、MOSトランジスタのゲート
及びソースの電位を接地電位に固定する。さらに、電源
電位が印加されるアルミニウム配線22は、コンタクト
ホール28を通してMOSトランジスタのソース/ドレ
イン領域14の他方に接続され、MOSトランジスタの
ドレインの電位を電源電位に固定する。
Then, an interlayer insulating film 18 is formed on the semiconductor substrate 10 so as to cover the gate electrode 13 and the resistor 17, and various aluminum wirings 19 to 22 are formed on the interlayer insulating film 18. The aluminum wiring 19 forming the input terminal is connected to the resistor 1 through the contact hole 23.
A signal applied to the input terminal is applied to the resistor 17, which is connected to one end of the resistor 7. The aluminum wiring 20 connected to the internal circuit is connected to the other end of the resistor 17 through the contact hole 24 to transmit the signal input from the input terminal to the internal circuit, and through the contact hole 25, the source / source of the protection MOS transistor. Drain region 14
Connected to. The aluminum wiring 21 to which the ground potential is applied is connected to the MOS through the contact holes 26 and 27.
It is connected to one of the source / drain regions 14 of the transistor and the gate electrode 13, and fixes the gate and source potentials of the MOS transistor to the ground potential. Further, the aluminum wiring 22 to which the power supply potential is applied is connected to the other of the source / drain regions 14 of the MOS transistor through the contact hole 28 and fixes the potential of the drain of the MOS transistor to the power supply potential.

【0012】以上の構造によれば、抵抗体17を保護抵
抗とし、ゲート電極13及びソース/ドレイン領域14
よりなるMOSトランジスタが、保護抵抗と電源電位及
び接地電位との間に接続され、図4に示すような入力保
護回路が構成される。ここで、抵抗体17は、酸化膜1
6及び拡散層15により半導体基板10から離されるた
め、酸化膜16の耐圧に加えて拡散層15が形成される
深さの分だけ耐圧が増すことになる。
According to the above structure, the resistor 17 serves as a protective resistor, and the gate electrode 13 and the source / drain region 14 are provided.
The MOS transistor is connected between the protection resistor and the power supply potential or the ground potential to form an input protection circuit as shown in FIG. Here, the resistor 17 is the oxide film 1
6 and the diffusion layer 15 separate from the semiconductor substrate 10, the breakdown voltage is increased by the depth of the diffusion layer 15 in addition to the breakdown voltage of the oxide film 16.

【0013】尚、以上の実施例においては、半導体基板
10をN型とし、MOSトランジスタをNチャンネル型
とした場合を例示したが、半導体基板10及びMOSト
ランジスタの導電型は、P型であっても差し支えない。
但し、MOSトランジスタをP型とする場合にはゲート
に印加する電位を電源電位とする必要がある。また、電
源電位と接地電位との間に接続されるMOSトランジス
タは、抵抗体17の入力端子側に接続するようにしても
よい。
In the above embodiments, the semiconductor substrate 10 is N-type and the MOS transistor is N-channel type. However, the conductivity type of the semiconductor substrate 10 and the MOS transistor is P-type. It doesn't matter.
However, when the MOS transistor is P-type, the potential applied to the gate needs to be the power supply potential. Further, the MOS transistor connected between the power supply potential and the ground potential may be connected to the input terminal side of the resistor 17.

【0014】[0014]

【発明の効果】本発明によれば、入力端子に接続される
保護抵抗と半導体基板との間の耐圧を向上することがで
き、装置の信頼性を高めることができる。また、保護抵
抗と半導体基板との間を絶縁する絶縁膜の膜厚を薄くで
きることから、ステップカバレッジが良好になり、製造
歩留まりの低下を防止できる。
According to the present invention, the breakdown voltage between the protective resistor connected to the input terminal and the semiconductor substrate can be improved, and the reliability of the device can be improved. In addition, since the thickness of the insulating film that insulates between the protective resistor and the semiconductor substrate can be reduced, the step coverage is improved and the manufacturing yield can be prevented from lowering.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の入力保護回路の構造を示す平面図であ
る。
FIG. 1 is a plan view showing a structure of an input protection circuit of the present invention.

【図2】図1のX−X線の断面図である。FIG. 2 is a sectional view taken along line XX of FIG.

【図3】ダイオードを用いた入力保護回路の回路図であ
る。
FIG. 3 is a circuit diagram of an input protection circuit using a diode.

【図4】MOSトランジスタを用いた入力保護回路の回
路図である。
FIG. 4 is a circuit diagram of an input protection circuit using a MOS transistor.

【符号の説明】[Explanation of symbols]

1 入力端子 2 保護抵抗 3、4 ダイオード 5、6 MOSトランジスタ 10 半導体基板 11、15 P型拡散層 12、16 酸化膜 13 ゲート電極 14 ソース/ドレイン領域 17 抵抗体 18 層間絶縁膜 19〜22 アルミニウム配線 23〜28 コンタクトホール 1 Input Terminal 2 Protection Resistor 3, 4 Diode 5, 6 MOS Transistor 10 Semiconductor Substrate 11, 15 P-type Diffusion Layer 12, 16 Oxide Film 13 Gate Electrode 14 Source / Drain Region 17 Resistor 18 Interlayer Insulating Film 19-22 Aluminum Wiring 23 to 28 contact holes

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 入力端子と内部回路との間に保護抵抗が
直列に接続され、この保護抵抗の一端に保護トランジス
タが接続される入力保護回路において、一導電型の半導
体基板の表面領域に電気的に独立して島状に形成された
逆導電型の不純物領域と、この不純物領域と対応して上
記半導体基板上に絶縁膜を介して形成される抵抗体と、
この抵抗体の一端に接続されて上記入力端子に連続する
第1の導電線と、上記抵抗体の他端に接続されて上記内
部回路につながる第2の導電線と、上記半導体基板の表
面領域に形成され、一方が上記第1あるいは第2の導電
線に接続されて他方が電源電位あるいは接地電位に接続
される少なくとも一対のソース/ドレイン領域と、これ
らソース/ドレイン領域の間に跨って上記半導体基板上
に形成されて一定の電位が与えられる少なくとも1つの
ゲート電極と、を備えることを特徴とする入力保護回
路。
1. In an input protection circuit in which a protection resistor is connected in series between an input terminal and an internal circuit, and a protection transistor is connected to one end of the protection resistor, an electric field is formed on a surface region of a semiconductor substrate of one conductivity type. Oppositely-conducting impurity regions formed independently in an island shape, and a resistor formed corresponding to the impurity regions on the semiconductor substrate via an insulating film,
A first conductive line connected to one end of the resistor and continuous to the input terminal, a second conductive line connected to the other end of the resistor and connected to the internal circuit, and a surface region of the semiconductor substrate. And at least one pair of source / drain regions connected to the first or second conductive line and the other connected to the power supply potential or the ground potential, and the source / drain regions. An input protection circuit, comprising: at least one gate electrode formed on a semiconductor substrate and supplied with a constant potential.
JP14629093A 1993-06-17 1993-06-17 Input protective circuit Pending JPH0722579A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14629093A JPH0722579A (en) 1993-06-17 1993-06-17 Input protective circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14629093A JPH0722579A (en) 1993-06-17 1993-06-17 Input protective circuit

Publications (1)

Publication Number Publication Date
JPH0722579A true JPH0722579A (en) 1995-01-24

Family

ID=15404344

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14629093A Pending JPH0722579A (en) 1993-06-17 1993-06-17 Input protective circuit

Country Status (1)

Country Link
JP (1) JPH0722579A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11176948A (en) * 1997-12-08 1999-07-02 Nec Ic Microcomput Syst Ltd Semiconductor integrated circuit
JP2009038100A (en) * 2007-07-31 2009-02-19 Sanyo Electric Co Ltd Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11176948A (en) * 1997-12-08 1999-07-02 Nec Ic Microcomput Syst Ltd Semiconductor integrated circuit
JP2009038100A (en) * 2007-07-31 2009-02-19 Sanyo Electric Co Ltd Semiconductor device

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