JPH07202789A - Digital radio terminal equipment - Google Patents

Abstract

PURPOSE:To provide a digital radio terminal whose high frequency section is available for high speed control in which power saving is realized. CONSTITUTION:In the communication mode, a switch 1225 (1235) of a low noise amplifier(LNA) 1221 of a reception section 122 (power amplifier(PA) 1231 of a transmission section 123 is closed to receive a power supply Vcc, and gate bias switches 1226, 1236 are turned on/off in a timing for a prescribed slot of one frame transmission reception period. On the other hand, in the standby mode, the switch 1225 is connected to the power supply Vcc for the low noise amplifier(LNA) 1221 of the reception section 122 in a timing of one-super-frame reception (RX) period, and the switch 1235 of the power amplifier (PA) 1231 of the transmission section 123 is always turned off.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time-division multiplex type digital wireless terminal device which realizes power saving (power saving).

[0002]

2. Description of the Related Art Recently, a time-division multiplex type digital wireless terminal device has been widely used as a portable terminal device capable of calling a caller from outside to talk.

By the way, in such a portable radio terminal device, in order to minimize the increase in the battery life and the temperature rise due to the heat generation of the device itself due to the limitation of the battery capacity and the like,
Normally, power saving is performed individually for each circuit.

FIG. 5 shows a partial schematic structure of an antenna section and a high frequency section of a digital wireless terminal device, wherein 1 is an antenna section, and a high frequency section 2 is connected to the antenna section 1. The high frequency unit 2 performs frequency conversion processing, and connects the reception unit 22 and the transmission unit 23 via the antenna switch unit 21. The receiver 22 has a low noise amplifier (LNA) 221, and the transmitter 23 has a power amplifier (PA) 231. Here, the low noise amplifier (LNA) 221 includes an amplification FET 222 and a load 22.
3. The decoupling capacitor 224 is provided, the power supply Vcc is connected to the decoupling capacitor 224 via the switch 225, and the gate bias voltage VG2 that optimizes the operation is applied to the amplification FET 222. Further, the power amplifier (PA) 231 is also an FE for amplification.
T232, load 233, decoupling capacitor 23
4, the decoupling capacitor 234 is connected to the power supply Vcc via the switch 235, and the amplification FET 23
2, the gate bias voltage VG4 is applied so that its operation is optimal.

However, in such a configuration, when in the communication mode now, the low noise amplifier (LNA) 221 of the receiving section 22 connected to the antenna 21 via the antenna switch section 21 is shown in FIG. ) As shown in (b) and (c), with the gate bias voltage VG2 connected to the amplification FET 222, the switch 225 is turned on at the timing of a predetermined slot (slot 2 in the illustrated example) in the reception (RX) period of the TDMA1 frame. The power supply Vcc is connected to secure the reception state of the burst signal, and the power amplifier (PA) 231 of the transmission unit 23 connected to the antenna 21 via the antenna switch unit 21 is an amplification FET.
With the gate bias voltage VG4 connected to H.232,
The switch 23 at the timing of a predetermined slot (slot 2 in the illustrated example) in the transmission (TX) period of the DMA1 frame.
By turning on 5 and connecting the power supply Vcc, the transmission state of the burst signal is ensured.

In the standby mode, the receiver 2
The low noise amplifier (LNA) 221 of No. 2 has the configuration shown in FIG.
As shown in (b) and (c), the TDMA1 superframe is received (R
At the timing of the period X), the switch 225 of the receiving unit 22 is turned on to connect the power supply Vcc to secure the waiting for reception.

[0007]

However, according to such a configuration, the switch 22 connected to the power supply Vcc is used.
Reference numerals 5 and 235 each have a contact resistance, and since decoupling capacitors 224 and 234 having a large capacity are connected to this power supply line, the charging / discharging time according to the time constant determined by these is the length of one frame of TDMA. 5m
s cannot be neglected, which makes it impossible to cope with high-speed control, and the switches 225, 235
There is a problem in that the power saving effect is reduced by the increase in the pulse width of the control signal for turning on.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a digital wireless terminal device capable of high-speed control of a high frequency section and realizing power saving.

[0009]

According to the present invention, in a digital wireless terminal device having a high frequency unit for transmitting and receiving a radio signal, the high frequency unit has a low noise amplifier, and a first unit for the low noise amplifier is provided. A communication unit including a power supply switch and a reception unit having a first amplification degree changeover switch; and a transmission unit having a power amplifier and having a second power supply switch and a second amplification degree changeover switch for the power amplifier. Then, the first and second power switches are turned on, the optimum amplification degree is selected by the first and second changeover switches at the timing of each predetermined slot in the transmission / reception period of each frame, and in the standby mode, The second power switch is turned off and the first power switch is turned on during a reception period of a predetermined slot. It is configured to turn on control ring.

[0010]

As a result, according to the present invention, in the call mode,
The first power switch for the low noise amplifier of the receiver and the second power switch for the power amplifier of the transmitter are kept in the ON state, and the low noise amplifier is supplied to the low noise amplifier at the timing of each predetermined slot in the transmission / reception period of each frame. Since the optimum gate bias is selected by the first changeover switch and the second changeover switch for the power amplifier, there is no influence of the charge / discharge time due to the time constant circuit of the power supply line, and the control signal is provided. The pulse width of can be narrowed.

In the standby mode, the second power switch for the power amplifier of the transmitter is turned off and the first power switch for the low noise amplifier of the receiver is turned on at the timing of the reception period of each superframe. Since the control is performed, the influence of the charging / discharging time of the time constant circuit included in the power supply line can be ignored, and the leak current in the power amplifier can be suppressed to a negligible level.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a schematic configuration of the same embodiment.
In the figure, reference numeral 11 denotes an antenna, and a high frequency section 12 is connected to the antenna 11. This high frequency part 12
Performs frequency conversion processing, and details will be described later.
Antenna switch unit 121, receiving unit 122, transmitting unit 12
3 and PLL synthesizer 124.

Here, the antenna switch section 121 receives the input signal from the antenna 11 to the receiving section 122 and the transmitting section 1
The output signal from 24 is distributed to each antenna 11. The reception unit 122 receives the reception signal input from the antenna 11 via the antenna switch unit 121.
Convert frequency from 1.9GHz to 1 by stage mixer
An IF signal of 50 to 250 MHz and 10 MHz is generated. The transmitting unit 123 frequency-converts a π / 4-shift QPSK modulated wave input from the modem 13 described later into 1.9 GHz by a mixer and outputs the frequency-modulated wave to the antenna 11 via the antenna switch unit 121. Then, the PLL synthesizer 124 performs local oscillation for frequency conversion in the receiving unit 122 and the transmitting unit 123.

The high frequency section 12 has a modem 13
TDMA14, speech codec 15 and PCM
16, a speaker 18 on the receiving side and a microphone 19 on the transmitting side are connected to the PCM 16 via an amplifier 17.

Here, the modem 13 uses a π / 4 shift QP
It performs SK modulation and demodulation processing, and at the receiving side, the receiving unit 1
The IF signal from 22 is demodulated and separated into IQ data,
The data is transferred to the TDMA 14 as a data string, and on the transmitting side, IQ data is created from the data transferred from the TDMA 14, and π / 4 shift QPSK modulation is performed and the IQ data is sent to the transmitting unit 124.

The TDMA 14 performs frame synchronization and slot format processing. On the receiving side, the scramble of the data of the predetermined slot sent from the modem 13 is descrambled, and the configuration data is extracted from the format of this slot. , Sends control data to the control unit 20 described later, transfers voice data to the speech codec 15, and at the transmitting side, adds control data to the voice data transferred from the speech codec 15 to create slot data. Then, the data is scrambled, the slot data is inserted into the frame at a predetermined timing (allocated time slot for transmission), and the modem 13
I am trying to transfer to.

The speech codec 15 performs compression / expansion processing of digital data.
ADPCM audio signal (4bi) sent from MA14
t × 8 KHz = 32 Kbps for PCM audio signal (8 b
(it × 8 KHz = 64 Kbps), it is expanded by decoding and output to PCM16.
The PCM voice signal sent from the D.6 is compressed by being encoded into the ADPCM voice signal and sent to the TDMA 14.

The PCM 16 performs analog / digital processing. On the receiving side, the PCM audio signal sent from the speech codec 15 is converted into an analog signal by D / A conversion, and then output to the amplifier 17 to be a speaker. 18 and a microphone 19 on the transmitting side.
A / D conversion of the analog audio signal input from the PC
The M audio signal is output to the speech codec 15. The PCM 16 also controls a volume, a ringer, a tone signal and the like.

The high frequency section 12 and the modem 1
3, TDMA14, speech codec 15 and P
A control unit 20 is connected to the CM 16 and the control unit 20
ROM 21, RAM 22, recording / reproducing circuit 23, memory 2
4, the display unit 25 and the key input unit 26 are connected.

Here, the ROM 21 stores the control program in the control unit 20. The RAM 22 temporarily stores the data handled by the control of the control unit 20. Further, the recording / reproducing circuit 23 records and reproduces a message when it is used as an answering machine. The memory 24 stores a standard message when used as an answering machine. The display unit 25 displays input data and results for various controls. The key input unit 26 is adapted to give a key input for setting various functions to the control unit 20.

FIG. 2 shows a schematic structure of only the main part of the high frequency section 12. In this case, the receiving unit 122 and the transmitting unit 12 are provided to the antenna 11 via the antenna switch unit 121.
3 are connected.

The receiver 122 is a low noise amplifier (LNA).
1221, and the transmission unit 123 includes a power amplifier (PA).
It has 1231.

Here, the low noise amplifier (L
(NA) 1221 is an amplification FET 1222 and a load 122.
3, a decoupling capacitor 1224 is provided, the power supply Vcc is connected to the decoupling capacitor 1224 via a switch 1225, and the amplification FET 122 is also provided.
2 to the amplification FET 122 via the switch 1226.
The gate bias voltage VG1 at which 2 is cut off or the gate bias voltage VG2 at which the operation of the amplification FET 1222 is optimal is selectively applied.

On the other hand, the power amplifier (PA) of the transmitter 123
1231 includes an amplification FET 1232, a load 1233, and a decoupling capacitor 1234. The decoupling capacitor 1234 is connected to a power supply Vcc via a switch 1235, and the amplification FET 1232 is amplified via a switch 1236. The gate bias voltage VG3 at which the power FET 1232 is cut off or the gate bias voltage VG4 at which the operation of the amplification FET 1232 is optimal is selectively applied.

By switching the gate bias voltage in this manner, the amplification degree of the amplification EFT 1222 and 1232 can be varied to enable burst control.

Next, the operation of the embodiment configured as described above will be described.

Now, in the call mode of the digital wireless terminal device shown in FIG. 1, when a call signal is input from the partner subscriber through the antenna 11, the high frequency section 12 causes the modem 1 to operate.
3, TDMA14, speech codec 15 and P
When a voice is output from the speaker 18 on the receiving side via the CM 16 and a call signal is input from the microphone 19 on the transmitting side, the speech codec 1 from the PCM 16 is input.
5, the TDMA 14, the modem 13, and the high frequency unit 12 output from the antenna 11 to the other subscriber.

In this case, in this communication mode, the antenna 1 is passed through the antenna switch unit 121 of the high frequency unit 12.
1 is connected to a low noise amplifier (LN
A) In 1221, as shown in FIG. 3B, the switch 1225 is turned on and the power supply Vcc is kept connected, and a predetermined slot (in the example shown in the figure) in the reception (RX) period of the TDMA1 frame in FIG. At the timing of slot 2), as shown in FIG. 7C, the switch 1226 is switched from the gate bias voltage VG1 side that substantially deactivates the amplification FET 1222 to the gate bias voltage VG2 side where the amplification FET 1222 operates optimally. By switching and applying this gate bias voltage VG2 to the amplification FET 1222, the reception state is secured.

In the transmission section 123 connected to the antenna 11 via the antenna switch section 121, in the power amplifier (PA) 1231, the switch 1235 is turned on to connect the power supply Vcc as shown in FIG. 3B. The transmission of the TDMA1 frame shown in FIG.
Operation of the amplification FET 1232 from the side of the gate bias voltage VG3 that causes the switch 1236 to substantially deactivate the amplification FET 1232 at a timing of a predetermined slot (slot 2 in the illustrated example) of the period X) as shown in FIG. Is switched to the optimum gate bias voltage VG4 side and this gate bias voltage VG4 is applied to the amplification FET 1232 to secure the transmission state.

Therefore, in such a communication mode, the low noise amplifier (LNA) 1221 of the receiver 122 and the power amplifier (PA) 1231 of the transmitter 123 both turn on the switches 1225 and 1235 to connect the power supply Vcc. The switch 122 on the gate bias side is left at the timing of a predetermined slot in the transmission / reception period of one frame.
Since 6 and 1236 are turned on and off, compared to the conventional one that turns on and off the power supply line to which a large-capacity decoupling capacitor is connected, there is no influence of the charge and discharge time of the time constant circuit by the capacitor,
High-speed control of the high frequency part is possible. In addition, amplification FET
Since the gate bias voltages of 1222 and 1232 are switched to the VG1 side and VG3 during the non-reception slot and the non-transmission slot, respectively, and the leakage current is suppressed to a low level, the power consumption can also be ignored.

On the other hand, in the standby mode, the receiving unit 1
The 22 low noise amplifiers (LNA) 1221 shown in FIG.
Reception of the TDMA1 superframe shown in (a) (R
At the timing of the period X), the switch 1225 is turned on to connect the power supply Vcc as shown in FIG. 7C, and the switch 1226 is amplified from the gate bias voltage VG1 side at the same timing as shown in FIG. FET
Switching to the side of the gate bias voltage VG2 that optimizes the operation of 1222, and this gate bias voltage VG2 is used for amplification FE
It is applied to T1222. Further, in the power amplifier (PA) 1231 of the transmitter 123, the switch 1235 is always turned off, and the switch 1236 is set to the gate bias voltage V.
It is switched to the G3 side or the gate bias voltage VG4 side.

Therefore, in the standby mode as described above,
The low noise amplifier (LNA) 1221 of the receiving unit 122 is 1
The connection of the power supply Vcc is turned on / off by the switch 1225 at the timing of the reception (RX) period of the super frame, but the reception (R
Since the cycle of the X) period is much longer than the cycle of the receiving period in the call mode, the influence of the charge / discharge time of the time constant by the capacitor 1224 accompanying the switching of the power supply line can be ignored. Moreover, the power amplifier (PA) of the transmitter 123
In 1231, since the power supply switch 1235 is always turned off, the leakage current in the power amplifier (PA) 1231 can be suppressed to a negligible level, and thus power saving in such a standby mode can also be realized. it can.

The present invention is not limited to the above-mentioned embodiments, but can be carried out by appropriately modifying it within the scope of the invention. For example, in the above-described embodiment, the low noise amplifier (LNA) 1221 of the receiver 122 and the power amplifier (PA) 1231 of the transmitter 123 both use the FET 1 for amplification, but these are basic bipolar transistors. Even if it is replaced with, the same effect can be expected.

[0035]

As described above, according to the present invention, in the call mode, the first power switch for the low noise amplifier of the receiver and the second power switch for the power amplifier of the transmitter are kept in the ON state. Thus, the optimum gate bias is selected by the first changeover switch for the low noise amplifier and the second changeover switch for the power amplifier at the timing of each predetermined slot in the transmission / reception period of each frame. It is possible to realize high-speed control of the high frequency part without being affected by the charging / discharging time by the time constant circuit that it has, and also to realize power saving because the pulse width of the control signal can be narrowed.

In the standby mode, the second power switch for the power amplifier of the transmitter is turned off and the first power switch for the low noise amplifier of the receiver is turned on at the timing of the reception period of the predetermined slot. Therefore, the influence of the charging / discharging time of the time constant circuit of the power supply line can be ignored, and the leakage current in the power amplifier can be suppressed to a negligible level. It can also be realized.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic configuration of a time division multiplexing digital wireless terminal device used in an embodiment of the present invention.

FIG. 2 is a diagram showing a schematic configuration of a high frequency unit of one embodiment.

FIG. 3 is a diagram for explaining the operation of the embodiment.

FIG. 4 is a diagram for explaining the operation of the embodiment.

FIG. 5 is a diagram showing a schematic configuration of a high frequency unit of a conventional digital wireless terminal device.

FIG. 6 is a diagram for explaining the operation of the high frequency unit.

FIG. 7 is a diagram for explaining the operation of the high frequency unit.

[Explanation of symbols]

 11 ... Antenna, 12 ... High frequency part, 121 ... Antenna switch part, 122 ... Receiving part, 1221 ... Low noise amplifier (LNA), 1222 ... Amplification FET, 1223 ... Load, 1224 ... Decoupling capacitor, 1225 ... Switch, 1226 ... switch, 123 ... transmission part, 1231 ... power amplifier (PA), 1232 ... FET for amplification, 1233 ... load, 1234 ... decoupling capacitor, 1235 ... switch, 1236 ... switch, 124 ... PLL synthesizer, 13 ... modem, 14 ... TDMA, 15 ... Speech codec, 16 ... PCM, 17 ... Amplifier, 18 ... Receiving side speaker, 19 ... Microphone, 20 ... Control section, 21 ... ROM, 22 ... RAM, 23 ... Recording / reproducing circuit, 24 ... Memory, 25 ... Display, 26 ... Enter key Power department.

Claims (1)

[Claims] 1. A digital wireless terminal device having a high-frequency unit for transmitting and receiving radio signals, wherein the high-frequency unit has a low-noise amplifier, and a first power switch and a first amplification degree changeover switch for the low-noise amplifier. A receiver having a power amplifier, and a transmitter having a power amplifier and a second power switch and a second amplification switch for the power amplifier. In a communication mode, the first and second power supplies are provided. The switch is turned on, and the optimum amplification degree is selected by the first and second changeover switches at the timing of each predetermined slot in the transmission / reception period of each frame. In the standby mode, the second power switch is turned off. In addition, the first power switch is ON-controlled at the timing of the reception period of a predetermined slot. Digital wireless terminal device to.