JPH07200652A - Circuit simulation device - Google Patents

Abstract

PURPOSE:To produce a simulator while confirming visually the selection of a simulation model when a circuit including plural simulation models is designed. CONSTITUTION:The location and the generating times point of the design data 1 are registered on a library management part 2 and applied to a compiler 6. The hierarchical structure of the compiling result 7 is analyzed at the part 2 and this analyzing result is sent to a design hierarchy browser 3 where the design hierarchy is displayed. Thus a desired simulation model is selected based on the display of the design hierarchy. Then the entire configuration 5 of a circuit is outputted by the browser 3. A simulator producing part 4 outputs the instructions to the compiler 6 and a linker 9 based on the hierarchical information and the location information on the data 1. Based on these instructions, the configuration 5 is applied to the compiler 6. Thus the result 7 is acquired and linked with a simulator kernel 8 by the linker 9. In such a way, a simulator 10 is acquired.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit simulation device, and more particularly to a circuit simulation device which uses a hardware description language for electrical system logic simulation.

[0002]

2. Description of the Related Art In recent years, in designing a large-scale logic circuit, a gate-level circuit drawing is written, and the whole is constructed by combining them, and then the entire functional design is performed. We are moving to a top-down design method in which functional leaks and interfaces are matched at each stage, they are divided into blocks according to function, and each block is similarly divided into blocks. The hard-veer description language is indispensable for realizing the top-down design. Using a hard-veer description language that supports from gate-level description to abstract behavioral description, the top-level functional design is described at the abstract behavioral level, the whole is verified, and then divided into blocks. Also, describe at the behavior level. This process is repeated, and when it is simplified to a certain extent, the level is lowered to the gate level manually or by a logic synthesis tool, and progress is being made toward detailed verification of timing and the like. In that case, the designer can specify the configuration of whether to perform the simulation in the hard-veer description language or the simulation using the gate-level description resulting from the logic synthesis only by the designer describing in the source of the hard-veer description language. It was possible to specify. Also, even if the description is for the same circuit written in the hardware description language, the description of the highest functional design level and the switching of the description written at the detailed level must also be written in the configuration source. There wasn't.

[0003]

In the above-mentioned conventional technique, the configuration of the simulation model to be created in advance has to be described in the source. Therefore, there is a disadvantage that the source must be modified or added when the simulation is to be executed by another simulation model.

[0004]

A circuit simulation apparatus according to the present invention displays a design hierarchy, selects from a plurality of description methods for the same circuit, and outputs a configuration of the entire circuit, and a design hierarchy browser. Compile and link sources in the required order to create a logic simulator, and analyze the compilation results of each source to check the connection with the upper and lower layers and provide the information to the design hierarchy browser. It has a library manager that manages paths and times and versions of each source and its objects, a hardware description language compiler, and a linker that creates a logic simulator by linking the compilation results of the design target with the simulator kernel. .

[0005]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a circuit simulation apparatus of the present invention.

The circuit simulation device of this embodiment is
As shown in FIG. 1, the design data is design data to be simulated, which is composed of a source of hardware description language and gate level data. The location and generation time of each source and data of the design data 1 in the file system are registered in the library management unit 2, and the compiler 6 is applied to each source. The compilation result 7
Is sent to the library management unit 2, the hierarchical structure is analyzed by the library management unit 2, and the result is sent to the design hierarchy browser 3 to display the design hierarchy shown in FIG. The designer selects a simulation model to be simulated from a plurality of simulation models for the same circuit or changes the design hierarchy structure on the design hierarchy browser 3 while viewing the display. Then, the design hierarchy browser 3 outputs the configuration 5 of the entire circuit. The simulator creation unit 4 issues an instruction to be given to the compiler 6 and the linker 9 based on the design hierarchy information from the design hierarchy browser 3 and the information on the location of the design data from the library management unit 2. Based on the instruction, the configuration 5 output by the design hierarchy browser 3 is applied to the compiler 6 to obtain the compilation result 7 of the entire design including the configuration 5. The linker 9 links the compile result 7 with the simulator kernel 8 that is the core of the simulator to create the simulator 10.

Hardware description language VHDL (VHIS
C Hardware Description La
nguage). First, the terms used below will be described. The entity is the part that describes the interface of a block. The architecture is a part that describes the actual operation of a certain block, and a plurality of architectures can be defined for one entity, but the actual simulated architecture is one for each entity. A component is a part that describes an interface and is described mainly within the architecture when the architecture includes other blocks. What is a configuration?
It defines the simulation model by specifying which architecture a certain entity uses and which entity a certain component refers to.

In FIG. 2, the top-level description 11 is an enterprise TOP and its architecture is A. And S as the component that the architecture refers to
UB1, SUB2 and SUB3 are defined. In addition, block 1 (12), block 2 (13), block 3
(14) are the entities E1, E2, and E3, respectively, and their architectures are A for E1 and
A1 is defined for E2, A is defined for E3, and SUB1 and SUB2 are defined as components to be referenced in the architecture A1 of E2. Sub block 1 (15), sub block 2 (16)
Are entities E4 and E5, respectively, and their respective architectures are both defined by the name A. When the hierarchy is defined on the design hierarchy browser 3 as shown in FIG. 2, the output configuration 5 is as shown in FIG. When the architecture used in the block 3 (13) is to be changed from A1 to A2, the change may be made on the screen of the design hierarchy browser 3 as shown in FIG. Four new configurations are automatically generated based on the hierarchy definition thus changed. Then, this configuration is finally compiled and linked with the simulator kernel 8 to generate a simulation based on the changed layer definition.

[0010]

As described above, the circuit simulation apparatus of the present invention can select a simulation model while visually confirming the design hierarchical structure, and outputs the configuration to manually change the source. There is an effect that an error can be eliminated and the trouble of the change can be saved.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a circuit simulation device of the present invention.

FIG. 2 is a diagram showing an example of a design hierarchy display screen in the circuit simulation apparatus of this embodiment.

FIG. 3 is a diagram showing the confication of the design hierarchy display screen of FIG. 2 in the circuit simulation apparatus of this embodiment.

FIG. 4 is a diagram showing the confication of the design hierarchy display screen of FIG. 5 in the circuit simulation apparatus of this embodiment.

5 is a diagram showing an example of a design hierarchy display screen in which the hierarchy structure of the design hierarchy display screen represented by the design hierarchy display screen of FIG. 2 in the circuit simulation apparatus of this embodiment is changed.

[Explanation of symbols]

 1 design data 2 library management unit 3 design hierarchy browser 4 simulator creation unit 5 configuration 6 compiler 7 compilation result 8 simulator kernel 9 linker 10 simulator 11 top-level description 12, 13, 14 block 15, 16 sub-block

Claims (1)

[Claims] 1. In a circuit design having a plurality of simulation models, a design hierarchy browser that displays the hierarchy of the design, selects from a plurality of description methods for the same circuit, and outputs the configuration of the entire circuit,
Compile and link each source in the required order to create a logic simulator, and analyze the compilation result of each source to check the connection with the upper and lower layers and provide the information to the design hierarchy browser. In addition, a library management unit that manages paths and times and versions of each source and its objects, a hardware description language compiler, and a linker that creates a logic simulator by linking the compilation result of the design target with the simulator kernel. Circuit simulation device characterized by.