JPH0720061B2 - Semiconductor integrated circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor integrated circuit having a complementary MOS type structure, and more particularly to a semiconductor integrated circuit designed to reduce power consumption in an input circuit portion that receives a signal from the outside. .

TECHNICAL BACKGROUND OF THE INVENTION In general, a semiconductor integrated circuit having a complementary MOS type configuration (hereinafter referred to as CMOS) is characterized by its low power consumption, and has recently been particularly often used for such low power consumption. Is starting to appear. FIG. 4 shows the configuration of a conventional input circuit section of such a CMOS semiconductor integrated circuit. This input circuit section is an input circuit section for an external signal, particularly a chip enable signal () for determining whether this semiconductor integrated circuit is in an operating state or in a standby state. Signal ▲
A P-channel MOS transistor 11 is connected to the input terminal 10 of ▼.
And the gates of the N-channel MOS transistors 12 are connected. The drains of the two MOS transistors 11 and 12 are commonly connected, and the P-channel MOS transistor 1
The source of 1 is the power supply potential VC and the N-channel MOS transistor
The 12 sources are connected to the ground potential, respectively.
A CMOS inverter 13 that inverts the signal {circle around (1)} is formed by the transistors 11 and 12. Furthermore, this inverter 13
At the common drain connection point 14 of the MOS transistors 11 and 12 which are the output terminals of the P-channel MOS transistor 16 and the N-channel MOS transistor 16 which form the CMOS inverter 15 of the next stage.
The gates of the respective transistors 17 are connected. cm
As in the case of OS inverter 13, both MOS transistors 1 above
The drains of 6 and 17 are connected in common, the source of the P-channel MOS transistor 16 is connected to the power supply potential VC, and the source of the N-channel MOS transistor 17 is connected to the ground potential. The common drain connection point 1 of the MOS transistors 16 and 17, which are the output terminals of the inverter 15,
Thereafter, the signal of 8 is inverted by several stages of inverters and supplied to an internal control circuit (not shown). Note that all of the above MOS transistors are of the enhancement type and are used for P-channel and N-channel.
The back gate of the MOS transistor is connected to each source.

In the semiconductor integrated circuit having the input circuit section having such a configuration, the chip enable signal ▲ ▼ is set to the operating state by being set to "0" level, and is set to the standby state by being set to "1" level. In this standby state, the power consumption is reduced.

By the way, in a CMOS semiconductor integrated circuit, in order to achieve response characteristics to external signals and stable DC operation, more specifically, in order to enable high-speed operation and operation at a lower power supply voltage, an internal P channel is used. The threshold voltage of each MOS transistor and N-channel MOS transistor is -1V
And is set to about + 1V.

[Problems of Background Art] By the way, when a CMOS semiconductor integrated circuit composed of MOS transistors having a threshold voltage as described above is driven by an output signal of a TTL circuit or an N-channel MOS type circuit,
The "1" level of the signal input as ▲ ▼ is a voltage of about 2V to 3V. Therefore, such a signal ▲
When ▼ is input to the input terminal 10 of the circuit of FIG. 4, both the P-channel MOS transistor 11 and the N-channel MOS transistor 12 are turned on. As a result, a current flows between the power source VC and the ground in the inverter 13 of the input circuit unit even in the standby state, and power is consumed.

Therefore, in order to eliminate such power consumption, conventionally, as shown by a broken line in FIG. 4, a pull-up resistor is provided between the power source VC and the input terminal 10 outside the integrated circuit.
Inserting 19 is being done. That is, the input terminal
When a "1" level signal is input to 10, the "1" level voltage is raised to the power supply VC to turn off the P-channel MOS transistor 11 to eliminate power consumption in the input circuit section.

As described above, conventionally, it is necessary to connect the resistor 19 to the outside in order to completely eliminate the power consumption during the standby, and there is a disadvantage that the cost of the resistor 19 is high. It should be noted that it is conceivable to form the resistor 19 in the integrated circuit from the beginning in order to save the trouble of attaching the resistor 19 externally. However, connecting this resistor 19 causes a leak current at the input terminal. The value of the leak current at the input terminal is different for each user of the semiconductor integrated circuit. When terminals of a plurality of integrated circuits are commonly connected, the resistor 19 is connected in parallel between the common connection portion and the power source VC, and the leakage current of the leak current may vary depending on the number of integrated circuits used. The values will be different. Therefore, the value of the leak current cannot be determined to be a specific value, and it is impossible to form the resistor 19 in advance in the integrated circuit.

[Object of the Invention] The present invention has been made in consideration of the above circumstances, and an object thereof is a semiconductor integrated circuit capable of eliminating power consumption in an input circuit section without connecting a resistor to the outside. To provide.

SUMMARY OF THE INVENTION In the present invention, a power supply terminal and a reference voltage terminal, a signal input terminal, a P-channel MOS transistor having a gate connected to the input signal terminal, and a drain of the P-channel MOS transistor. A source connected to the reference voltage terminal and a gate connected to the input signal terminal to form a CMOS inverter together with the P-channel MOS transistor, a drain connected to the power supply terminal, and a gate connected to the reference voltage. To the terminal
The sources are connected to the sources of the P-channel MOS transistors, respectively, and the P-channel
Depletion for voltage drop in which the threshold voltage is set so that the voltage obtained by subtracting the absolute value of the threshold voltage of the MOS transistor becomes smaller than the lowest voltage on the high logic level side of the signal supplied to the signal input terminal. Type MOS transistor, the N channel MOS transistor and the P channel MOS transistor are connected in series by turning off the P channel MOS transistor when a high logic level side signal is supplied to the signal input terminal. There is provided a semiconductor integrated circuit configured to cut off a current path therethrough.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a configuration of an input circuit section of a semiconductor integrated circuit according to an embodiment of the present invention. The circuit of this embodiment has a new N-channel depletion type MO between the CMOS inverter 13 and the power supply VC of the conventional circuit shown in FIG.
The S-transistor 21 is inserted. The gate and back gate of the MOS transistor 21 (portion that becomes the channel region) are both connected to ground. The threshold voltage of the MOS transistor 21 is set to -3V, for example.

In such a configuration, the drain voltage of the MOS transistor 21, that is, the power supply voltage of the CMOS inverter 13 is MO
From the gate voltage V _G of the S transistor 21 to its threshold voltage V th21
The cuttings obtained by subtracting the value (V _G -Vth21) or more should not be. Here, V _G is 0 V because it is ground, and Vth21 is set to −3 V in advance, so the power supply voltage of the CMOS inverter 13 does not exceed 3 V. Therefore, even if the threshold voltage of the P-channel MOS transistor 11 in the CMOS inverter 13 is set to -1V, if the "1" level voltage of the signal ▲ ▼ is + 2V or more, the P-channel MOS transistor 11 is turned off. .
Therefore, no current flows in this CMOS inverter 13. That is, since the "1" level voltage of the chip enable signal ▲ ▼ may be +2 V or more, the semiconductor integrated circuit having this input circuit unit can be connected to the outside without connecting a resistor.
Even when driven by the output signal of the TTL circuit or the N-channel MOS type circuit, the power consumption in the input circuit section can be eliminated.

FIG. 2 is a circuit diagram showing a configuration of an input circuit portion of a semiconductor integrated circuit according to another embodiment of the present invention. In the circuit of this embodiment, instead of providing the depletion type MOS transistor 21, the enhancement type MOS with two P-channels connected in series between the CMOS inverter 13 and the power source VC.
The transistors 22 and 23 are inserted. The gates of both MOS transistors 22 and 23 are connected to their respective drains. Also, both MO
The threshold voltage of each of the S transistors 22 and 23 is set to -1V like other P channel MOS transistors.

In the circuit of this embodiment, when the power supply voltage VC is + 5V,
The power supply voltage of the CMOS inverter 13 is 5 V from this P channel MO
It does not exceed 3V, which is the sum of the threshold voltages of two S-transistors.

FIG. 3 is a circuit diagram showing a modification of the embodiment shown in FIG. Here, the back gate of the P-channel MOS transistor 11 in the inverter 13 is not connected to its source but is connected to the power supply VC. With such a connection, a sufficient back gate bias is applied to the P-channel MOS transistor 11, so that the threshold voltage can be made smaller than -1V by the back gate bias effect. As a result, it becomes possible to operate with a lower power supply voltage.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a semiconductor integrated circuit capable of eliminating power consumption in the input circuit section without connecting a resistor to the outside.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing the structure of an embodiment of the present invention, and FIG.
FIG. 4 is a circuit diagram showing the configuration of another embodiment of the present invention, FIG. 3 is a circuit diagram showing the configuration of a modification of the embodiment shown in FIG. 1, and FIG. 4 is a circuit diagram of a conventional circuit. 10 ... Input terminal, 11,16 ... P-channel MOS transistor, 12,17 ... P-channel MOS transistor, 13,15 ...
... CMOS inverter, 21 ... P-channel depletion type MOS transistor, 22,23 ... P-channel enhancement type MOS transistor.

Claims (1)

[Claims] 1. A semiconductor integrated circuit having a power supply terminal, a reference voltage terminal, and a signal input terminal, wherein a P-channel MOS whose gate is connected to the signal input terminal.
A transistor and a drain are connected to the drain of the P-channel MOS transistor, the source is connected to the reference voltage terminal, and the gate is connected to the signal input terminal, and an N-channel MOS forming a CMOS inverter together with the P-channel MOS transistor.
A transistor and a drain are connected to the power supply terminal, a gate is connected to the reference voltage terminal, and a source is connected to the source of the P-channel MOS transistor. The absolute value of the threshold voltage of the P-channel MOS transistor is subtracted from the voltage of the source. And a depletion-type MOS transistor for voltage drop, the threshold voltage of which is set so as to become smaller than the lowest voltage on the high logic level side of the signal supplied to the signal input terminal. The signal supplied to the terminal is for controlling whether the semiconductor integrated circuit is in an operating state or a standby state, and a high logic signal is applied to the signal input terminal in order to put the semiconductor integrated circuit in the standby state. By turning off the P-channel MOS transistor when a signal on the level side is supplied, the N-channel MOS transistor is turned on. The semiconductor integrated circuit characterized by being configured to interrupt the current path through the Njisuta and P-channel MOS transistor in series.