JPH07193503A - Successive comparison type a/d converter - Google Patents

Abstract

PURPOSE:To provide a successive comparison-type A/D converter with small power consumption. CONSTITUTION:The successive comparison-type A/D converter is provided with a control means 10 transmitting a first control signal and a second control signal by an A/D conversion termination signal transmitted when binarization is terminated to LSB on a binarized analog signal. A comparison means 12 to which the second control signal is supplied is provided with a prescribed potential connection means which forcedly connects the input-side of an amplifier to prescribed potential. A successive comparison register 11 to which the first control signal is supplied transmits a signal for forcedly setting the output signal of a D/A converter 2 to a minimum level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a successive approximation type A / D converter which reduces power consumption during a period in which an A / D (analog / digital) conversion operation is not performed.

[0002]

2. Description of the Related Art For example, in order to convert a certain voltage value of an analog signal changing within a range of 0-5V into a digital signal,
FIG. 6 shows a conventional configuration of a successive approximation A / D converter that converts an analog signal having a preset full scale into a digital signal. That is, the successive approximation A / D converter includes an R-2R ladder resistance circuit 2 that is connected to an output side of a later-described successive approximation register 1 and generates a predetermined voltage based on predetermined data supplied from the successive approximation register 1,
R-2 Connected to the output side of the ladder resistor circuit 2 R-2
A comparator 3 for comparing the predetermined voltage supplied from the R ladder type resistor circuit 2 with the voltage value of the supplied binarized analog signal, and a comparator connected to the output side of the comparator 3 and supplied from the comparator 3. The binarized analog signal is digitally converted by the data, and the successive approximation register 1 for producing the predetermined data to be used in the successive approximation register, and the binarized analog connected to the output side of the successive approximation register 1 When the digital conversion is completed for all the bits of the signal, this digital data is supplied from the successive approximation register 1 to the N-bit latch 4, the above-described successive approximation register 1, the R-2R ladder type resistor circuit 2, the comparator 3, The control register 5 controls the operation of the N-bit latch 4.

The R-2R ladder resistance circuit 2 is shown in FIG.
It has the configuration shown in. In FIG. 7, “VRT” indicates the maximum value of the full scale and “VRB” indicates the minimum value of the full scale. The data latch 2a latches the data (D0 to DN) supplied from the successive approximation register 1. The R-2R ladder resistance circuit 2 is configured to switch the switches S0 to SN based on the data (D0 to DN).
Each of them is connected to either VRT or VRB to generate a predetermined voltage from the output terminal (DAOUT).

[0004]

The successive approximation A / D converter having the above-described structure operates as follows. First, according to the predetermined data sent from the successive approximation register 1 to the R-2 ladder resistor circuit 2 under the control of the control register 5, the voltage value of 1/2 of the full scale is output from the R-2R ladder resistor circuit 2. Converter 3
Then, the converter 3 compares the binarized analog signal with the applied voltage value and sends the comparison result to the successive approximation register 1. Next, according to the predetermined data sent from the successive approximation register 1 to the R-2R ladder resistance circuit 2 under the control of the control register 5, the voltage value that is 3/4 of the full scale is output from the R-2R ladder resistance circuit 2. Applied to the comparator 3, the comparator 3 compares the binarized analog signal with the 3/4 voltage value and sends the result to the successive approximation register 1. In this manner, the successive approximation A / D converter converts the binarized analog signal from the MSB (most significant bit) side to the LSB (least significant bit) side into a digital signal having a predetermined number of bits. At the time when the conversion to the digital signal is completed, the successive approximation register 1 sends the digital data to the N-bit latch 4 and at the same time EO indicating the end of the digital conversion.
The CB signal is sent to the control register 5.

As described above, conventionally, at the end of the A / D conversion operation, the R-2R latch type resistance circuit 2 outputs the LSB.
The state in which the predetermined voltage necessary for determining is still applied to the comparator 3 is maintained. Therefore, also in the comparator 3, a voltage that is neither a low (L) level nor a high (H) level is applied to the input side, so that a current flows in the circuit. Therefore, when the standby time is long until the next A / D conversion operation, there is a problem that the conventional successive approximation A / D converter consumes a large amount of power. The present invention has been made to solve such problems, and an object thereof is to provide a successive approximation A / D converter with low power consumption.

[0006]

The present invention provides a D / A converter having an R-2R type ladder resistance means, and a binarized analog signal connected to the output side of the D / A converter and supplied from the outside. And a comparison means for comparing the output signal of the D / A converter, and an output signal of the D / A converter connected to the output side of the comparison means to control the output signal of the D / A converter and the MSB side to the LSB side by the output signal of the comparison means. To a successive approximation register that sequentially determines the digital conversion value of the binarized analog signal
In the D converter, the first control signal is sent to the successive approximation register by the A / D conversion end signal sent at the time when the A / D conversion is completed up to the LSB of the binarized analog signal, and the comparison is performed. The comparison means is provided with control means for sending a second control signal to the means, and the comparison means forcibly sets the input side of the amplifier forming the comparison means to the ground potential or the power supply potential by the supply of the second control signal. The successive approximation register is supplied with the first control signal to supply a signal for forcibly setting the output signal of the D / A converter to the lowest level. Characterized by sending to a converter

[0007]

With this configuration, the constant potential connection means provided in the comparison means forcibly forces the input side of the amplifier forming the comparison means to the ground potential or the second control signal supplied from the control means. It is set to the power supply potential and acts to prevent the current from being sent from the comparison means. Further, the successive approximation register sends a signal for forcibly setting the output signal of the D / A converter to the minimum level to the D / A converter when the first control signal is supplied from the control means. Therefore, the successive approximation register acts so as to prevent the current from being sent from the D / A converter.

The D / A converter is the R in the embodiment.
-2R ladder resistance circuit, comparison means corresponds to the comparator described in the embodiment, control means corresponds to the control register in the embodiment, and constant potential connection means corresponds to the N-channel MOS transistor in the embodiment. Equivalent to.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the successive approximation A / D converter of the present invention will be described below with reference to the drawings. FIG. 1 shows the structure of the successive approximation A / D converter in this embodiment. However, the outline of the successive approximation A / D converter in this embodiment is different from that of the successive approximation A / D converter shown in FIG. Absent. Therefore, in the successive approximation A / D converter of the present embodiment shown in FIG. 1, the same components as those of the successive approximation A / D converter shown in FIG. 6 are designated by the same reference numerals and the description thereof will be omitted. In the successive approximation converter of this embodiment, the control register 1 is different from the conventional successive approximation A / D converter shown in FIG.
0, the successive approximation register 11 and the comparator 12 are different. These will be described below.

The control register 10 is, for example, a successive approximation register 11 when the binarization of all the bits up to the LSB of the binarized analog signal is completed.
Based on the A / D conversion end signal (EOCB) sent from the above, the operation of sending the first control signal to the successive approximation register and sending the second control signal to the comparator 12 is performed.

The successive approximation register 11 is supplied with the first control signal from the control register 10,
Data latch 2a provided in the R-2R ladder resistance circuit 2
The data with all the bits being 0 is transmitted to.

The comparator 12 has, for example, the configuration shown in FIG. That is, the comparator 12 is connected to the input terminal AIN to which the binarized analog signal is supplied, the input terminal DA to which the output voltage of the R-2R ladder resistance circuit 2 is supplied, and the clock signal connected to the input terminal AIN. A transmission gate 20 whose operation is controlled by φ1, a transmission gate 21 which is connected to the input terminal DA and whose operation is controlled by a clock signal φ2, and one terminal on the output side of the transmission gates 20 and 21 connected to each other are provided. A connected capacitor 22, an inverter 23 having the other terminal of the capacitor 22 connected to the input side, and an inverter 23
To the transmission gate 24, which is connected in parallel to the input terminal of the inverter 25 and whose output terminal is connected to the output side of the inverter 23; An inverter 26 serving as an output terminal of the comparator 12, a transmission gate 27 connected in parallel to the inverter 26 and operation-controlled by a clock signal φ1, and an inverter 23.
-Channel MOS having a drain connected to the input side of the source, a source grounded, and the second control signal supplied to the gate
A transistor 28 (hereinafter referred to as NMOS) and an NMOS transistor 29 having a drain connected to the input side of the inverter 26, a source grounded, and the gate supplied with the second control signal are provided.

The comparator 12 may have the configuration shown in FIG. 3 or 4. In FIGS. 3 and 4, the same components as those shown in FIG. 2 are designated by the same reference numerals. The comparator 32 shown in FIG. 3 includes NMOS transistors 28 and 29 that form the comparator 12.
Instead of P-channel MOS (hereinafter referred to as PMOS)
It is composed of transistors. That is, a PMOS whose drain is connected to the input side of the inverter 23, whose source is connected to the power source, and whose second control signal is supplied to its gate
A transistor 33 and a PMOS transistor 34, which has a drain connected to the input side of the inverter 26, a source connected to a power supply, and a gate to which the second control signal is supplied, are provided.

The comparator 42 shown in FIG. 4 is formed by a transmission gate in place of the NMOS transistors 28 and 29 forming the comparator 12. The transmission gate is composed of CMOS. That is, one terminal is connected to the input side of the inverter 23, the other terminal is grounded and the operation is controlled by the second control signal, and one terminal is connected to the input side of the inverter 26 and the other terminal is connected. And a transmission gate 44 whose terminal is grounded and whose operation is controlled by the second control signal.

The operation of the successive approximation A / D converter of the present embodiment having the above-mentioned structure will be described below. The CST (start conversion) signal shown in FIG.
And the successive approximation A / D converter is set. Next, a CLK (clock) signal is supplied to the control register 10 to start A / D conversion. First, the binarized analog signal is sampled and held by the comparator 12. Next, as described above, the successive approximation register 11 receives the R-2 signal by the control signal sent from the control register 10 to the successive approximation register 11.
The data supplied to the data latch 2a of the R ladder type resistance circuit 2 is sequentially changed. Therefore, the successive approximation voltage is supplied from the R-2R ladder resistance circuit 2 to the comparator 12, the comparator 12 compares the comparison voltage with the binarized analog signal, and the successive approximation register 11 outputs the MS.
The binarized data is sequentially determined from B to LSB.
And when the comparison is completed for all bits,
The successive approximation register 11 sends the digital conversion data to the N-bit latch 4, and the A / D conversion operation ends.

When the A / D conversion operation is completed, the successive approximation register 11 has the control register 10
An A / D conversion end (EOC) signal is sent to the control register 10, and in response to this, the control register 10 sends the first control signal to the successive approximation register 11 and sends the second control signal to the comparator 1.
Send to 2. When the first control signal is supplied, the successive approximation register 11 sends out data in which all bits are 0 to the data latch 2a included in the R-2R ladder resistance circuit 2. Therefore, the R-2R ladder resistance circuit 2 is
Connect all of the switches S0 to SN to the VRB side. Therefore, the current in the R-2R ladder resistance circuit 2 becomes zero.

On the other hand, when the second control signal is supplied, the comparator 12 becomes the NMOS transistor 2 shown in FIG.
8, 29 are turned on, the input sides of the inverters 23, 26 are fixed to the L level, and the discharge of the capacitors 22, 25 disappears, so that no current flows in the inverters 23, 26. In the comparator 32 shown in FIG. 3, the input sides of the inverters 23 and 26 are fixed to the H level and the capacitors 22 and 25 are not discharged, so that no current flows through the inverters 23 and 26. In addition, in the comparator 42 shown in FIG.
Since the input side of is fixed at the L level, no current flows through the inverters 23 and 26 as in the case of FIG.

Thus, at the end of A / D conversion, R
-2R ladder resistance circuit 2 and, for example, the current output from the comparator 12 shown in FIG. 2 disappears, and this state is maintained until the next A / D conversion operation is started. It is possible to reduce current consumption other than during the A / D conversion operation.

Although the A / D conversion end signal is sent to the control register 10 by the successive approximation register 11 in the above embodiment, it may be supplied to the control register 10 from the outside of the successive approximation A / D converter. Good.
With this configuration, it is possible to arbitrarily prevent the consumption current from being sent out and reduce the current when the battery or the like is over-discharged.

Further, by using the comparator 42 shown in FIG. 4, the impedance in the switch of the transmission gate can be made flat and lower than the comparator shown in FIG. Can be done quickly.

[0021]

As described above in detail, according to the present invention, the constant potential connecting means provided in the comparing means forces the input side of the amplifier constituting the comparing means by the second control signal supplied from the controlling means. Since the potential is set to the ground potential or the power supply potential, it is possible to prevent the comparison unit from sending out a current after the A / D conversion. Further, the successive approximation register receives D / when the first control signal is supplied from the control means.
Since the signal for forcibly setting the output signal of the A converter to the minimum level is sent to the D / A converter,
It is possible to prevent the current from being sent from the D / A converter after the A / D conversion.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a successive approximation A / D converter of the present invention.

FIG. 2 is a circuit diagram showing a configuration example of the converter shown in FIG.

FIG. 3 is a circuit diagram showing another configuration example of the converter shown in FIG.

FIG. 4 is a circuit diagram showing another configuration example of the converter shown in FIG.

5 is a timing chart for explaining the operation of the successive approximation A / D converter shown in FIG.

FIG. 6 is a block diagram showing a configuration of a conventional successive approximation type A / D converter.

FIG. 7 is a diagram showing a configuration of an R-2R ladder resistance circuit.

[Explanation of symbols]

2 ... R-2R ladder type resistance circuit, 4 ... N bit latch,
10 ... Control register, 11 ... Successive approximation register, 12 ... Comparator, 23, 26 ... Inverter, 2
8, 29 ... NMOS, 33, 34 ... PMOS, 43, 4
4 ... Transmission gate.

Claims (6)

[Claims] 1. A D / having R-2R type ladder resistance means.
A / D converter, a binarized analog signal connected to the output side of the D / A converter and supplied from the outside, and the D / A
The comparing means for comparing the output signal of the A converter with the comparing means is connected to the output side of the comparing means to control the output signal of the D / A converter, and the output signal of the comparing means controls the MSB side to the LSB side sequentially. A successive approximation A / D converter including a successive approximation register that determines a digital conversion value of a binarized analog signal, wherein A / D conversion is completed up to LSB for the binarized analog signal. A control means for sending a first control signal to the successive approximation register and a second control signal to the comparison means by an A / D conversion end signal sent at a time point, the comparison means comprising the second control The successive approximation register is provided with a constant potential connection means for forcibly setting the input side of the amplifier constituting the comparison means to the ground potential or the power supply potential by the supply of the signal. Is a successive approximation type, wherein a signal for forcibly setting the output signal of the D / A converter to the minimum level is sent to the D / A converter by being supplied with the first control signal. A / D converter. 2. The successive approximation A / D converter according to claim 1, wherein the A / D conversion end signal is sent from the successive approximation register. 3. The successive approximation A / D converter according to claim 1, wherein the A / D conversion end signal is supplied from the outside. 4. The constant potential connecting means is an N-channel type field effect transistor in which the A / D conversion end signal is supplied to the gate and the source electrode is connected to the ground level. A successive approximation type A / D converter described in 1. 5. The constant potential connecting means is a P-channel field effect transistor in which the A / D conversion end signal is supplied to the gate and the source electrode is connected to the power supply potential. Successive approximation type A described in Crab
/ D converter. 6. The sequential gate according to claim 1, wherein the constant potential connecting means is a transmission gate which is on / off controlled by the A / D conversion end signal and has one terminal connected to a ground level. Comparison type A / D converter.