JPH07192468A - Output circuit and semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an output circuit capable of effectively preventing the generation of a ringing without increasing the access time. CONSTITUTION:A driving transistor 2a conducts when the potential of a node N2 becomes an H level to discharge an output node 6 to a ground potential level. A driving transistor 2b discharges the output node 6 to the ground potential level at a high speed when the transistor 6 becomes on-state. The driving transistor 2b becomes on-state for a prescribes period at the time of completing the outputting of high level data to discharge the output node 6 to the ground potential level for a constant period. Thus, the potential of the output node 6 is lowered from a high level to an intermediate level to make the amplitude of a next output signal small.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit, and more particularly to improvement of a data output circuit used in a semiconductor memory device.

[0002]

2. Description of the Related Art FIG. 86 is a block diagram schematically showing an overall structure of a general dynamic semiconductor memory device. Referring to FIG. 86, the dynamic semiconductor memory device includes a memory cell array 900 in which dynamic memory cells MC are arranged in a matrix of rows and columns.
In memory cell array 900, word line WL is arranged corresponding to each row of memory cells. Memory cell MC
Bit line pairs BL and ZBL are arranged corresponding to the respective columns. Memory cell MC is arranged corresponding to an intersection of one word line WL and a pair of bit lines BL and ZBL. In FIG. 86, one word line WL and a pair of bit lines BL and ZBL are representatively shown. Bit line B
Data complementary to each other appear on L and the complementary bit line ZBL.

The dynamic semiconductor memory device further includes
An address buffer 902 which generates an internal row address signal RA and an internal column address signal CA in accordance with an externally applied address signal Ad, and an internal row address signal RA from the address buffer 902 are decoded,
A row decoder 904 for selecting a corresponding word line in memory cell array 900 and a column for decoding an internal column address signal CA from address buffer 902 to generate a signal for selecting a corresponding column (bit line pair) in memory cell array 900. A decoder 906 is included.

Address buffer 902 is activated in response to internal row address strobe signal ZRAS, and latches a given address signal Ad to generate internal row address signal RA, and internal column address strobe signal ZCAS. Column latch 907 for latching address signal Ad applied in response to and generating internal column address signal CA.

Row address signals and column address signals are time-division multiplexed and applied to address buffer 902. The internal row address strobe signal ZRAS is
RA receiving external row address strobe signal / RAS
It is generated from the S buffer 910. Internal column address strobe signal ZCAS is activated in response to activation of internal row address strobe signal ZRAS, and is generated from CAS buffer 912 taking in external column address strobe signal / CAS.

The dynamic semiconductor memory device further includes
In response to a column selection signal from a column decoder 906 and a sense amplifier 914 that detects and amplifies data of a memory cell connected to a word line selected in the memory cell array 900, a corresponding column (bit line in the memory cell array 900 is Pair) to the internal data bus 915 I
Includes O-gate 916. The sense amplifier 914 responds to the internal row address strobe signal ZRAS at a predetermined timing with a sense amplifier activation signal (not explicitly shown).
The operation is controlled by a clock control circuit 918 that generates The clock control circuit 918 also controls activation / deactivation of the row decoder 904.

The semiconductor memory device further includes a column latch 9
07, an ATD circuit 920 that detects a change in the internal column address signal CA from the signal 07 and generates an address change detection signal φATD at the time of detection, an internal column address strobe signal ZCAS from the CAS buffer 912, and an external write / read instruction. Signal (write enable signal) / WE and an input / output control circuit 922 which generates a timing control signal for determining data input / output according to the address transition detection signal φATD, and a data write instruction signal from the input / output control circuit 922 (clearly (Not shown), the input circuit 924 transmitting the internal write data to the internal data bus 915 according to the external data D, and the internal read data appearing on the internal data bus 915 according to the data output enable signal from the input / output control circuit 922. It includes an output circuit 926 for generating and outputting the external read data Q. Mu.

Write enable signal / WE designates a data write when it is "L" and a data read operation when it is "H". Next, the operation will be briefly described.

External row address strobe signal / RAS
Becomes "L", and when the internal row address strobe signal ZRAS from the RAS buffer 910 becomes "L" accordingly, the memory cycle starts. In response to "L" of internal row address strobe signal ZRAS, row latch 905 included in address buffer 902 latches address signal Ad to generate internal address signal RA and applies it to row decoder 904. Clock control circuit 918
Applies an activation signal to row decoder 904 in accordance with internal row address strobe signal ZRAS. Row decoder 904 decodes internal row address signal RA and selects a corresponding word line in memory cell array 900. As a result, the data of the memory cell connected to the selected word line is transferred to the corresponding bit line BL (or Z
BL). Then, the clock control circuit 918
The memory array 914 is activated in accordance with a sense amplifier activation signal (not explicitly shown) from the bit line pair BL
And differentially amplify the potential appearing on ZBL.

On the other hand, the external column address strobe signal / CAS becomes "L" after the falling of the external row address strobe signal / RAS, and the C is enabled by the internal row address strobe signal ZRAS of "L".
The AS buffer 912 generates an "L" internal column address strobe signal ZCAS. In response to this internal column address strobe signal ZCAS, column latch 907 latches the applied address signal Ad and generates internal column address signal CA. The column decoder 906 decodes this internal column address signal CA, and the column (bit line pair) in the memory cell array 900 is decoded.
Generate a signal to select. After the sense amplifier 914 senses and amplifies the data of the memory cell in each bit line pair, the IO gate 916 causes the column decoder 906 to
Conducting in response to the column select signal from, the corresponding bit line pair is connected to internal data bus 915. Then input circuit 9
Data is written or read via 24 or output circuit 926.

FIG. 87 is a diagram showing a structure of a 1-bit data output portion in the output circuit 926. In the case where the semiconductor memory device shown in FIG. 86 is configured to input / output multi-bit data such as 4-bit or 8-bit, the structure shown in FIG.
The input / output circuit shown in is provided according to the number of bits of a plurality of data.

Referring to FIG. 87, output circuit 926 includes an inverter 5 for inverting data ZDD appearing on internal data bus line 915b, a 2-input AND circuit 3 for receiving output enable signal OEM and the output of inverter 5. And 2 input A for receiving output enable signal OEM and internal read data ZDD
ND circuit 4, first output drive transistor 1 that drives output node 6 to power supply potential Vcc level in response to the output of AND circuit 3, and output node 6 that is ground potential GND in response to the output of AND circuit 4. It includes a second drive transistor 2 that discharges to a level. Drive transistors 1 and 2
Are both n-channel MOS transistors. Output enable signal OEM is output from input / output control circuit 922 shown in FIG. 86 to internal column address strobe signal ZCA.
It is generated in accordance with S and the address transition detection signal φATD. The operation of the output circuit shown in FIG. 87 will now be described with reference to the operation waveform diagram of FIG.

Internal column address strobe signal ZCA
When S goes to "L", after a predetermined period of time, a signal having the logic inverted from the data of the selected memory cell is transmitted onto internal data bus line 915b. Internal data bus line 915b is precharged to an intermediate potential during standby. FIG. 88 shows a state in which an "L" data signal appears on internal data bus line 915b.

AND while the output enable signal OEM is "L"
The outputs of circuits 3 and 4 are both "L", and drive transistors 1 and 2 are both off. In this state, the output node 6 maintains the high impedance state (Hi-Z).

When the output permission signal OEM becomes "H", A
The ND circuits 3 and 4 are enabled. The data signal ZDD on the internal data bus line 915b is "H", and the output of the inverter 5 is "L". Therefore,
According to the output enable signal OEM of "H", the output of the AND circuit 4, that is, the potential of the node N2 becomes "H", and the second
Drive transistor 2 is turned on. The output node 6 is discharged to the ground potential level GND level through the second drive transistor 2, and the output data Q of "L" is output.

When data signal ZDD is "L", in response to the rise of output enable signal OEM, the output of AND circuit 3, that is, the potential of node N1 becomes "H", and first drive transistor 1 is turned on. Becomes As a result, output node 6 is charged to a voltage level lower than power supply potential Vcc level by the threshold voltage of transistor 1, and output data Q attains "H".

[0017]

Drive transistors 1 and 2 have a current driving capability of, for example, several mA in order to charge / discharge an external load at high speed and output data at high speed.
Has been made larger. The semiconductor memory device is enclosed in a package. In this case, as shown in FIG. 89, the output node 6 is connected to a frame lead forming an output terminal via a bonding wire. In FIG. 89, this bonding wire and frame lead are shown as an output terminal 930. Such a bonding wire and a frame lead have not only a parasitic capacitance C but also a parasitic inductance L. When a current change occurs in the parasitic inductance L, a voltage expressed by the following equation is generated.

V = -Ldi / dt where di / dt is the time derivative of the current i flowing through the inductance L.

When both drive transistors 1 and 2 are off, output node 6 is in a high impedance state. In this high impedance state, the potential level of the previous output data Q is held. Therefore, when the data Q of "L" is output after the output data Q of "H" is output, FIG.
As shown in, the output node 6 is discharged through the drive transistor 2 having a large current driving capability,
Ringing occurs at this output node 6.

When the "Q" data Q is output after the "L" output data Q is output, the output node 6
Is charged via the drive transistor 1 having a large current driving capability. Also in this case, FIG. 90 (A)
As shown in (1), a large current change occurs in the parasitic inductance L, resulting in overshoot.

Further, unlike the structure in which the output node 6 is maintained in the high impedance state, even when the output node 6 is held at the intermediate potential, the output node which has been precharged to the intermediate potential is charged and discharged according to the logic of the data to be output. At this time, since this charge / discharge is performed through drive transistor 1 having a large current driving capability, ringing similarly occurs at the output node.

When the ringing such as the overshoot or the undershoot occurs, the data cannot be read until the output data becomes stable, and the access time becomes long. When the amplitude at the time of occurrence of this undershoot is large, a large voltage is applied between the gate and drain of the output drive transistor 1 (node terminal connected to the output node 6), and the withstand voltage characteristic of the transistor 1 is reduced. The problem of deterioration arises. This also applies to the drive transistor 2.

In order to prevent the occurrence of ringing as described above, it is possible to drive the output node in two steps as shown in FIG. Here, FIG. 91 shows a structure of a portion for discharging the output node in two steps.

In FIG. 91, the output circuit includes drive transistors 2a and 2b provided in parallel between output node 6 and the ground potential node. Drive transistors 2a and 2b are formed of n-channel MOS transistors. The current drivability of drive transistor 2a is made smaller than the current drivability of drive transistor 2b. This is achieved by adjusting the channel length or channel width of the transistor. The output of AND circuit 4 receiving output enable signal OEM and internal read data signal ZDD is applied to the gate of drive transistor 2a. In order to control on / off of drive transistor 2b, a delay stage 7 delaying the potential on node N2 for a predetermined time, and an AND circuit 8 receiving the output of delay stage 7 and the signal potential on node N2 are provided. The output of AND circuit 8 is applied to the gate of drive transistor 2b. The delay stage 7 includes an even number of inverters (4 inverters in FIG. 91),
The given signal is delayed for a predetermined time. Next, in FIG.
The operation of the output circuit shown in FIG. 9 will be described with reference to the operation waveform diagram of FIG.

Internal column address strobe signal ZCA
When S attains an active state of "L", the column selecting operation is started and the data of the selected memory cell is transmitted onto internal data bus line 915b. Output enable signal OEM is "H"
Then, the potential of the node N2 becomes "H", the drive transistor 2a is turned on, and the output node 6 is gently discharged. At this time, the output of the delay stage 7 is still at low level, the potential of the node N3 is "L", and the drive transistor 2b is in the off state.

When the output of the delay stage 7 becomes "H" after a lapse of a predetermined time, the output of the AND circuit 8 becomes "H" and the drive transistor 2b is turned on. As a result, output node 6 is discharged at high speed. When the drive transistor 2b is turned on, the potential of the output node 6 is sufficiently lowered, so that ringing hardly occurs even if the output node 6 is discharged at high speed.
This is because the maximum amplitude when the damped oscillation occurs in the RLC circuit is proportional to the voltage value when the rapid discharge is performed.

In the dynamic semiconductor memory device, an operation mode called static column mode is known. This static column mode is shown in FIG.
As shown in the operation waveform diagram, it is an operation mode in which data is randomly input / output by inputting only an address signal to one row of memory cells designated by a row address signal X.

That is, as shown in FIG. 93, the row address strobe signal ZRAS is first lowered to "L", the row address signal is taken in, and the word line is selected. The data of the memory cell connected to the selected word line is detected and amplified by the sense amplifier and latched. At this time, if the column address signal Y is asynchronously input and held for a predetermined time, the data of the corresponding column address is output. In the static column mode, column address strobe signal ZCAS has an output enable function without a column address latch instruction function and is held at "L". In the static column mode, it is not necessary to toggle the column address strobe signal / CAS to fetch the column address signal, and data can be output at high speed.

However, in such a static column mode, as shown in FIG.
EM is held in the "H" state. Therefore, one of drive transistors 1 and 2a is turned on, and output node 6 is held at "H" or "L". Therefore, in this static column mode operation, when "L" data is output after "H" data is output, the potential amplitude of output node 6 becomes large and the delay time provided by delay stage 7 is short. The problem that ringing occurs occurs. If the delay time of the delay stage 7 is lengthened in order to prevent the occurrence of such ringing, the access time becomes longer and the characteristic of the static column mode of high speed access is lost.

The delay stage is composed of an inverter. As such an inverter, a normal CMO
S inverters are often used. The driving force of the MOS transistor is determined by its gate voltage. That is, if the operating power supply voltage of the inverter formed by this delay stage increases, the operating speed of the inverter increases,
The delay time of the delay stage is shortened. Further, the higher the operating temperature, the slower the operating speed of the MOS transistor (due to the increase in threshold voltage and the increase in channel resistance due to generation of heat carriers). Therefore, the higher the operating temperature, the slower the operating speed of the inverter forming the delay stage, and the longer the delay time of the delay stage. If the delay time of the delay stage is different, the on-timing of the drive transistor 2b shown in FIG. 91 is different. In this case, if the delay time is short, drive transistor 2b is turned on when the potential of the output node is not sufficiently lowered, and output node 6 is discharged at high speed, so ringing occurs. At this time, when the power supply voltage is high or when the temperature is low, the driving force of the output drive transistor also increases. Therefore, there is a problem that ringing is more likely to occur.

Therefore, an object of the present invention is to provide an output circuit capable of stably outputting a signal at high speed without causing ringing.

Another object of the present invention is to provide an output circuit in a semiconductor memory device capable of stably outputting a data signal without increasing access time.

[0033]

According to a first aspect of the present invention, there is provided an output circuit according to a signal appearing at an input node at the time of activation of an output enable signal. A drive element that drives to one of the potential levels and a control unit that drives the output node to a potential level intermediate between the first and second potential levels in response to the inactivation of the output permission signal. Prepare

According to another aspect of the output circuit, the drive element means for driving the output node to the potential corresponding to the logic of the input signal in response to the activation of the output enable signal, and the inactivation of the output enable signal. Discriminating means for discriminating the logic of the signal appearing at the output node in response to the transition of the output node, and discriminating the output node by the discriminating means in response to the discrimination result output of this discriminating means and the signal invalidating instruction signal of the output node And a control means for driving the potential to a potential corresponding to a logic different from the generated logic for a predetermined period.

According to another aspect of the output circuit, a drive element for driving the output node to a potential level corresponding to the logic of the input signal according to the input signal, and a potential at which the signal potential of the output node corresponds to the logic of the input signal. And a control means for increasing the driving force of the drive element.

According to another aspect of the output circuit, the first drive element drives the output node to the potential level corresponding to the logic of the input signal at the first speed according to the input signal, and the delay means for delaying the input signal. A second drive element for driving the output node to a potential level corresponding to the logic of the input signal at a second speed higher than the first speed in response to the output of the delay means; Adjusting means for adjusting the length of the delay time given to the signal according to at least one of the operating power supply voltage and the operating temperature.

According to another aspect of the present invention, there is provided an output circuit, which is responsive to an output enable signal and an input signal, for transmitting a signal having a potential corresponding to the logic of the input signal to the first node, and the gate means. Responsive to the output, a first drive element for driving the output node to a potential corresponding to the logic of the input signal at a first speed; a delay means for delaying the output of the gate means; A second drive element for driving the output node to the potential level corresponding to the logic of the input signal at the second speed higher than the first speed, and indicating that the output enable signal and the input signal should be output. Adjusting means for adjusting the delay time according to the output instruction signal.

According to a sixth aspect of the present invention, an output circuit responds to an internal signal by transmitting a voltage supplied to a reference power supply node for supplying a logic voltage of a signal to be output to an output node, and an output transistor. A first current supply element having a first current driving capability for coupling a voltage supply source of a corresponding logic and a reference power supply node in response to an output enable signal which gives a signal output timing to the node; After activation of the first current supply element in response to the signal, a second current connecting the voltage supply source and the reference power supply node and having a second current drive capacity larger than the first current drive capacity. And a supply element.

An output circuit according to a seventh aspect includes a drive transistor driving an output node to a voltage level on a power supply node in response to an internal signal, and a variable delay means, and in response to the internal signal, the variable delay means. And a delay adjusting means for adjusting the delay time of the variable delay means in accordance with the output instruction signal indicating that the internal signal should be output and the internal signal. A first current drive element having a first current drive capability, which is activated when the output signal of the gate means is activated and connects the reference voltage source and the reference power supply node; and the first current drive element of the first current drive element. A second current drive element that is activated after activation and that connects the reference voltage source and the reference power supply node and that has a larger current driving force than the first current drive element; Obtain.

An output circuit according to an eighth aspect is the output circuit according to the sixth or seventh aspect, wherein the reference voltage supply source is a first reference voltage source for applying a first logic voltage to the second current drive element. , Second than the voltage on this first reference voltage source
A second supply source for providing the first current drive element with a voltage close to the logic voltage of 1.

An output circuit according to a ninth aspect of the present invention is a plurality of insulated gate field effect transistors each having a different threshold voltage and a substrate region bias voltage and provided in parallel between an output node and a reference power supply node. In response to the internal signal, a plurality of insulated gate field effect transistors are connected to each other such that the insulated gate field effect transistors having a larger absolute value of the threshold voltage or the larger absolute value of the substrate region bias voltage are sequentially turned on. And an activation unit that is turned on at different timings.

According to a tenth aspect of the present invention, in an output circuit, a resistance element coupled to an output node, a drive transistor connected between the resistance element and a voltage source and rendered conductive in response to an internal signal, and the conduction of the drive transistor. A switching element for short-circuiting the resistance element is provided after a predetermined time has elapsed.

An output circuit according to an eleventh aspect of the invention is connected in parallel between an output node and a voltage supply node, and has a plurality of resistance elements having different resistance values, each of the plurality of resistance elements and a voltage supply node. And a plurality of drive transistors connected between the two, and an activation control unit that sequentially turns on the drive transistors connected to the resistance element having a large resistance value in response to an internal signal.

According to a twelfth aspect of the present invention, the output circuit has a reference voltage generating means for generating a constant reference voltage independent of the external power supply voltage and the temperature, and a positive temperature coefficient according to the reference voltage and the external power supply voltage, and a negative temperature coefficient. Internal voltage generating means for generating an internal voltage having an external power supply voltage dependency, and output means for driving an output node to the voltage level of the internal voltage in response to the internal signal.

According to a thirteenth aspect of the present invention, the output circuit responds to the internal signal on the internal node by driving the output node to the voltage level on the first power supply node, and a clock for giving the output timing of the internal signal. Comparing means activated in response to the signal and comparing the voltage on the first power supply node with the reference voltage; and a second power supply node to the first power supply node in response to the output signal of the comparing means. And a transistor element that supplies a current.

According to a fourteenth aspect of the present invention, a semiconductor device provides a bus amplifier for amplifying an internal signal on an internal bus having a plurality of bit widths in a parallel manner, and a logic signal corresponding to each of the plurality of signals amplified by the bus amplifier. A plurality of output nodes for outputting to the outside, and a plurality of output circuits provided corresponding to each of the plurality of output nodes and buffering corresponding signals from the bus amplifier and transmitting the buffered signals to the corresponding output nodes. . The time constant that determines the changing speed of the output signal of each of the plurality of output circuits is shortened as the distance between the corresponding output node and the bus amplifier increases.

An output circuit according to claim 15 is coupled between the output node and the reference voltage node, and drives the output node to a voltage level on the reference voltage node with a first current driving force in response to an internal signal. Connected between the first drive element and the output node and the reference voltage node, and arranged closer to the output pad than the first drive element. A second drive element is provided which is turned on at a late timing and drives the output node to a voltage level on the reference voltage node with a second current driving force larger than the first current driving force.

An output circuit according to claim 16 is coupled between the output node and the reference voltage node, and outputs the output node and the pad at a voltage level on the reference voltage node with a first current driving force in response to an internal signal. Is connected between the output node and the reference voltage node, has a current driving force larger than that of the first drive element, and conducts at a timing later than that of the first drive element. Second drive element for driving the output node and the output pad to a voltage level on the reference voltage node, and noise absorption provided between the first drive element and the output pad for absorbing a noise voltage appearing on the output pad And means.

[0049]

In the output circuit according to the first aspect, the output node is driven to the intermediate potential level when the output permission signal is inactivated, and the output node is driven from the intermediate potential level to the potential when the next output signal is output. Changes. Therefore, the potential amplitude of the output node can be reduced, and ringing can be effectively prevented. Further, since the potential of the output node changes from the intermediate potential to the potential of “H” or “L”, the timing of determining the output signal becomes faster,
The output signal can be output at high speed.

In the output circuit according to the second aspect, when the output signal is invalidated, that is, when a new output signal is to be output next, the potential corresponding to the first logic of the output node becomes the second potential. It is driven to a potential level corresponding to the logic for a predetermined period. Therefore, even when the "L"("H") signal of the opposite logic is output after the "H"("L") signal is output, the potential amplitude of the output node becomes small and the ringing The generation can be effectively suppressed. In addition, when a signal is output, the time required for changing the potential of the output node is shortened, and the signal can be output at high speed.

In the output circuit according to the third aspect, the driving force of the drive element that drives the output node is increased as the potential level of the output node changes. Therefore, the output node is driven relatively slowly when ringing is likely to occur, and the output node is driven at a high speed when ringing is unlikely to occur. Therefore, an output signal can be generated at high speed without causing ringing.

In the output circuit according to the fourth aspect, the delay time of the delay means is adjusted according to the operating power supply voltage and the operating temperature. Since the delay time of the delay means is adjusted according to the operating condition, the second drive element can be activated at the optimum timing regardless of the operating condition, and the output signal is output at high speed without causing ringing. be able to.

In the output circuit according to the fifth aspect, the delay time of the delay means is adjusted according to the output permission signal and the output instruction signal. From the timing relationship between the output permission signal and the output instruction signal, it can be known whether invalid data is output to the output node. Therefore, when the valid output signal is output after the invalid output signal is output, the second drive element can be activated at an optimum timing even when the logics of the two are different, and ringing occurs. Can be reliably prevented. According to another aspect of the output circuit of the present invention, the voltage on the reference power supply node to which the drive transistor is coupled is changed relatively slowly by the first current supply element and then rapidly changed by the second current supply element. The drive transistor transmits the voltage on the reference power supply node to the output node when conducting. Therefore,
The voltage of the output node changes gently at first, and changes rapidly when the voltage on the output node reaches a voltage level at which ringing does not occur. As a result, the output signal can be output at high speed without causing ringing.

In the output circuit of claim 7, the reference voltage node coupled to the drive transistor is driven to the voltage level on the reference voltage source by the first and second drive elements. The delay time of the gate means is adjusted by the adjusting means according to whether or not the invalid signal is output. The first and second drive elements sequentially turn on in accordance with the output signal of the gate means. On the other hand, when the voltage level on the reference voltage node is gently changed according to the internal signal by the first current supply element and the ringing does not occur in the output signal, the second current supply element causes the voltage on the reference voltage node to be increased. The voltage changes rapidly. As a result, an output signal with no ringing can be output at high speed regardless of the presence or absence of an invalid signal.

In the output circuit of claim 8, claim 6 is provided.
Alternatively, in the output circuit of No. 7, the first current supply element drives the voltage on the reference voltage node to a voltage level where ringing does not occur, and then the second current supply element drives the reference voltage node to the final reached voltage level. To do. The drive element drives the output node to the voltage level on this reference voltage node in response to an internal signal. The amount of voltage change by the first current supply element is small, and the absolute value of the gate-source voltage is effectively small, so that the current supply amount is effectively reduced, and the reference voltage is set to an intermediate voltage level where ringing does not occur. Drive the voltage node. The second current supply element drives the reference voltage node to the final voltage level when ringing is no longer possible. As a result, the drive element can quickly transmit a stable output signal to the output node without causing ringing.

According to another aspect of the output circuit of the present invention, the threshold voltage and the substrate region bias voltage are different from each other, and accordingly, the current driving capability of the plurality of insulated gate field effect transistors is different. The smaller the absolute value of the threshold voltage or the absolute value of the substrate region bias voltage, the greater the current driving capability of the insulated gate field effect transistor. Therefore, the output node is set to a conductive state by sequentially setting the plurality of insulated gate field effect transistors in order of increasing current driving capability, that is, increasing absolute value of threshold voltage or increasing absolute value of substrate bias voltage. As the voltage level approaches the final reached voltage level, it is driven with a large current driving force, and accordingly, an output signal can be output at high speed while suppressing the occurrence of ringing.

In the output circuit of the tenth aspect, the output node is gently driven by first driving the output node through the resistance element, and then when the output node reaches the voltage level where ringing does not occur, the resistance element is driven. Due to the short circuit, a large current driving force drives this output node. As a result, the occurrence of ringing is suppressed, and a fast and stable output signal can be obtained.

In the output circuit of the eleventh aspect, in the resistance elements having different resistance values, the current values flowing therethrough are different from each other, and accordingly the current driving force is different. Therefore, when the current driving is sequentially performed from the resistance element having the larger resistance value, the output node is first driven with the smaller current driving force, and the output node is sequentially driven with the larger current driving force. This makes it possible to output the output signal at high speed while suppressing the occurrence of ringing.

In the output circuit according to the twelfth aspect, a voltage that increases as the ambient temperature increases and decreases as the external power supply voltage increases is transmitted to the reference voltage node. When the temperature rises, the operating speed of the drive transistor becomes slow (current driving power becomes small). Therefore, at this time, by increasing the voltage of the reference power supply node, a decrease in the operating speed of the drive transistor is suppressed. On the other hand, when the external power supply voltage increases, the drive transistor operating speed increases, and ringing may occur, the current driving force of the drive transistor is reduced when the external power supply voltage is applied by lowering the voltage of the reference power supply node. By making it smaller than that, the driving force is made smaller and the occurrence of ringing is suppressed. As a result, an output signal without ringing can be output at high speed.

In the output circuit of the thirteenth aspect, when the output signal is output, the transistor element is rendered conductive to drive the reference power supply node to the voltage level of the reference voltage source. The drive transistor drives the output node according to the voltage on the reference voltage node. It is possible to adjust the voltage level of the reference node when the output signal changes according to the response characteristics of the transistor element and the comparison means, and accordingly to suppress the sudden change of the output signal and suppress the occurrence of ringing of the output signal. can do.

In the semiconductor device of claim 14, the output signal change speed of the output circuit is set according to the distance from the bus amplifier to the output node. If this distance is long, the load from the bus amplifier to the output circuit or the load from the output circuit to the output node is large, and the change speed of the input signal or output signal is slow. Does not happen. Therefore, by adjusting the changing speed (time constant) of the output signal according to this distance, the output signal can be generated at high speed without causing ringing. Also, the output signals of all output circuits are
By adjusting this time constant at almost the same timing, the definite state can be reached, the margin of the signal output time becomes small, and a semiconductor device operating at high speed can be obtained accordingly.

In the output circuit according to claim 15,
A drive transistor having a large current driving force is arranged between the output pad and a drive element having a small current driving force.
A drive transistor having a large current driving capability has a larger channel width than a drive transistor having a small current driving capability, and the junction area between the impurity region and the substrate region and the area between the gate electrode and the impurity region are large. In addition, the junction withstand voltage and the withstand voltage are higher than those of a drive transistor having a small current driving force. Therefore, even if excessive noise such as surge voltage is applied to the output pad, excessive noise such as surge voltage is absorbed by the drive transistor with large current driving force, and drive transistor with low current driving force is destroyed by this excessive noise. It is possible to prevent the noise from occurring and to obtain an output circuit having excellent noise resistance.

In the output circuit of the sixteenth aspect, a protection circuit for absorbing excessive noise such as surge voltage is arranged between the output pad and the drive transistor having a small current driving force. Therefore, it is possible to prevent a drive transistor having a small withstand voltage and a small current driving force from being destroyed by excessive noise such as a surge voltage, and an output circuit excellent in noise resistance can be obtained.

[0064]

【Example】

[First Embodiment] FIG. 1 is a diagram showing the structure of an output circuit according to a first embodiment of the present invention. FIG. 1 shows a portion for driving output node 6 to the ground potential level. If a structure similar to that shown in FIG. 1 is used for a portion driving output node 6 to the level of power supply potential Vcc, overshoot of the output node can be prevented.

In FIG. 1, output circuit 926 includes 2-input AND circuit 10 receiving output enable signal OEM and read data signal DD on internal data bus line 915a, and output enable signal OEM and complementary signal on internal data bus line 915b. AND circuit 11 receiving the internal read data signal ZDD and AND
In response to the output of the circuit 10, the output node 6 is connected to the power supply potential Vc.
a first drive transistor 1 driven to the c level,
Drive transistor 2a driving output node 6 to the ground potential level in response to the output of AND circuit 11 and drive transistor 2b provided in parallel with drive transistor 2a are included. The current drivability of drive transistor 2a is made smaller than the current drivability of drive transistor 2b. Drive transistors 1, 2a and 2b are both formed of n-channel MOS transistors. The difference in the current driving force between the drive transistors 2a and 2b is the size or the gate (channel) width,
Alternatively, it can be realized by appropriately setting the ratio of the gate width to the gate length.

The output circuit 926 further includes an AND circuit 10.
Of the output of the node N1, that is, the inverting delay circuit 15 that delays the signal potential of the node N1 and inverts its logic, the 2-input NOR circuit 16 that receives the signal on the node N1 and the output of the delay circuit 15, and the output enable signal OEM. An inverting delay circuit 17 that delays for a predetermined time and inverts its logic, and a 2-input NO that receives the output of the inverting delay circuit 17 and the output enable signal OEM
An R circuit 18, an inversion delay circuit 19 for delaying a data output instructing signal DOT generated when the column address signal changes, and inverting its logic, and an output instructing signal DOT.
And a NOR circuit 20 that receives the output of the inverting delay circuit 19,
It includes a 2-input OR circuit 21 that receives the outputs of NOR circuits 18 and 20, and a 2-input NAND circuit 22 that receives the output of NOR circuit 16 and the output of OR circuit 21.

The 2-input NOR circuit 16 has a positive polarity one-shot pulse having a time width determined by the delay time of the inverting delay circuit 15 when the potential of the node N1 falls from "H" to "L". Generate a signal.

The 2-input NOR circuit 18 outputs the output enable signal O
Inversion delay circuit 17 when EM changes from “H” to “L”
Generates a positive one-shot pulse signal having a time width determined by the delay time of the.

The 2-input NOR circuit 20 outputs the output instruction signal D
When OT changes from "H" to "L", a one-shot positive polarity pulse signal having a time width determined by the delay time of the delay circuit 19 is generated. Output instruction signal D
OT is "L" for a predetermined time when the column address signal changes.
Is generated in the form of a one-shot pulse.

The output circuit 926 further includes an AND circuit 11
Output of the delay circuit 12, that is, the delay circuit 12 for delaying the signal on the node N2 for a predetermined time, and the signal on the node N2 and the delay circuit 1
A 2-input NAND circuit 13 for receiving the output of 2 and a NAN
It includes a 2-input NAND circuit 14 that receives the output of D circuit 13 and the output of NAND circuit 22. When the output of the NAND circuit 14 is "H", the drive transistor 2b is turned on. Next, the operation of the output circuit shown in FIG. 1 will be described with reference to the operation waveform diagram of FIG.

Now, the selected memory cell has data "L".
The data read operation in the case of storing is described. When the internal column address strobe signal ZCAS falls to the active state of "L", the internal column address signal Y
1 is generated. When the internal address signal Y1 is generated from the address buffer, the address transition detection signal φATD output from the address transition detection circuit is generated in the form of a one-shot pulse. According to the address change detection signal, the output instruction signal DOT is "L" for a predetermined period.
In accordance with this output instruction signal DOT, internal data bus line 9
15a and 915b are once precharged to "L". In the standby mode, output instruction signal OEM is at "L", the potentials of nodes N1 and N2 are "L", and drive transistors 1, 2a and 2b are all off.

In accordance with the one-shot output instruction signal DOT, the NOR circuit 20 generates a pulse having a delay time width of the inverting delay circuit 19 and the output of the OR circuit 21 becomes "H". At this time, the potential of the node N1 is still at "L" and the potential of the node N4 is still at "H". The output enable signal OEM is at "L", and the potential of the node N5 is "H". Therefore, even if this output instruction signal DOT is "L" for a predetermined period, the output of the NAND circuit 22 (potential of the node N8) is "H" and does not change.

At this time, the potential of the node N2 is "L".
And the output of the NAND circuit 13 is “H”, NA
The output of the ND circuit 14 (potential of the node N9) is at "L".

When output enable signal OEM attains an active state of "H", the potential of node N1 becomes "L" and the potential of node N2 becomes "H". As a result, the drive transistor 1
Remains off. On the other hand, drive transistor 2
a is turned on, and the potential of output node 6 is gently discharged to the ground potential level. When the delay time of the delay circuit 12 elapses, the output of the delay circuit 12 becomes "H" and the output of the NAND circuit 13 becomes "L". As a result, the output of the NAND circuit 14 becomes "H", and the drive transistor 2b is turned on. Drive transistor 2b rapidly discharges output node 6 to the ground potential level.

When the external column address signal Ad changes, the output instructing signal DOT accordingly goes low for a predetermined period. This operation mode is called a static column mode. When output instruction signal DOT attains "L", it is indicated that the data appearing at output node 6 is invalid in the next cycle. That is, it can be said that output instruction signal DOT is a signal indicating that the data appearing at output node 6 at that time should be invalidated.
In response to the transition of the output instruction signal DOT to "L",
Internal data lines 915a and 915b are both precharged to the ground potential level again. As a result, the potentials of nodes N1 and N2 are both set to "L", and drive transistors 1, 2a and 2b are turned off.
A predetermined time (the time required until the bit line pair is selected according to the column address signal and the selected data is read onto the internal data bus) after output instruction signal DOT falls to "L". After a lapse of time, internal data bus line 9
The potentials of 15a and 915b are "H" and "L", respectively. As a result, drive transistor 1 is turned on and output node 6 is charged to the level of power supply potential Vcc.

Internal column address strobe signal ZCA
When S becomes inactive "H", output enable signal OEM also becomes "L". In response to this, the NOR circuit 1
From 8, a one-shot pulse is generated. On the other hand, at this time, the potential of the node N1 also falls from "H" to "L", and the drive transistor 1 is turned off. In response to the fall of the potential of the node N1, the NOR circuit 16
From, a one-shot pulse signal is generated on node N4. The inverting delay circuit 15 is composed of, for example, five stages of inverters, and the inverting delay circuit 17 is, for example, 3 stages.
Inverting delay circuit 1
The delay time of 5 is longer than the delay time of the inverting delay circuit 17. Therefore, the potential of the node N4 is "H"
At this time, the potential of the node N7 (output of the OR circuit 21) becomes “H”, and the potential from the NAND circuit 22 to the node N8 is
A one-shot pulse signal of "L" having a time width determined by the delay time of the inverting delay circuit 17 is generated. In response, a one-shot pulse of "H" is generated from the NAND circuit 14 on the node N9, and the drive transistor 2
b is turned on. As a result, output node 6 is discharged from the power supply potential Vcc level to the ground potential level for a predetermined time, and the potential of output node 6 attains an intermediate potential level between power supply potential Vcc and ground potential GND. The intermediate potential level of output node 6 is determined by the driving force of drive transistor 2b, the external load and the delay time of inverting delay circuit 17.

As described above, since the drive transistor 2b discharging to the ground potential level is turned on for a predetermined time after the completion of reading "H" data, a structure for holding the potential of output node 6 at the intermediate potential is provided. Even if not, the potential of the output node 6 is at the intermediate potential level. Therefore, regardless of whether the data read in the next cycle is "H" or "L", since output node 6 is driven from the intermediate potential level, the output amplitude is small and ringing may occur. Therefore, a stable output signal Q can be obtained at high speed. This fast and stable output signal Q
Thus, for example, even when "L" data is output after "H" data is output in the static column mode, ringing does not occur at the output node 6 and the stable output signal Q is obtained. Can be output.

By providing the configuration shown in FIG. 1 also for drive transistor 1, output node 6 is pulled up after the completion of "L" data reading as shown by the broken line in FIG. Can be set to a level.

FIG. 3 is a diagram showing the configuration of an output circuit when a control system is provided for both "H" and "L" data reading. In FIG. 3, control blocks 40a and 4
0b are the NOR circuits 16, 18, 20 shown in FIG.
An OR circuit 21, a NAND circuit 22, and inverting delay circuits 15, 17, and 19. The delay circuits 12a and 12b correspond to the delay circuit 12 shown in FIG.
D circuits 13a and 13b correspond to NAND circuit 13 shown in FIG. 1, and NAND circuits 14a and 14b correspond to NAND circuit 14 shown in FIG.

Therefore, if the circuit structure shown in FIG. 3 is used, as shown in FIG. 4, in the static column mode operation, the output node is driven to the intermediate potential in accordance with the output instructing signal DOT, and when the memory cycle is completed. Output node 6 is driven to an intermediate potential according to output instruction signal OEM. Therefore, in any case,
Since the output node 6 is driven to "H" or "L" from the intermediate potential, it is possible to generate a stable output signal without causing ringing.

FIG. 5 is a diagram showing the structure of the output instruction signal and output permission signal generation system. The control signal generation system shown in FIG. 5 is included in the input / output control circuit shown in FIG.

Referring to FIG. 5, the output control signal generation circuit is activated in response to internal row address strobe signal ZRAS, and outputs a one-shot "L" pulse signal in response to address transition detection signal φATD. A one-shot pulse generation circuit 50 for generating and a delay circuit 51 for delaying the internal column address strobe signal ZCAS for a predetermined time.
And a one-shot pulse generation circuit 52 that generates a one-shot pulse signal in response to the rise of the output instruction signal DOT from the one-shot pulse generation circuit 50, an internal write enable signal ZWE, and an internal column address strobe signal ZCAS. A gate circuit 57 for receiving and outputting a signal of "H" when a data read operation is designated;
Output of one-shot pulse generation circuit 52 and gate circuit 5
2-input NAND circuit 55 receiving the output of 7 and the delayed column address strobe signal ZCA from delay circuit 51.
It is set in response to an inverter circuit 54 that inverts SE and an "L" signal from the inverter circuit 54.
It includes a flip-flop 56 that is reset in response to the "L" signal from the D circuit 55, and an inverter circuit 58 that inverts the output of the flip-flop 56. Output instruction signal OEM is generated from inverter circuit 58.

The one-shot pulse generation circuit 52 includes a delay circuit 61 for delaying the output instruction signal DOT by a predetermined time,
It includes a 2-input AND circuit 62 that receives the output of delay circuit 61 and output instruction signal DOT. The delay circuit 61 is composed of an even number of inverters (two inverter circuits in the configuration shown in FIG. 5).

Flip-flop 56 includes two cross-coupled NAND circuits NA1 and NA2. NAN
D circuit NA1 receives the output of inverter circuit 54 at one input and the output of NAND circuit NA2 at the other input. The NAND circuit NA2 has one input NA
The output of the ND circuit 55 is received, and the output of the NAND circuit NA1 is received at the other input. The output of NAND circuit NA1 is applied to inverter circuit 58.

Gate circuit 57 outputs a signal of "H" when internal column address strobe signal ZCAS is "L" and write enable signal ZWE is "H". The gate circuit 57 may be replaced with an inverter that inverts the output enable signal ZOE when the dynamic semiconductor memory device used has a configuration using the output enable signal ZOE. It is only necessary to use the configuration of outputting the "H" signal during the data read operation.

The control signal generating system further inverts the output instructing signal DOT from the one-shot pulse generating circuit 50, and in response to the output of the inverter circuit 59, the internal data bus lines 915a and 915b are grounded. It includes precharge transistors 60a and 60b for precharging to a level. Precharge transistors 60a and 60b are both formed of n-channel MOS transistors. Next, the operation of the control signal generation system shown in FIG. 5 will be described with reference to FIG. 6 which is an operation waveform diagram thereof.

When row address strobe signal ZRAS is in the inactive state of "H", output instruction signal DOT
Is at "L" and the column address strobe signal ZC
AS is in an inactive "H". At this time, the potentials of internal nodes N11, N12 and N13 are "L", and the potentials of nodes N10, N14 and N15 are "H".

When the row address strobe signal ZRAS is activated to "L", the memory cycle starts. In response to this "L" internal row address strobe signal ZRAS, one-shot pulse generation circuit 50 is activated, and output instruction signal DOT, which is the output thereof, is raised to "H". When a predetermined time elapses after the output instruction signal DOT becomes “H”, the one-shot pulse generation circuit 5
A signal of "H" is output from 2. When the column address signal changes, address change detection signal φATD is generated in response to the change. It should be noted that in the semiconductor memory device capable of the static column operation mode, the column address strobe signal has only the function of the output enable signal, not the address latch instruction function. This address change detection signal φ
In response to ATD, output instruction signal DOT is set to "L" for a predetermined period. When the output instruction signal DOT becomes "L", the output of the one-shot pulse generation circuit 52 (node N
12) becomes “L”. This one-shot output instruction signal DO is output from the one-shot pulse generation circuit 52.
An "L" signal whose pulse width is longer than T by the delay time provided by the delay circuit 61 is output.

When the one-shot pulse generation circuit 52 outputs the signal of "L" on the node 12, the NAND circuit 55 outputs the signal of "H" on the node N13.

Next, the column address strobe signal ZC
When AS becomes “L”, the delay column address strobe signal Z becomes “L” after a predetermined time has passed from the delay circuit 51.
CASE is generated. By this "L" delayed column address strobe signal ZCASE, the inverter circuit 5
An "H" signal is output from node 4 to node N11.

On the other hand, the potential of the node N14 is at "H", and in response to the rise of the potential of the node N13, the potential of the node N14 is increased.
15 becomes "L". The potential of the node N15 is the node N1
When it goes to "L" in response to the rise of the potential of 3, the potential of the node N15 goes to "H", and the NAND circuit NA1 outputs a signal of "L" to the node N14. In response to the fall of the potential of the node N14, the inverter circuit 5
The output signal from 8, that is, the output permission signal OEM becomes "H".

Internal column address strobe signal ZCA
While S (ZCASE) is "L" and the potential of the node N15 is "H", the potential of the node N14 is fixed to "H". That is, the output permission signal OEM becomes "H".

Internal delay column address strobe signal Z
When CASE is "L", output instruction signal DOT
Is "L" and the potential of the node N13 is "H", the potential of the node N14 is "L" and the potential of the node N15 is low.
The potential of does not change. That is, while the delayed column address strobe signal ZCASE is "L", the output instruction signal D
Even if the OT is generated, the output enable signal OEM maintains the "H" state.

On the other hand, when output instructing signal DOT goes "L", the output of inverter circuit 59 goes "H", precharge transistors 60a and 60b are both turned on, and internal data bus lines 915a and 915b are grounded for a predetermined time. Discharge to potential level. Thus, in the static column mode and the normal mode, internal data bus lines 915a and 915b can be temporarily brought to the precharged state of the ground potential level of the predetermined potential when new data is to be read.

Internal data bus lines 915a and 91
When the precharge operation of 5b to the ground potential level is executed only during data reading, gate circuit 57 is used.
The inverter circuit 59 may be configured to be in an operable state when the output of is "H". This configuration
This is easily realized by receiving the output of the gate circuit 57 and the output instruction signal DOT by an AND circuit and applying the output of the AND circuit to the precharge transistors 60a and 60b.

With the configuration of the control circuit described above, regardless of whether "H" or "L" data is read, the output node 6 is surely set to the intermediate potential level when the next new data is to be read. Can be precharged.

The delay circuits 15, 17, 1 shown in FIG.
The number of stages of the inverter circuits of the delay circuits 61 shown in FIGS. 9 and 12 and FIG. 5 is not limited to the number of stages shown in the figure, and may be set to the number of stages giving an appropriate delay time.

[Modification 1] FIG. 7 shows a modification of the output circuit of the first embodiment. In the structure shown in FIG. 7, an n channel MOS transistor 62 is provided which is conductive in response to the output of NAND circuit 22 and drives output node 6 to reference potential VREF for a predetermined period. The NAND circuit 1 is connected to the drive transistor 2b having a large driving force.
The output of 3 is given through the inverter 63. In this structure, when the output node 6 is discharged, first the drive transistor 2a operates to gently discharge the output node 6, and after a predetermined time elapses, the drive transistor 2b is turned on to rapidly output the output node 6. Discharge to ground potential level. "H" when one read operation is completed or in static column mode
When the output signal of "L" is output after the output signal of
It conducts in response to the output of the circuit 22 and drives the output node 6 to the reference potential VREF. If a potential level of Vcc / 2 used in a dynamic semiconductor memory device is used as reference potential VREF, output node 6 can be reliably driven to intermediate potential Vcc / 2, and "H". At the time of reading data and at the time of reading "L" data, the data determination timing can be made the same without any ringing, and high-speed access can be realized (access time is "H" data and This is because it is determined by the longer data confirmation time when reading "L" data).

[Modification 2] FIG. 8 is a view showing still another modification of the first embodiment. In FIG. 8, a delay circuit 15b and a NOR circuit 16b are provided in order to generate a signal which is at "H" for a predetermined period in response to the fall of the potential of node N2. The delay circuit 15b has a node N1.
It has a structure similar to that of the inverting delay circuit 15a for generating a one-shot pulse in response to the fall of the potential. The outputs of the NOR circuits 16a and 16b are the OR circuit 6
Given to 4. The output of the OR circuit 64 is the NAND circuit 2
Given to 2.

According to the structure shown in FIG. 8, a one-shot pulse signal can be generated when the potentials of nodes N1 and N2 fall to turn on precharge transistor 62 for a predetermined period. Therefore, output node 6
Regardless of whether the data signal appearing at "H" or "L", when one data read cycle is completed or when new data is to be read, precharge transistor 62 is turned on and output node 6 is turned on. It becomes possible to precharge to the intermediate potential VREF.

As described above, according to the first embodiment, the output node is driven to the intermediate potential when the data signal read operation is completed or when new data should be read next. . Therefore, when a new signal is output, whether the data signal of "H" or "L" is output, the output node 6 is driven from the intermediate potential to the potential of the corresponding logic level. The potential amplitude of the node can be reduced, the occurrence of ringing can be prevented, and a data signal can be stably output at high speed. At this time, since the output node is held at the intermediate potential again, it is possible to shorten the time required to determine the potentials of the "H" and "L" levels, and to enable high-speed access.

Further, from the intermediate potential to "H" or "L"
Since the output node is driven to the potential level of, the current consumption at the time of outputting the data signal can be reduced.

[Embodiment 2] FIG. 9 shows a structure of an output circuit according to a second embodiment of the present invention. FIG. 9 shows a circuit structure for discharging output node 6 to the ground potential level.

Referring to FIG. 9, the output circuit receives an inverter circuit 5 for inverting internal read data signal ZDD, an output enable signal OEM and an output of inverter circuit 5.
It includes an ND circuit 3 and an AND circuit 4 receiving an output enable signal OEM and an internal read data signal ZDD. Internal read data signal ZDD is a data signal having a logic opposite to that of data DD.

The output circuit further includes the output of the AND circuit 4,
That is, delay circuit 12 delaying the signal on node N2 for a predetermined time, NAND circuit 13 receiving the signal on node N2 and the output of delay circuit 12, inverter circuit 64 receiving the output of NAND circuit 13, and output node 6 on output node 6. P channel MOS transistor 67 which adjusts the "H" driving force of inverter 64 in response to the signal potential of. The inverter circuit 64 includes p-channel Ms that are connected in a complementary manner.
It includes an OS transistor 66 and an n-channel MOS transistor 65. The transistor 67 is a p-channel MO
It is provided between S transistor 66 and a power supply potential node supplying power supply potential Vcc, and its gate receives a signal on output node 6.

In response to the output of AND circuit 3, the output circuit further includes an n channel MOS transistor 1 for charging output node 6 to the level of power supply potential Vcc, and an AND circuit.
In response to the output of the circuit 4, the potential of the output node 6 is relatively slowly discharged, and an n-channel MOS transistor (drive transistor) 2a and an inverter circuit 64 are provided.
N-channel MOS transistor (drive transistor) 2b which discharges the potential of output node 6 to the ground potential level in response to the output of. The current driving capability of the transistor 2a is smaller than that of the transistor 2b. Next, the operation of the output circuit shown in FIG. 9 will be described with reference to the operation waveform diagram of FIG.

First, the operation when internal read data signal ZDD attains "H" will be described. Output enable signal OEM
Is "L", the outputs of AND circuits 3 and 4 are both "L", and drive transistors 1, 2a and 2
b are all off.

When the output enable signal OEM rises to "H", the output of the AND circuit 4 becomes "H". This allows
Drive transistor 2a is turned on, and output node 6 is discharged relatively slowly. The signal potential on output node 6 is applied to the gate of transistor 67. The driving force of the transistor 67 increases (the conductance increases) as the gate potential decreases. When a predetermined time has passed, the NAND circuit 13
Output (signal potential on the node N3) becomes "L". In response to the fall of the signal potential on the node N3, the output of the inverter circuit 64 becomes "H". The potential level of the "H" signal output from the inverter 64 changes depending on the potential level of the output node 6. The transistor 67 is the p-channel MOS transistor 6 of the inverter circuit 64.
The voltage transmitted to 6 is Vcc-V (6) -Vth. Here, V (6) represents the potential of the output node 6,
Vth represents the absolute value of the threshold voltage of p channel MOS transistor 67. Therefore, as the potential of output node 6 decreases, the potential level of "H" output from inverter circuit 64 rises, drive transistor 2b is turned on more strongly, and the potential of output node 6 is brought to the ground potential level at high speed. And discharge. That is, the inverter circuit 6
When the potential level of the output "H" of the output node 4 rises as the potential of the output node 6 drops, the drive transistor 2b is strongly turned on accordingly, and when the potential of the output node 6 drops sufficiently, the drive transistor 2b Discharges output node 6 to ground potential faster. This allows
When the potential of the output node 6 reaches a potential level at which ringing does not occur, the drive transistor 2b discharges the output node 6 to the ground potential level at high speed, so that ringing does not occur and an output signal is stably generated. You can

This p-channel MOS transistor 67
May be considered as a resistance element in which a normally-on transistor is used and the resistance value (conductance) thereof increases as the potential of the output node 6 decreases. In this case, when the output of the inverter 64 becomes "H", the rise of the output potential becomes faster according to the fall of the potential of the output node 6, and the drive transistor 2b
Is strongly turned on in response to the fall of the potential of the potential output node 6.

In the operation waveform diagram shown in FIG. 10, when output node 6 is discharged to the ground potential level and output enable signal OEM attains "L", drive transistors 1, 2a and 2b are all turned off. The operation waveform of the state is shown. However, output node 6 may be used in combination with the configuration in which it is held at the intermediate potential level as in the first embodiment. In FIG. 10, the potential change of output node 6 at this time is shown as Q '. When the output node 6 is held at the intermediate potential level, the discharge power is increased as the potential decreases, and the following advantages are obtained.

FIG. 11 shows operation waveforms when valid read data is transmitted after output enable signal OEM is activated. In FIG. 11, output node 6 is shown to be precharged to the intermediate potential. When output enable signal OEM is "L", output node 6 is precharged to the intermediate potential. Output enable signal OEM
Rises to "H", at which time the internal read data signal Z
If DD is "L", the potential of the node N1 rises to "H", the potential of the output node 6 rises, and the output data Q'becomes "H". When a valid data appears after a lapse of a predetermined time and internal read data signal ZDD attains "H", the potential of node N2 rises to "H" and the potential of node N1 falls to "L". As a result, drive transistor 2a is turned on, output node 6 is gently discharged to the ground potential level, and the potential of output signal Q'decreases gradually.

Then, after a lapse of a predetermined time, the node N3 (N
When the output of the AND circuit 13) becomes "L", the output of the inverter circuit 64 gradually rises. The rising speed of the output of inverter circuit 64 is determined by the potential of output node 6. Therefore, when the potential of output signal Q'is high, the output of inverter circuit 64 rises gently, and when the potential of output signal Q'is sufficiently low, the output of inverter circuit 60 rises rapidly to the power supply potential Vcc level. Go up. The drive power of drive transistor 2b is increased when the potential of output node 6, that is, the potential of output signal Q'is sufficiently reduced, and discharges output node 6 to the ground potential level at high speed. As a result, in the operation in which invalid data is output and then valid data is output, even if the logics of the valid data and invalid data are different, the current driving capability of the drive transistor 2b is set to the potential level of the output node 6. By adjusting accordingly, an output signal can be stably generated without generating ringing.

The operation mode in which invalid data appears on output node 6 will be described later in detail.

FIG. 12 shows a structure of a portion for driving the output node to the "H" level. In FIG. 12, the output node 6 is driven (charged) to the power supply potential Vcc level.
In order to achieve this, a drive transistor 1a formed of an n-channel MOS transistor which conducts in response to a signal potential on node N1 is provided and drive transistor 1a is provided.
A drive transistor 1b is provided in parallel with.

The control portion of the output circuit further receives a delay circuit 12a for delaying the signal potential on node N1 for a predetermined time, and an NA for receiving the signal on node N1 and the output of delay circuit 12a.
ND circuit 13a, p-channel MOS transistor 71 and n-channel MOS transistor 73 whose gates receive the output of NAND circuit 13a, p-channel MOS transistor 72 provided between transistors 71 and 73, and a signal on output node 6. Receives at the gate
Channel MOS transistor 75 and transistor 75
P channel M provided between the power supply potential supply node and the
The OS transistor 74 is included. The gate of transistor 74 is connected to the connection point of transistors 72 and 73 and the gate of drive transistor 1b. The gate of transistor 72 is connected to the node of transistors 74 and 75. The operation of the circuit shown in FIG. 12 will now be described with reference to the operation waveform diagram of FIG.

Now, it is assumed that internal read data signal ZDD is "L". When the output permission signal OEM is "L",
The potentials of nodes N1 and N2 are both "L", and drive transistors 1a and 2 are both off. Since the potential of the node N1 is “L”, the output of the NAND circuit 13a is “H”, and the transistor 73 is turned on to the drive transistor 1b.
The signal of "L" is given. Therefore, drive transistor 1b is also off. When output enable signal OEM rises to "H", the potential of node N1 rises to "H" and drive transistor 1a is turned on. The current driving capability of drive transistor 1a is made relatively small, and the potential of output node 6 is gradually raised.
After a lapse of a predetermined time, the output of the NAND circuit 13a (output potential of the node N3a) becomes "L", the transistor 73 is turned off, and the transistor 71 is turned on.
The potential of output node 6 is applied to the gate of transistor 75. When the potential level of output node 6 is at the intermediate potential level, the current driving capability of transistor 75 is small (conductance is small) and the current driving capability of transistor 74 is larger, and therefore the gate potential of transistor 72 is relatively high. , The conductance of the transistor 72 is small. Therefore, in this state, the potential of drive transistor 1b gradually rises, and drive transistor 1b has its current driving capability limited and charges output node 6 relatively slowly. When the potential of the output node 6 is sufficiently increased, the current driving capability of the drive transistor 75 is increased, the potential of the transistor 72 is accordingly lowered sufficiently, the current driving capability of the transistor 72 is increased, and the potential of the transistor 1b is increased at high speed. As a result, the current driving force is increased and the output node 6 is charged at high speed.
At this time, the current drivability of the transistor 74 is reduced as the gate potential of the transistor 1b is increased, and the gate potential of the transistor 72 is discharged at high speed with the potential increase of the output node 6, so that the transistor 72 is sufficiently discharged. It becomes a strong ON state, and accordingly the drive transistor 1
The current driving force of b is increased at high speed. Thus, when the potential of output node 6 rises to a potential level at which ringing does not occur, the potential rises at a high speed, and an output signal can be stably generated without the occurrence of ringing. In FIG. 13, the operation waveform when the output node 6 is charged to the intermediate potential is output signal Q '.
Are also shown.

As described above, according to the structure of the output circuit of the second embodiment, since the driving force of the output node is adjusted according to the potential level of the output node, the potential of the output node causes ringing. The potential of the output node is changed at high speed when it reaches the potential level that does not occur, and a stable output signal without ringing can be generated.

[Third Embodiment] In a dynamic semiconductor memory device having a static column mode function, a column selecting operation is executed in accordance with an address transition detection signal φATD generated in response to a change in a column address signal. The column address strobe signal ZCAS is only used to determine the data output timing. Therefore, in this case, after the row address strobe signal ZRAS is activated, the column address strobe signal ZC is activated.
Time required for AS to become active, that is, RAS
-CAS delay time TRCD and time required from the change of the column address signal Ad to the change of the column address strobe signal ZCAS Column address-CAS delay time T
Invalid data may occur at the output node depending on the ASC relationship. Before describing the third embodiment, the operation when invalid data is output and when invalid data is not output will be described with reference to the control signal generation circuit shown in FIG.

First, with reference to FIGS. 5 and 14, the operation when invalid data is not output will be described.

When row address strobe signal ZRAS is activated and attains "L", the memory cycle starts, and address signal Ad applied at that time is taken in as row address signal X, and the row selecting operation is executed. In this state, the control circuit shown in FIG. 5 is in the initial state,
Output enable signal OEM is at "L".

When row address strobe signal ZRAS is activated and becomes "L", one-shot pulse generation circuit 50 is enabled and its output becomes "H". The column address transition detection signal φATD is enabled in response to the row address strobe signal ZRAS in the column address buffer 907 in the static column mode. 907 output does not change, so one-shot address change detection signal φATD
Is not generated (see FIG. 60). Alternatively, pulse change detection circuit (ATD circuit) 920 may be configured to be operable when row address strobe signal ZRAS is "L".

When the row address hold time elapses,
Then, the address signal Ad changes and the column address signal Y is generated. In response to the change of the address signal Ad, the address change detection signal φATD is activated, and the output instruction signal DOT generated from the one-shot pulse generation circuit 50 is at “L” for a predetermined period. In response to the transition of the output instruction signal DOT to "L", the one-shot pulse generation circuit 52 supplies a pulse signal of "L" having a longer "L" period than the output instruction signal DOT to the node N12. . The pulse width of the "L" one-shot pulse signal applied to node N12 is longer than the period in which output instruction signal DOT is "L" by the delay time provided by delay circuit 61.

When the potential of the node N12 becomes "L", N
The AND circuit 55 outputs a signal of “H” on the node 13.

At the time of data reading, gate circuit 57
Is at "H". In the initial state, the node N
The potential of 14 is at "H", and when the potential of the node N13 becomes "H", the potential of the node N15 becomes "L".
This surely sets the potential of the node N14 to the "H" level. In this state, the output instruction signal OE
M is still "L" inactive.

When the address-CAS delay time TASC is sufficiently long, even if the output instruction signal DOT becomes "H",
The delayed column address strobe signal ZCASE is still at "H". In this state, node N14 is still
Is at "H". Therefore, the output instruction signal DO
When T becomes "H", the potential of the node N13 falls to "L" and accordingly the potential of the node N15 rises to "H".

Next, address-CAS delay time TAC
When D has passed, the column address strobe signal ZCA
S is activated and becomes "L", and accordingly the delayed column address strobe signal ZCASE becomes "L". When the delayed column address strobe signal ZCASE becomes "L", the inverter circuit 54 outputs a signal of "H" on the node N11. Since the potential of the node N15 is "H", the potential of the node N14 becomes "L" and the output instruction signal OEM becomes "H" in response to the rise of the potential of the node N11.

When output enable signal OEM attains "H", valid data ZDD has already appeared. According to this data signal ZDD, the potential of node N1 is "L", node N is at node N1.
The potential of 2 becomes "H". When the potential of the node N2 becomes “H”, the drive transistor 2a is turned on,
The output Q gradually decreases, then the drive transistor 2b is turned on, and the potential of the output Q is decreased at high speed.

As described above, if time TASC is sufficiently long, invalid data is not output, and output signal Q stably changes from the intermediate potential level to the ground potential level or the power supply potential level without causing ringing. be able to.

FIG. 15 shows operation waveforms when invalid data is output. The operation of invalid data output will be described below with reference to FIGS. 15 and 5.

Row address strobe signal ZRAS is activated and attains "L". In response to activation of row address strobe signal ZRAS, output instruction signal DOT
Becomes "H". In response to activation of the internal row address strobe signal ZRAS, the address Ad given at that time is taken in as a row address signal (X address), and the row corresponding to this X address is selected.

When address signal Ad changes, address change detection signal φATD is generated. According to this address transition detection signal φATD, one-shot pulse generation circuit 50 generates an output instruction signal DOT which is a “L” one-shot pulse signal after a lapse of a predetermined time.

Immediately after generation of the column address signal, column address strobe signal ZCAS falls to "L". That is, assume that the address-CAS delay time TASC is extremely short. At this time, before the output instruction signal DOT becomes "L", the delayed column address strobe signal ZC
ASE becomes “L”. In response to this, the node N11
Since the potential of the node N15 is "H" and the potential of the node N15 is "H", the output of the NAND circuit NA1 (the potential of the node N14) is "L" and the output enable signal OEM is "H". After the output instruction signal DOT becomes “L”, valid data is output after a predetermined time has elapsed, and the internal read data Z
DD rises to "H". Therefore, the output permission signal O
When EM is "H", invalid data appears,
Output signal Q according to this "L" invalid data signal ZDD
The potential of rises. Then valid data appears,
The output signal Q decreases according to the internal read signal ZDD of "H".

Therefore, when "L" data is output as valid data after "H" data is output as invalid data, when the output signal Q is set to the intermediate potential. However, when the potential amplitude becomes large and the drive transistor 2b is turned on, the potential of the output node 6 is not sufficiently lowered, and the output signal Q may be ringing. Therefore, a configuration in which ringing does not occur even when such invalid data is output will be described below. In the following explanation,
The output signal Q will be described on the assumption that it is precharged to the intermediate potential. Also, only the drive section for setting the output signal Q to "L" will be described, but this is because the output signal Q is "H".
A similar configuration can be provided for the path when the vehicle rises to.

FIG. 16 is a diagram showing the structure of the output circuit of the third embodiment of the present invention. FIG. 16 shows a structure for preventing ringing from occurring at the output node 6 when outputting an "L" data signal. If a similar structure is provided for node N1 (output of AND circuit 3), a structure for preventing the occurrence of ringing at the time of outputting "H" data can be realized.

Referring to FIG. 16, the output circuit basically has an output permission signal OEM and an internal read data signal ZD.
AND circuit 4 receiving D and internal read data signal ZDD
An inverter circuit 5 that inverts the signal, an AND circuit 3 that receives the output of the inverter circuit 5 and the output permission signal OEM, and AN
In response to the output of the D circuit 3, the output node 6 is set to the power supply potential Vc.
AND with drive transistor 1 that charges to the c level
In response to the output of the circuit 4, a drive transistor 2a having a small current driving capability for gently discharging the output node 6 to the ground potential level is provided in parallel with the drive transistor 2a, and the output node 6 is larger than the drive transistor 2a. Drive transistor 2 that discharges with current driving force
b is included.

The control system for controlling the operation of drive transistor 2b includes an inverter circuit 81 which inverts output instruction signal DOT, a NAND circuit which receives the signal of node N2 (output of AND circuit 4) and the output of inverter circuit 81. 82 and a flip-flop 84 receiving the output of NAND circuit 82 and the signal on node N2. This flip-flop 84 is a cross-coupled NAND circuit NA3.
And NA4. One input of the NAND circuit NA3 receives the output of the NAND circuit 82, and the other input is N.
It receives the output of AND circuit NA4. NAND circuit NA4
Receives the output of the NAND circuit NA3 at its one input,
The other input receives the signal on node N2. The flip-flop 84 has a function of determining whether or not valid data appears at the node N2.

The control system further includes a flip-flop 84.
An inverter circuit 85 that receives the output of the NAND circuit NA3 (the signal on the node N25) included in
Circuit 86, delay circuit 87 delaying the output of inverter circuit 85 for a predetermined time, delay circuit 88 delaying the output of NAND circuit 86, NAND circuit 89 receiving the outputs of delay circuits 87 and 88, and node N2 on node N2. Signal and NAN
An AND circuit 90 receiving the output of the D circuit 89 is included. AN
The output of D circuit 90 is applied to the gate of drive transistor 2b.

The delay time T1 of the delay circuit 87 is equal to the delay circuit 8
It is set longer than the delay time T2 of 8. Next, the operation of the output circuit shown in FIG. 16 will be described with reference to the operation waveform diagram of FIG.

First, the operation when the invalid data signal is output will be described with reference to FIG. Here, it is assumed that the invalid data signal is the "L" data signal ZDD and the valid data signal is the "H" data signal ZDD.

When an invalid data signal is output, output instruction signal OEM first attains "H" and then output instruction signal DOT attains an active state "L". Output enable signal OEM
Rise to "H", the potential of the node N2 is at "L" according to the invalid data signal ZDD. In this state, drive transistor 1 is on, drive transistor 2a is off, and output node 6 is charged through drive transistor 1 and its potential rises. In this state, when output instruction signal DOT falls to "L", inverter 81 outputs a signal of "H" to node N23. When the output instruction signal DOT is "L",
Valid data appears and internal read data signal ZDD rises to "H". As a result, the potential of the node N2 rises to "H", the drive transistor 2a is turned on, the drive transistor 1 is turned off, and the output node 6 is gently discharged.

When the potential of the node N2 rises to "H",
Since the potential of the node N23 is "H", the NAND circuit 82 outputs a signal of "L" to the node N24. When the potential of the node N24 becomes "L", the flip-flop 84 is set and the potential of the node N25 becomes "H" (the potential of the node N26 is "H"). Node N
When 25 rises to "H", the NAND circuit NA4 included in the flip-flop 84 receives the signals of "H" at both inputs thereof, so that the potential of the node N26 becomes "L",
The potential of the node N25 is fixed at "H".

When the potential of the node N25 rises to "H", the potential of the node N27 becomes "L". Node N27
When the potential of is "H", the output of the AND circuit 83 becomes "L" because the output instruction signal DOT is "L". Therefore, the output of the NAND circuit 86 is fixed at "H".

When the delay time T1 of the delay circuit 87 elapses, the NAND circuit 89 outputs "L" from the delay circuit 87.
Signal is output to the node N30. At this time, the potential of the node N2 is "H", and AND
The circuit 90 outputs a signal of "H" on the node N31 to turn on the drive transistor 2b. As a result, output node 6 is discharged at high speed through drive transistor 2b.

As described above, when the invalid data exists, output enable signal OEM is activated prior to the change of output instruction signal DOT. In this case, the delay circuit 87 having a long delay time allows the output drive transistor 2
The on-transition timing of b is determined. As a result, the output node 6 is discharged at high speed via the drive transistor 2b after the potential of the output node 6 is sufficiently lowered. Even when invalid data and valid data having different logics are output, the occurrence of ringing can be reliably and reliably prevented.

Next, the operation when the invalid data signal is not output will be described with reference to FIG.

When invalid data is not output, output permission signal OEM attains "H" after generation of output instruction signal DOT. As is clear from the circuit configuration of FIG.
When output instructing signal DOT is "H", output enable signal OEM is generated in accordance with delayed column address strobe signal ZCASE.

In this state, output enable signal OEM
Has risen to "H", the valid read data signal ZDD of "H" has already been output, and the potential of the node N2 is "H" in response to the rise of the potential of the output enable signal OEM.
Becomes When the potential of node N2 rises to "H", output instruction signal DOT has already returned to "H", and AND circuit 83 outputs the signal of "H" to node N28. On the other hand, in the flip-flop 84, the node N26
Is set to "H" in the initial state, and the node N25 is set to "L" in the initial state. Therefore, even if the output instruction signal DOT becomes "L" when the potential of the node N2 is "L", the latch state of the flip-flop 84 does not change. Similarly, the node N2
The output of the NAND circuit 82 is "H" (the output of the inverter circuit 81 has already fallen to "L") even when the potential of the signal rises from "L" to "H", and the latch of the flip-flop 84 is latched. The state does not change. Therefore, the node N
The potential of 27 is fixed at "H".

In this state, the potential of node N2 rises to "H" and accordingly the potential of node N28 is "H".
Rises to, the potential of the node N29 rises to the NAND circuit 86.
Will fall to "L". After the delay time T2 of the delay circuit 88 elapses, the NAND circuit 89 outputs the signal of “H” to the node N30. As a result, the AND circuit 90
Outputs a signal of "H" on the node N31 to turn on the drive transistor 2b.

When invalid data is not output, the address access time TASC is relatively long. In this case, since the invalid data signal is not output, when output enable signal OEM is activated, output node 6 is gently discharged by drive transistor 2a and its potential lowers. At this time, after the elapse of the delay time T2 provided by the delay circuit 88, the drive transistor 2b is turned on,
The output node 6 is discharged at high speed to the ground potential level. At this time, since the invalid data is not output, the drive transistor 2b having a large driving force is activated after the potential of the output node 6 is sufficiently reduced.
A stable output signal can be obtained without ringing.

In the operation waveform diagram shown in FIG. 17, internal read data signal ZDD is set to the "L" state during standby. As in the case of the first embodiment, a structure is used in which both internal data lines 915a and 915b are precharged to the ground potential level when the output node is held at the intermediate potential.

The current drivability of drive transistors 2a and 2b can be realized by varying the size of drive transistors 2a and 2b, that is, the ratio of gate width W to gate length L. The drive transistors 2a and 2b may have different β (a constant proportional to W / L).

Further, drive transistors 2a and 2b
Does not need to have a different current driving force. When the drive transistor 2b is on, the drive transistor 2a is also on, so that the output node 6 is discharged through the two transistors. Therefore, the discharge capacity of the output node 6 is equivalently increased. Even if the current driving capabilities of drive transistors 2a and 2b are the same, the same effect can be obtained.

Further, even if three or more transistors for discharging the output node 6 are provided and the discharge of the output node 6 is realized in a plurality of stages, the same effect as in the above embodiment can be obtained. it can. In this configuration, a delay circuit is further provided at the output of the AND circuit 90 in the configuration shown in FIG. 16, and a transistor which conducts in response to the output of the delay circuit is additionally provided between the output node 6 and the ground potential. It can be easily realized.

Delay circuits 87 and 88 shown in FIG.
The number of stages of the inverter is arbitrary as long as the condition that the delay time of the delay circuit 87 is shorter than the delay time of the delay circuit 87 is satisfied, and a delay element different from the inverter may be used (for example, RC delay element). .

[Modification 1] FIG. 18 shows a structure and an operation of a main portion of a modification of the output circuit shown in FIG.
In FIG. 18A, the output control unit is not provided with delay circuits 87 and 88 shown in FIG. NAND circuit 89 receives signals from NAND circuit 86 and inverter circuit 85 shown in FIG. The output of NAND circuit 89 is applied to AND circuit 90 shown in FIG.

In FIG. 18A, the NAND circuit 89
Is provided between the power supply potential supply node and the output node 894, and is provided between the power supply potential supply node and the output node 894 and the p-channel MOS transistor 890 whose gate receives the output signal A from the NAND circuit 86. Output signal B from the inverter circuit 85 to its gate
A p-channel MOS transistor 891 for receiving the signal is included.
The current driving capability of the transistor 890 is the transistor 891.
Is larger than the current driving force of. NAND circuit 89
Is an n-channel MOS transistor 892 whose gate receives the output signal A from the NAND circuit 86, and n which receives the output signal B from the inverter circuit 85 in its gate.
A channel MOS transistor 893 is included. Transistors 892 and 893 are connected in series between output node 894 and the ground potential node. The signal on output node 894 is applied to AND circuit 90 at the next stage. The current drivability of transistors 892 and 893 may be set to be the same. Next, the NAND shown in FIG.
The operation of the circuit will be described with reference to the operation waveform diagram of FIG.

If the output signal A from the NAND circuit 86 is at "L", the p-channel MOS transistor 890
Turns on. As a result, the potential of output node 894 is charged by transistor 890 with a relatively large driving force, and rises to "H" at a relatively high speed.

On the other hand, when the output signal P from the inverter circuit 85 becomes "L", the p-channel MOS transistor 8
91 is turned on, and output node 894 is charged relatively gently via transistor 891. The signal on output node 894 is applied to AND circuit 90 in the next stage. The signal potential on the output node 894 is A in the next stage.
When the input logic threshold value of the ND circuit 90 is exceeded, the AND circuit 90 outputs a signal of "H". Therefore,
As shown in FIG. 18B, the time required for the output of the AND circuit 90 to rise to “H” is set in FIG. 16 by setting the current driving capability of the transistors 890 and 891 to an appropriate value. It can be set to the same time as the delay time given by the delay circuits 87 and 88 shown.

[Modification 2] FIG. 19 is a diagram showing the structure of the control unit of the output circuit of the second modification of the third embodiment.
In FIG. 19, the control unit includes gate circuits 91 and 92 which receive the output permission signal DOT and the output instruction signal OEM.
, A flip-flop 93 set in response to the rise of the output of the gate circuit 91, and a flip-flop 9 set in response to the rise of the output of the gate circuit 92.
4, a delay circuit 95 for delaying a signal on the node N2 for a predetermined time, an output of the delay circuit 95, and a flip-flop 93.
AND circuit 96 that receives the output of the flip-flop 94, the AND circuit 97 that receives the output of the delay circuit 95, the AND circuit 98 that receives the signal on the node N2 and the output of the ADN circuit 96, and the node N2. Signal above and AN
AND circuit 99 that receives the output of D circuit 97 and AND
AND the drive transistor 2ba that discharges the output node 6 to the ground potential level in response to the output of the circuit 98;
It includes a drive transistor 2bb that discharges output node 6 to the level of the ground potential in response to the output of circuit 99.

Gate circuit 91 receives signals DOT and OE.
When both M are "L", an "H" signal is output. Output instruction signal DOT when output permission signal OEM is "L"
Is "L" when invalid data is not output, as shown in FIG. 17 (B). At this time, the gate circuit 91 outputs the "H" signal to set the flip-flop 93, and the Q output of the flip-flop 93 causes the "H" signal to be output.

Gate circuit 92 outputs a signal of "H" when output instruction signal DOT attains "L" while output enable signal OEM is "H". Output enable signal OEM is "H"
At this time, the output instruction signal DOT becomes "L" when the invalid data signal is output. At this time, the gate circuit 92 outputs the signal of "H", sets the flip-flop 94, and the Q output of this flip-flop 94 outputs the signal of "H".

Next, the operation will be briefly described. When the potential on output node N2 becomes "H", drive transistor 2a is turned on, and output node 6 is gently discharged. When a predetermined time has elapsed, the output of the delay circuit 95 becomes "H". When there is a possibility that invalid data may be output, the gate circuit 92 sets the flip-flop 94, and outputs a signal of "H" from its Q output. When there is no possibility that invalid data will be output, the gate circuit 91 sets the flip-flop 93 to output a signal of "H" from its Q output.

When the output of the delay circuit 95 becomes "H", A
One of the outputs of the ND circuits 96 and 97 becomes "H".
In response, one output of AND circuits 98 and 99 is "H".
Becomes

The current drivability of drive transistor 2ba is larger than that of drive transistor 2bb. Therefore, when invalid data is not output, drive transistor 2ba is turned on by flip-flop 93 and AND circuits 96 and 98, and the potential of output node 6 is discharged at high speed. When the invalid data is not output, the potential amplitude of the output node 6 has already been discharged by the drive transistor 2a, and even if the output node 6 is discharged with a large driving force, ringing does not occur and a stable output signal is output. Can be generated.

When invalid data may be output, flip-flop 94, AND circuits 97 and 99.
Drive transistor 2bb is turned on via. When this invalid data signal may be output, it is considered that the potential of output node 6 has not fallen sufficiently. Therefore, at this time, the output node 6 is
Drive transistor 2b having a relatively small driving force
It is slowly discharged by b. At this time, drive transistors 2a and 2bb are both turned on, and therefore discharge is performed at a higher speed than in the case where output node 6 is driven by one drive transistor. As a result, an output signal can be stably generated without ringing.

In the static column operation mode, when signal OEM is at "H", output instruction signal DOT
Becomes "L". If invalid data may be output first, the flip-flop 93 is set,
In the static column operation mode, it is continuously set. Flip-flops 93 and 94 are reset in response to the fall of output enable signal OEM. In the static column mode, flip-flops 93 and 94 are both set, and drive transistors 2ba and 2bb are both turned on. However, in the static column mode, as shown in the first embodiment, the output node 6 is once set to the intermediate potential after the output of the data signal is completed, and the drive transistors 2a, 2ba and 2bb are all turned on. Even if it becomes a state, there is no possibility that ringing will occur.

At this time, the flip-flops 93 and 9
4 may also be configured to be reset by the address transition detection signal φATD. In this case, a logical sum of the inverted signal of the output signal OEM and the address transition detection signal φATD is obtained, and the logical sum output is obtained by the flip-flop 93.
And 94 reset inputs. When the flip-flops 93 and 94 are reset according to the column address transition detection signal φATD in this manner, the flip-flop 94 is operated in the static column mode operation.
Is set, and drive transistors 2a and 2bb are set.
Thus, discharging of output node 6 is executed.

Since output node 6 is discharged from the intermediate potential to the ground potential level, two drive transistors 2
Even if the output node 6 is driven by only a and 2bb,
Output node 6 can be discharged to the ground potential level at a sufficiently high speed.

In the configuration shown in FIG. 19, AND
The circuit 96 outputs the output signal of the delay circuit 95 and the NAND circuit 86.
When the AND circuit 97 is configured to receive the output signal of the delay circuit 95 and the output signal of the inverter 85 (see FIG. 16), the same effect can be obtained.

[Modification 3] FIG. 20 shows a third modification of the output circuit of the third embodiment. FIG. 20 shows a structure of a portion of NAND circuit 89 and delay circuits 87a and 88 shown in FIG. 20, delay circuit 87a includes a delay circuit 87a for delaying a signal applied from inverter 85 to node N27, and a delay circuit 87a.
A delay circuit 88 for delaying 29 (output of NAND circuit 86) by a predetermined time is included. The delay circuit 87a includes three stages of cascade-connected inverter circuits 871 to 873 and a delay circuit 88.
Of the inverter circuit 873 is received at one input, and the output of the inverter circuit 873 is received at the other input. The gate circuit 874 outputs a signal of "H" when the output of the inverter circuit 873 is "L" and the output of the delay circuit 88 is "H". The outputs of the delay circuits 87a and 88 are N
It is applied to AND circuit 89. The output of NAND circuit 89 is applied to AND circuit 90. The AND circuit 90 has the potential on the node N2 at "H" and the NAND circuit 8
When the output of 9 is "H", the drive transistor 2b
Is turned on.

FIG. 21 shows a NAND circuit 89 shown in FIG.
It is a figure which shows the structure of. In FIG. 21, NAND circuit 89 has a gate receiving the signal potential on node N40.
Channel MOS transistors 89a and 89c and p channel M receiving at its gate the signal potential on node N41.
It includes an OS transistor 89b and an n-channel MOS transistor 89d. Transistors 89a and 89b
Are provided in parallel with each other between the power supply potential node and the output node N30. Transistors 89c and 89d
Are connected in series between the output node N30 and the ground potential. The transistors 89a and 89b may have the same size, and the size (channel width) of the transistor 89b may be larger than that of the transistor 89a. The operation of the circuits shown in FIGS. 20 and 21 will now be described with reference to the operation waveform diagram of FIG.

When the invalid output is present, the potential level of node N29 is "H", and accordingly the signal potential on node N41 is also "H". In this case, the gate circuit 874 included in the delay circuit 87a functions as an inverter circuit. Therefore, when the signal potential on the node N27 becomes "L", the potential of the node N40 becomes "L" after a lapse of a predetermined time.
Becomes At this time, as shown in FIG. 21, in the NAND circuit 89, the p-channel MOS transistor 89a is formed.
Since only the transistor 89a is turned on, the output node N30 is charged only through the transistor 89a. Therefore, the potential rise of node N30 becomes relatively gradual. When the potential level of the node N30 exceeds the input logic threshold value of the AND circuit 90, the potential of the node N2 is at “H”, so the output of the AND circuit 90 becomes “H” (node N3
Potential of 1).

On the other hand, when there is no invalid output, the potential on node N27 is "H", and gate circuit 874 functions as a buffer circuit at this time. Node N29
When the potential of the node N41 becomes "L", the potential on the node N41 becomes "L" after a lapse of a predetermined time by the delay circuit 88, and the output of the gate circuit 874 becomes "L". NAND circuit 89
, P channel MOS transistors 89a and 89b are both turned on, and output node N30
Is charged by these two transistors 89a and 89b, and its potential rises. When the potential of the node N30 exceeds the input logic threshold value of the AND circuit 90, AND
The circuit 90 outputs an "H" signal on the node N31.

The rise of the signal potential on node N30 is relatively gentle when there is an invalid output, and relatively fast when there is no invalid output. As a result, the rise time of the signal potential on node N31 can be made different, and the ON timing of output drive transistor 2b can be made different depending on whether there is an invalid output or not. At this time, if the input / output response characteristic of the AND circuit 90 is comparatively gentle, the rise of the signal potential on the node N31 is similar to that of the node N30, and the output drive transistor 2b
When the invalid output is present, the driving force is gradually increased, and when the invalid output is not present, the driving force is rapidly increased. Thus, output node 6 can be discharged at high speed when ringing is unlikely to occur.

[Embodiment 4] FIG. 23 is a diagram showing a structure of a control portion of an output circuit of a fourth embodiment. FIG. 23 also shows a circuit configuration for discharging output signal Q to the ground potential level.

In FIG. 23, the output circuit includes an AND circuit 3 receiving an output enable signal OEM and an output of inverter circuit 5 receiving internal read data signal ZDD, and an AND circuit receiving an internal read data signal ZDD and output enable signal OEM. 4 and drive transistor 1 which conducts in response to the output of AND circuit 3 to charge output node 6 to the power supply potential Vcc level, and output node 6 to ground potential level in response to the output of AND circuit 4. It includes a drive transistor 2a for discharging and a drive transistor 2b provided in parallel with drive transistor 2a for discharging output node 6 to the ground potential level in response to a control signal from control circuit 100.

Control circuit 100 includes an inverter circuit 81 for inverting the logic of the signal on node N2 (output of AND circuit 4), the signal potential on node N2 and inverter circuit 8.
AND circuit 101 receiving the output of 1 and the output instruction signal D
An inverter circuit 102 for inverting the logic of OT and an AND
A NAND circuit 103 that receives the output of the circuit 101 and the output of the inverter circuit 102; a NAND circuit 104 that receives the output of the AND circuit 101 and the output instruction signal DOT;
It includes a latch circuit 105 receiving an output of ND circuit 103 and a signal on node N2, and a latch circuit 106 receiving an output of NAND circuit 104 and a signal on node N2.

The latch circuit 105 is the NAND circuit 103.
NAND circuit NA5 which receives at one input the output of the above, and NAND circuit NA6 which receives at one input the signal on the node N2
including. The output of the NAND circuit NA6 is the NAND circuit NA.
5 to the other input. The output of NAND circuit NA5 is applied to the other input of NAND circuit NA6. Latch circuit 106 also includes cross-coupled NAND circuits NA7 and NA8. The NAND circuit NA7 receives the output of the NAND circuit 104 at one input and the N input at the other input.
It receives the output of AND circuit NA8. NAND circuit NA8
Receives the signal on node N2 at one input and the output of NAND circuit NA7 at the other input.

The output control circuit 100 further outputs the output of the NAND circuit NA5 of the flip-flop 105 (node N4
6 signal) and a NAN of the flip-flop 106, and a delay stage 107 for delaying its logic for a predetermined time and inverting its logic.
Delay circuit 108 delaying the output of D circuit NA7 for a predetermined time and inverting its logic, and delay circuits 107 and 1
AND circuit 9 receiving the output of NAND circuit 89 and the signal on node N2 and the output of NAND circuit 89
Including 0. The output of AND circuit 90 is applied to the gate of drive transistor 2b.

The delay time of the delay circuit 107 is the delay circuit 10
It is set longer than the delay time of eight. Next, the operation of the circuit shown in FIG. 23 will be described with reference to the operation waveform diagram of FIG.

First, the operation when an invalid data signal is output will be described with reference to FIG. In this case, the invalid data signal is "L" and the valid data signal is "H". In the initial state, output enable signal OEM is at "L" and output instruction signal DOT is at "H". Even if output enable signal OEM rises to "H", internal read data signal ZDD is at "L" and the potential of node N2 is at "L" at that time.

In this state, when the output instruction signal DOT falls to "L", the potential of the node N43 becomes "H" by the inverter circuit 102, and the NAND circuit 103.
Functions as an inverter during this time. NAND circuit 10
4, the output of the AND circuit 101 is “L”,
The state of "H" is maintained.

When valid data signal ZDD is applied to internal data bus line 915b, the potential of node N2 accordingly rises to "H". As a result, the output of the inverter circuit 81 becomes "L". Due to the delay time of the inverter circuit 81, the AND circuit 101 outputs an "H" pulse signal having a delay time width given by the inverter circuit 81. Is generated.

In response to the one-shot pulse signal from AND circuit 101, one-shot "L" pulse signal is generated from NAND circuit 103 on node N45. As a result, in the latch circuit 105,
The output of the NAND circuit NA5 becomes "H", and the node N4
The potential of 6 is set to "H".

Even if a one-shot "H" pulse signal is generated on node N44, output instruction signal DOT is generated during this period.
Is "L", and the latched state of the latch circuit 106 does not change (the output of the NAND circuit 104 maintains "H"). That is, the node N49 (N of the latch circuit 106 is
The output of the AND circuit NA7) is fixed to "L". The output of the delay circuit 108 is “H”, and the NAND circuit 89 functions as an inverter circuit.

When the delay time of the delay circuit 107 elapses, the delay circuit 107 outputs a signal of "L" and N
The output of the AND circuit 89 becomes "H". Next, since the potential of the node N2 is "H", the output of the AND circuit 90 (the signal potential on the node N31) becomes "H", and the drive transistor 2b is turned on. That is, when the invalid data signal is output, the drive transistor 2b is turned on after the drive transistor 2a is turned on and the delay time T1 of the delay circuit 107 elapses.
Turns on. As a result, when the invalid data signal and the valid data signal have different logics, the drive transistor 2b is turned on when the potential of the output node 6 is sufficiently lowered to reach a level at which ringing does not occur.

Next, the operation when invalid data is not output will be described with reference to FIG. In this state, first, the output instruction signal DOT is "L" for a predetermined period.
Becomes In response to the output instruction signal DOT, the output of the inverter circuit 102 is "H" for a predetermined period. However, at this time, the potential of the node N2 is "L", and A
The output of the ND circuit 101 is "L". Therefore, N
The outputs of the AND circuits 103 and 104 maintain "H".

While output instruction signal DOT is at "L", valid data is transmitted onto internal data bus line 915b and internal data signal ZDD attains "H". After the output instruction signal DOT becomes “H”, the output permission signal OE
M becomes "H", and the potential of the node N2 becomes "H".

In response to the rise of the potential of the node N2,
A one-shot "H" pulse signal is generated from AND circuit 101 on node N44. At this time, the output instruction signal DOT has already returned to "H", and the output of the inverter circuit 102 is "L". Therefore, NAN
The output of the D circuit 103 maintains "H".

On the other hand, the NAND circuit 104 uses this AND
In response to the one-shot "H" pulse signal from the circuit 101, an "L" pulse signal is generated. As a result, the output of the NAND circuit NA7 of the latch circuit 106 rises from "L" to "H". This NAND circuit NA7
In response to the transition of the output (the signal potential on the node N49) to "H", the output of the NAND circuit NA8 falls to "L", and the potential of the node N49 is latched to "L".

After the delay time T2 of delay circuit 108 has elapsed, the output of delay circuit 108 rises to "H".

The potential of the node N46 is "L", and the output of the delay circuit 107 is "H". Therefore, NAN
The output of D circuit 89 rises to "H" in response to the output of delay circuit 108, and then the output of AND circuit 90 rises to "H". Drive transistor 2b is AND
It conducts in response to the output of circuit 90, discharging output node 6 to the ground potential level.

As described above, when the invalid data signal is not output, drive transistor 2b is turned on after the delay time of delay circuit 108 has elapsed. The delay time of the delay circuit 108 is the delay circuit 1
It is shorter than the delay time of 07. Therefore, when the invalid data signal is not output, the drive transistor 2b can be turned on at a faster timing.

As described above, by adjusting the on-timing of drive transistor 2b according to the presence or absence of the generation of the invalid data signal, the ringing can be surely prevented from occurring.

Also in the structure shown in FIG. 23, various modifications can be made as in the first embodiment. Also in the modified example described below, the circuit configuration for pulling up the potential of the output node 6 is further utilized, and the number of inverter stages of the delay circuit is set appropriately, as in the case of the above-described embodiment. It can be corrected.

[Modification 1] FIG. 25 shows a first modification of the fourth embodiment. FIG. 25 also shows a circuit configuration for preventing the occurrence of ringing at the time of discharging output node 6. In FIG. 25, the control circuit 1
00 is an inverter circuit 110 for inverting the signal potential on the node N2, and a signal on the node N2 and the inverter circuit 1
AND circuit 111 that receives the output of 10, an inverter circuit 112 that receives the output instruction signal DOT, and AND circuit 1
N receiving the output of 11 and the output of the inverter circuit 112
An AND circuit 113, a delay circuit 114 for delaying the output of the NAND circuit 113 by a predetermined time T1, and an AND circuit 11
NAND circuit 1 receiving the output of 1 and the output instruction signal DOT
14 and the output of the NAND circuit 118a for a predetermined time T2.
(T2 <T1) Delay circuit 118b that delays, NAND circuit 115 that receives the outputs of delay circuits 118a and 118b, inverter circuit 116 that inverts the output of NAND circuit 115, output of inverter circuit 116 and the signal on node N2 A latch circuit 117 for receiving the signal is included.

The latch circuit 117 has a cross-coupled NA.
It includes ND circuits NA9 and NA10. NAND circuit N
A signal for driving the drive transistor 2b is output from A10. The NAND circuit NA9 receives the signal potential on the node N2 at its one input, and receives the signal potential on the node N2.
10 receives the output of inverter circuit 116 at its one input. The outputs of NAND circuits NA9 and NA10 and the other input are cross-coupled. The operation of the circuit shown in FIG. 25 will now be described with reference to the operation waveform diagram of FIG.

First, with reference to FIG. 26A, the operation when the invalid data signal is output will be described. First, output instruction signal OEM rises to "H". In this state, read data signal ZDD is at "L" and is an invalid data signal. In this state, the potential of the node N2 is "L", the output of the AND circuit 111 is also "L", and the outputs of the NAND circuits 113 and 114 are "H". The NAND circuit 115 outputs a signal of "L" according to the outputs of the delay circuits 118a and 118b, and the inverter circuit 116 outputs a signal of "H". The signal potential of the node N2 is "L", and in the latch circuit 117, the output of the NAND circuit NA9 is "H" and the output of the NAND circuit NA10 is "L".

When output instruction signal DOT is at "L" for a predetermined period, the output of inverter circuit 112 is correspondingly at "H". During the "L" period of the output instruction signal DOT,
Valid data is read, internal read data signal ZDD rises to "H", and accordingly the potential of node N2 rises to "H". In response to the rise of the potential of the node N2, A
The one-shot pulse signal generation circuit including the ND circuit 111 and the inverter circuit 110 generates a one-shot "H" pulse signal on the node N74. N
The AND circuit 113 receives the “H” signal at one input via the inverter circuit 112, and therefore AN
In response to the rise of the output of D circuit 111, the signal of "L" is transmitted onto node N75.

On the other hand, the NAND circuit 114 does not respond to the one-shot pulse signal from the AND circuit 111 and outputs the signal of "H" because the output instruction signal DOT is at "L".

After the delay time T1 of the delay circuit 118a elapses, the output of the delay circuit 118a becomes "L" and the output of the NAND circuit 115 becomes "H" (the output of the delay circuit 115 is "H"). . According to the output of the NAND circuit 115, the inverter circuit 116 outputs the node N77.
A one-shot "L" signal is output above. As a result, the NAND circuit NA10 outputs a signal of "H",
The drive transistor 2b is turned on.

Even if the output of the inverter circuit 116 returns to "H", the NAND circuit NA9 responds to the "H" signal generated from the NAND circuit NA10 in response to the previous one-shot pulse signal. The signal of "L" is output. Therefore, the output of the inverter circuit 116 is "H".
The output of the NAND circuit NA10 maintains "H" even after returning to "1".

When the potential of the node N2 becomes "L", in the latch circuit 117, the output of the NAND circuit NA9 becomes "H", and the NAND circuit NA10 receives the signals of "H" at its both inputs, so that "L". Receive the signal. As a result, the drive transistor 2b is turned off.

As described above, when the invalid data signal is output, the delay circuit 114 having a long delay time determines the timing at which the drive transistor 2b is turned on.

Next, the discharge operation of the output node 6 when invalid data is not output will be described with reference to FIG.

First, the output instruction signal DOT becomes "L" and the output of the inverter circuit 112 becomes "H". At this time,
The signal potential of the node N2 is still "L", the output of the AND circuit 111 is "L", and the output of the NAND circuit 114 is "H" regardless of the change of the output instruction signal DOT.
To maintain. In this state, the outputs of delay circuits 118a and 118b are both "H", the output of NAND circuit 115 is "L", the output of inverter circuit 116 is "H", and the output of NAND circuit NA10 is "L". ”
Is.

The valid data signal is the internal data bus line 915.
b), and internal data signal ZDD rises to "H". After this, the output enable signal OEM becomes "H", and the potential of the node N2 becomes "H". In response to the rise of the signal potential at node N2, AND circuit 111 generates a one-shot "H" pulse signal. At this time,
The output instruction signal DOT is at "H", and the inverter circuit 1
The output of 12 is "L". Therefore, the output of the NAND circuit 113 does not change and is in the “H” state.
One-shot "L" signal is output from NAND circuit 114 onto node N76. After the delay time T2 of the delay circuit 118b elapses, the output of the delay circuit 118b becomes "L" and the output of the NAND circuit 115 becomes "H". In response, the output of inverter circuit 116 becomes "L", and NAND circuit NA10 outputs a signal of "H" on node N78. Drive transistor 2b is turned on in response to the "H" signal on node N78.

When the invalid data signal is not output,
Therefore, due to the delay time of the delay circuit 118b,
The timing when the drive transistor 2b is turned on is determined. When the invalid data signal is not output, even if the drive transistor 2b is turned on, the potential of the output node is sufficiently low, ringing does not occur, and the "L" signal can be output stably.

In the modification shown in FIG. 25, various modifications can be added. [Modification 2] FIG. 27 is a diagram showing the structure of the output circuit control unit of the second modification of the fourth embodiment. In FIG.
The output control circuit 100 uses the internal read data signal ZDD and
A NAND circuit 121 that receives the output of the inverter circuit 5 and the output permission signal OEM, and the output permission signal OEM and NAND
A latch circuit 122 that receives the output of the circuit 121 is included. The latch circuit 122 includes NAND circuits NA11 and NA1.
Including 2. NAND circuit NA11 receives output enable signal OEM at one input and the output of NAND circuit NA12 at the other input. NAND circuit NA12 receives the output of NAND circuit 121 at one input and the output of NAND circuit NA11 at the other input.

Output control circuit 100 further includes an inverter circuit 124 receiving the output of NAND circuit NA12 of latch circuit 122, a delay circuit 123 delaying the signal on node N2 for a predetermined time, an output of inverter circuit 124 and a delay circuit. A NAND circuit 126 that receives the output of 123;
A delay circuit 125 that delays the output of the inverter circuit 124 for a predetermined time T4, a NAND circuit 89 that receives the output of the NAND circuit 126 and the output of the delay circuit 125, and an AND 90 that receives the output of the NAND circuit 89 and the signal on the node N2.
including. From AND circuit 90 to drive transistor 2b
A drive control signal is applied to the gate of. Next, FIG.
The operation of the output control unit shown in FIG. 7 will be described with reference to the operation waveform diagram of FIG. In the output control circuit shown in FIG. 27, output instruction signal DOT is not used.

First, with reference to FIG. 28A, the operation when an invalid output exists will be described. When the invalid data signal is output, output enable signal OEM rises to "H" before the change of internal read data signal ZDD. When the internal read data signal ZDD rises to "H" while the output enable signal OEMT is "H", the node N
The potential of 2 rises to "H" via the AND circuit 4.

On the other hand, internal read data signal ZDD is "H".
Even when the voltage rises, the output of the inverter circuit 5 is at "H" level due to the delay time of the inverter circuit 5.
Therefore, all three inputs of the NAND circuit 121 become "H", and the NAND circuit 121 outputs a signal which becomes "L" during the delay time of the inverter circuit 5.

When the NAND circuit 121 outputs a signal of "L" to the node N82, the output of the NAND circuit NA12 included in the latch circuit 122 becomes "H". The "H" signal applied from the NAND circuit NA12 to the node N84 causes the output of the NAND circuit NA11 to be "L". The output node N8 of the latch circuit 122
The "H" state of No. 4 is held while the output enable signal OEM is "H".

When the potential on node N84 rises to "H", inverter circuit 124 sets the potential of node N85 to "L". The output of the delay circuit 123 is "L" before the output of the inverter circuit 124 falls to "L".
It is in. When the output of the delay circuit 123 becomes "H" in response to the rise of the potential of the node N2, the output of the node N8 has already been reached.
The potential of 5 is "H". Therefore, NAND
The output of the circuit 126 is fixed at "H".

"L" on the node N85 is the delay circuit 125.
When transmitted to one input of the NAND circuit 89 via
The NAND circuit 89 outputs a signal of "H" on the node N30. In response to this, the AND circuit 90 outputs a signal of "H" on the node N31, and the drive transistor 2b is turned on. That is, when the invalid data signal is output, the drive transistor 2b is turned on at the timing determined by the delay time T4 of the delay circuit 125. The delay time of the delay circuit 125 is the delay time T3 of the delay circuit 123.
Is set longer than. Therefore, output node 6
The drive transistor 2b is turned on after the potential of is sufficiently lowered, and ringing can be effectively prevented.

The operation when the invalid data signal is not output will be described with reference to FIG. If the invalid data signal is not output, the internal read data Z
The output enable signal OEM becomes "H" after DD rises to "H" and becomes valid. When the output enable signal OEM becomes "H", the output of the inverter circuit 5 is already "L" and the output of the NAND circuit 121 is "H". Even if internal read data signal ZDD changes from "L" to "H", output enable signal OEM is at "L" in that case. Therefore, the NAND circuit 121 always outputs the "H" signal.

When output enable signal OEM attains "H", the potential of node N2 rises to "H". Latch circuit 122
When the output of the NAND circuit 121 is "H" and the output enable signal OEM is "L", the NAND circuit NA1
1 outputs the signal of "L", and the NAND circuit NA1
A signal of "H" is output from 2. Therefore, NAN
In the D circuit NA11, the potential of the node N84 is at "L" even if the output enable signal OEM rises to "H", and the NAN
The output of the D circuit NA11 is fixed at "H". That is,
The potential of the node N84 is fixed to "L", and the node N85
Is fixed at "H".

After the potential of the node N2 rises from "L" to "H" and the delay time T3 of the delay circuit 123 elapses, the output of the delay circuit 123 becomes "H" and the NAND
The output of the circuit 126 becomes "L". Although the output of the delay circuit 125 is fixed to "H", this NAND circuit 12
In response to the "L" signal transmitted from 6 to node N86, the output of NAND circuit 89 rises to "H", and correspondingly the output of AND circuit 90 rises to "H". That is, when the invalid data signal is not output, the delay time T3 of the delay circuit 123 determines the timing at which the drive transistor 2b is turned on. The drive transistor 2b is turned on in a relatively short period after the output of the valid data signal. In this case, the output node 6 is discharged from the intermediate potential, for example, and the potential level is sufficiently lowered. Therefore, even if the drive transistor 2b is turned on, no ringing occurs and a stable output signal can be obtained.

Also in the structure of the output control circuit of the second modification shown in FIG. 27, a structure for pulling up the output signal may be used as in the first modification, and other similar structures are also possible. May be modified.

[Modification 3] FIG. 29 shows a structure of a third modification of the fourth embodiment. Also in FIG. 29,
The structure of an output control circuit for discharging output node 6 to the ground potential level is shown.

In FIG. 29, the output control circuit 100 is
An output enable signal OEM, an internal read data signal ZDD,
NAND circuit 130 receiving the output of the inverter circuit 5
A delay circuit 131 for delaying the signal potential on the node N2 for a predetermined time, an output enable signal OEM and a NAND circuit 130.
Latch circuit 132 for receiving the output of. Latch circuit 1
32 is a cross-coupled NAND circuit NA13 and N
Including A14. NAND circuit NA13 receives output enable signal OEM at one input and the output of NAND circuit N14 at the other input. NAND circuit NA14 receives the output of NAND circuit 130 at one input and the output of NAND circuit NA13 at the other input.

Output control circuit 100 further includes a NAND circuit 134 receiving the output of delay circuit 131 and the output of NAND circuit NA14 included in latch circuit 132, and an inverter receiving the signal output from latch circuit 132 to node N95. A circuit 133 and a NAND circuit 13 that receives the output of the inverter circuit 133 and the output of the delay circuit 131.
5, a delay circuit 136 that delays the output of the NAND circuit 134 for a predetermined time T1, a delay circuit 137 that delays the output of the NAND circuit 135 for a predetermined time T2, and a delay circuit 136.
And a NAND circuit 139 for receiving the outputs of 137 and N
It includes an AND circuit 90 receiving the output of AND circuit 89 and the signal potential on node N2. A signal is applied from AND circuit 90 to the gate of drive transistor 2b. Next, the operation of the output control circuit shown in FIG. 29 will be described with reference to the operation waveform diagram of FIG.

First, the operation when there is an invalid output will be described with reference to FIG. In this case, first, when the internal read data signal ZDD is "L", the output enable signal OE
M rises to "H". In this state, the output of the NAND circuit 130 (signal potential on the node N92) is "H".
It is in.

When the valid data signal is transmitted and internal read data signal ZDD rises to "H", the potential of node N2 rises to "H". At this time, the inverter circuit 5
The NAND circuit 130 outputs a one-shot “L” signal depending on the delay time of the NAND circuit 130. As a result, in latch circuit 132, the output of NAND circuit NA14 rises to "H", the signals of both inputs of NAND circuit NA13 both become "H", and the potential of node N94 falls to "L". The latched state of the latch circuit 132 is maintained while the output enable signal OEM is "H".

After the delay time of delay circuit 131 elapses after the potential of node N2 rises to "H", the potential of node N93 rises to "H". The potential of the node N95 is at "H", and the NAND circuit 134 outputs the node N
A signal of "L" is output on 97.

On the other hand, the NAND circuit 135 is connected to the node N9.
Since the potential of 6 is set to "L" by the inverter circuit 133, the state of "H" is maintained. Therefore,
The output of the delay circuit 137 does not change and maintains the "H" state.

After the delay time T1 of the delay circuit 136 has elapsed, the output of the delay circuit 136 becomes "L",
The NAND circuit 89 outputs a signal of “H” to the node N30. As a result, the output of the AND circuit 90 is "H".
(The potential of the node N2 is already at “H”). In response to the "H" signal on node N31, drive transistor 2b is turned on, and output node 6 is discharged at high speed.

Next, with reference to FIG. 30B, the operation in the case where the invalid data signal is not output will be described. In this case, output enable signal OEM becomes "H" after internal read data signal ZDD becomes "H". Therefore, the output of the NAND circuit 130 is fixed at "H", and the latch circuit 130 maintains the initial state. In the initial state, the latch circuit 132 outputs the output enable signal OEM.
Is at "L", the NAND circuit NA14
The signal of “L” is output to 95. Therefore, inverter circuit 133 always outputs a signal of "H" on node N96.

After the delay time of the delay circuit 131 elapses after the potential of the node N92 rises to "H",
The potential of the node N93 rises to "H". Node N95
Is at "L", and the potential of the node N96 is at "H". Therefore, when the potential of the node N93 rises to "H", it goes from the NAND circuit 135 to the node N98 at "L".
Signal is output. When the delay time T2 of the delay circuit 137 elapses, the output of the delay circuit 137 rises to "H". As a result, the NAND circuit 89 is connected to the node N3.
"H" signal is output to 0, and A on node N31
The ND circuit 90 outputs a signal of "H", and the drive transistor 2b is turned on.

That is, when an invalid data signal may be output, the delay time of delay circuits 131 and 136 determines the timing at which drive transistor 2b is turned on. When the invalid data signal is not output, the delay circuit 131 and the delay circuit 13
Due to the delay time of 7 the drive transistor 2b
The timing for turning on is determined. As a result, the drive transistor 2b can be turned on at the optimum timing depending on whether or not the invalid data signal is output, and the output signal can be stably output without causing ringing.

In the output control circuit shown in FIG. 29, various modifications can be made as in the first modification.

[Modification 4] FIG. 31 shows a fourth modification of the output control circuit according to the fourth embodiment. Figure 31
At output control circuit 100, in response to rising of the signal potential on node N2, inverter control circuit 110 and AND circuit 111 for generating a one-shot "H" pulse signal, output instruction signal DOT and AND A NAND circuit 141 that receives the output of the circuit 111 and a node N
2 and a latch circuit 142 that receives the output of NAND circuit 141. Latch circuit 142 includes NAND circuits NA15 and NA16. NAND circuit NA15
Receives the output of the NAND circuit 141 at its one input,
The other input receives the output signal of NAND circuit NA16. The NAND circuit NA16 has a node N at one input.
It receives the signal potential above 2 and the output of NAND circuit NA15 at the other input.

Output control circuit 100 further includes a delay circuit 143 receiving an output of NAND circuit NA15 of latch circuit 142 and a delay circuit 14 receiving a signal on node N2.
6 and an AN receiving the outputs of delay circuits 146 and 143.
D circuit 144, inverter 147 that inverts the signal on node N2, output of inverter 147, and NOR circuit 1
Including 45. A drive control signal is applied from NOR circuit 145 to the gate of drive transistor 2b via node N31.

Delay circuits 143 and 146 delay the applied signal for a prescribed time and invert the logic thereof. The inverter circuit 147 also has a function as a delay circuit.

The operation of the output control circuit shown in FIG. 31 will now be described with reference to the operation waveform diagram of FIG.

First, the operation when an invalid data signal is output will be described with reference to FIG.

First, output enable signal OEM rises to "H". In this state, internal read data signal ZDD is at "L", and the potential of node N2 is at "L" without change.

When output enable signal DOT falls to "L", a valid data signal of "H" is transmitted onto internal read data line 915b after a lapse of a predetermined time. According to the internal read data signal ZDD of "H", the potential of node N2 rises to "H". In response to the rise of the potential of node N2, AND circuit 111 outputs a one-shot "H" signal. The pulse width of the one-shot pulse signal output from the AND circuit 111 is determined by the delay time of the inverter circuit 110.

When this one-shot pulse signal is generated from AND circuit 111, output instruction signal DOT is still at "L" and the output of NAND circuit 141 is fixed at "H". In the latch circuit 142, the node N2 is at "L" in the initial state, and the NAND circuit NA1
An "H" signal is output from 6 and NAND
The circuit NA15 outputs a signal of "L". Therefore, even if the potential of the node N2 rises to "H",
The signal applied from NAND circuit NA16 to node N106 is at "H" and does not change. That is, the latch state of the latch circuit 142 does not change at all, and the node N105
Is fixed at "L".

When the potential of the node N2 rises to "H",
After the delay time of the inverter 147 has elapsed, the inverter circuit 147 outputs a signal of "L" to the node N107. The AND circuit 144 receives the “H” signal from the delay circuit 143. Therefore, after the delay time of the delay circuit 146 elapses after the potential of the node N2 rises to "H", the potential of the node N108 becomes "L" and the output of the AND circuit 144 becomes "L". NOR circuit 145 receives the signal of "L" at its both inputs and raises the potential of node N31. At this time, as will be described later, the NOR circuit 145 and the AND circuit 144 form a composite gate, and at the output portion, only one p-channel MOS transistor is turned on. As a result, the potential of the node N31 gradually rises and the driving force of the drive transistor 2b is gradually increased. As a result, the potential drop at output node 6 is moderated. As a result, even when the invalid signal is output, the driving force of the drive transistor 2b is increased only after a sufficient time has elapsed, and a stable "L" signal is generated without ringing. Can be output.

Next, the operation when invalid data is not output will be described with reference to FIG.

First, output instruction signal DOT is generated. Valid data signal ZDD in response to this output instruction signal DOT
Rises to "H". In this state, the potential of the node N2 is "L".

After output instructing signal DOT rises to "H", output enable signal OEM rises to "H" and the potential of node N2 rises to "H". When the potential of the node N2 rises to "H", the AND circuit 111 generates a "H" one-shot pulse signal by the delay function of the inverter circuit 110. "H" from AND circuit 111
NAND circuit 1 in response to the one-shot pulse signal of
A one-shot "L" pulse signal is generated from 41 to the node N104 (the signal DOT is already at "H"). In response to the "L" signal on node N104, the output of NAND circuit NA15 of latch circuit 142 rises to "H". NAND circuit NA15 to node N
In response to the “H” signal applied to 105, the NAND circuit NA16 outputs the “L” signal to the node N106.
This state is maintained while the potential of the node N2 is "H".

On the other hand, in response to the rise of the potential of the node N2, the output of the inverter circuit 147 becomes "L", and N
The output of the OR circuit 145 gradually rises. Then, the output of delay circuit 146 falls to "L" after the delay time has elapsed in response to the rise of the signal on node N2, and AND circuit 1
The output of 44 becomes "L". The output of the delay circuit 143 falls to "L". As a result, in the composite gate composed of the AND circuit 144 and the NOR circuit 145, at least two p-channel MOS transistors are turned on, and unlike the case where an invalid data signal is output, the potential of the node N31 is raised with a large driving force. The drive transistor 2b is turned on at a relatively early timing after the valid data signal appears on the node N2, and the output node 6 is discharged with a strong driving force. As a result, the potential of output node 6 falls at high speed.

As described above, the drive transistor 2b
The gate for controlling the potential of the gate of is composed of a composite gate, and the number of charge transistors that are turned on among the transistors of this composite gate is made different according to the presence or absence of invalid data output, so that the output node 6 can be set at an optimum timing. It can be discharged to ground potential level.

FIG. 33 shows the AND circuit and NO shown in FIG.
It is a figure which shows the concrete structure of the composite gate of R circuit. Figure 3
3, the AND circuit 144 and the NOR circuit 14
5 is connected in series between the power supply potential supply node and the output node N31 and has its gate connected to the node N
P channel MOS transistors 151 and 152 connected to 107 and N109, and p channel MOS transistors 153 connected in series between the power supply potential supply node and node N31 and having their gates connected to nodes N107 and N108, respectively. 154, an n-channel MOS connected between the output node N31 and the ground potential node and having its gate connected to the node N107.
The transistor 155 is connected in series between the node N31 and the ground potential node, and has its gate connected to the node N108.
And n-channel MOS transistors 156 and 157 receiving the potential of N109.

In the structure of the composite gate shown in FIG. 33, NOR circuit 145 functions as an inverter circuit when the potential of node N107 is "L". When the potential of node N107 is "L", transistors 151 and 153 are on and transistor 155 is off in FIG. When the potential of the node N108 is “L”, the transistor 154 is turned on. Therefore, when the invalid data signal may be output, the output node N31 is connected to the transistor 15
Only charged via 3 and 154. At this time, the transistor 156 is off, there is no discharge path, and the potential of the node N31 gradually rises.

On the other hand, when the potentials of nodes N108 and N109 are both "L", the potential of node N107 is "L", so that node N31 is charged via transistors 151 and 152 and further transistors 153 and 154 are connected. Node N31 is charged via At this time, discharging transistors 155, 156, and 157 are all in the off state, so that node N31 is charged at a relatively high speed and its potential rises at a high speed.

When the potential of the node N107 becomes "H",
The transistor 155 is turned on, and the node N31
Is discharged through the transistor 155 and its potential becomes “L”. At this time, the transistors 151 and 153 are off.

By using the composite gate as shown in FIG. 33 described above, the rising speed of the potential of the gate of the drive transistor 2b, that is, the node N31 can be switched depending on whether the invalid data signal is output or not, and the drive is performed at the optimum timing. The driving force of the transistor 2b can be increased.

In the structure of the composite gate shown in FIG. 33,
P-channel MOS transistors 151 and 153 may be shared and may be configured by one p-channel MOS transistor. Also in the output control circuit shown in FIG. 31, various modifications can be added as in the previous embodiment.

[Modification 5] FIG. 34 shows a structure of an output circuit according to a fifth modification of the fourth embodiment. Figure 3
4, the output circuit includes a delay circuit 161 that delays the output enable signal OEM for a predetermined time T5, an inverter circuit 5 that inverts the internal read data signal ZDD, and a delay circuit 16.
AND circuit 3 receiving the output of 1 and the output of inverter circuit 5, output enable signal OEM and internal read data signal ZD
Responsive to the output of the AND circuit 4, which receives D, the drive transistor 1 formed of an n channel MOS transistor which conducts in response to the output of the AND circuit 3 and charges the output node 6 to the power supply potential Vcc level, and the output of the AND circuit 4. Drive transistor 2a formed of an n-channel MOS transistor which is turned on and discharges output node 6 to the ground potential level.

The output circuit further includes a delay circuit 160 for delaying the output of the AND circuit 4 by a predetermined time T6, and a node N2.
AND circuit 90 which receives the signal (output of AND circuit 4) and the output of delay circuit 160. The output of AND circuit 90 is applied to the gate of drive transistor 2b.
The current drivability of drive transistor 2b is made larger than the current drivability of drive transistor 2a. The operation of the output circuit shown in FIG. 34 will now be described with reference to the operation waveform diagrams of FIGS. 35 and 36.

First, the operation in the case where the invalid data signal is not output will be described with reference to FIG. When the invalid data signal is not output, the internal read data signal Z
The output rise signal "H" rises after DD rises to "H". In response to the rise of output enable signal OEM, AND circuit 4 outputs a signal of "H" to node N2. In response to the rise of the potential of node N2, drive transistor 2a is turned on and output node 6
The potential of is slowly discharged to the ground potential level.

Next, the delay time T of the delay circuit 160
After 6 has elapsed, the output of the delay circuit 160 becomes "H" and the output of the AND circuit 90 becomes "H". As a result, drive transistor 2b is turned on, and the potential of output node 6 is discharged at high speed to the ground potential level.
When the drive transistor 2b is turned on, the potential of the output node 6 is sufficiently low, and even if the drive transistor 2b discharges the potential of the output node 6 at high speed, ringing does not occur and a stable output signal is generated. Obtainable.

Here, the node N1 outputs the output enable signal OEM.
Rises to "H", the internal read data signal ZDD is already at "H" at that time, so that it always holds the potential of "L" and the drive transistor 1 is in the off state.

Next, the operation when the invalid data signal is output will be described with reference to FIG. When the invalid data signal is output, output enable signal OEM rises to "H". At this time, the internal read data signal Z
DD is at "L". Therefore, the output of the inverter circuit 5 is at "H". After the delay time T5 of the delay circuit 161 elapses after the output enable signal OEM rises to "H", the output of the AND circuit 3 (potential of the node N1) rises to "H" and the drive transistor 1 is turned on. And the output node 6 is charged.

Then, when the valid data signal is transmitted and internal read data signal ZDD rises to "H", the output of inverter circuit 5 attains "L". As a result, the output of the AND circuit 3 (potential of the node N1) becomes "L", and the drive transistor 1 is turned off. On the other hand, in response to the change of the internal read data signal ZDD to "H", the AN
The output of the D circuit 4 (potential of the node N2) rises to "H", and the drive transistor 2a is turned on. As a result, the potential of output node 6 is gently discharged to the ground potential level.

After the delay time T6 of delay circuit 160 has elapsed, the output of delay circuit 160 rises to "H" and the output of AND circuit 90 rises to "H". As a result, drive transistor 2b is turned on, and the potential of output node 6 is discharged at high speed to the ground potential level.

When this invalid data signal is output, the time during which the invalid data signal appears at output node 6 is shortened by delay time T5 of delay circuit 161. Therefore, the time when the invalid data signal appears on output node 6 is shortened, and the amount of change in potential of output node 6 due to the invalid data signal can be reduced. As a result, after the drive transistor 2a is turned on and the potential of the output node 6 is discharged, when the drive transistor 2b is turned on, the potential of the output node 6 is made sufficiently low, and ringing is effectively generated. It is possible to obtain a stable output signal.

Until the internal read data signal ZDD becomes "H" in the valid state, the AND circuit 3 supplies "H" to the node N1.
If the delay time T5 of the delay circuit 161 is set so that the above signal is not output, it is possible to prevent the invalid data signal from being output.

In the structure shown in FIG. 34, when the invalid data signal is not output (see FIG. 35A), the potential of the node N1 becomes "H" after the output enable signal OEM becomes "H". The delay time T5 of the delay circuit 161
Just delayed. Therefore, in this case, only the access time of the "H" output is delayed. The access time is determined by the "L" output time, and when the "H" access time is shorter than the "L" access time, the deterioration of the access time can be prevented.

The structure shown in FIG. 34 shows a structure in which output node 6 is discharged to the ground potential level. However, also in the configuration shown in FIG. 34, a configuration similar to that of the delay circuit 151 is provided for the AND circuit 4,
The delay circuit 160 and the AND circuit 90 are connected to the node N1.
By providing a drive transistor having a larger driving force than that of the drive transistor 1 in parallel with the drive transistor 1, it is possible to prevent ringing from occurring when the potential of the output node 6 rises.

Delay circuits 161 and 1 shown in FIG.
The number of inverters 60 may be set to an appropriate value. Further, delay circuits 160 and 161 may be realized by delay elements other than the inverter.

[Modification 6] FIG. 36 shows a structure of an output circuit according to a sixth modification of the fourth embodiment. Figure 3
6, the output circuit includes an inverter circuit 5 for inverting internal read data signal ZDD, an AND circuit 3 for receiving output enable signal OEM and the output of inverter circuit 5, and an output circuit for receiving output enable signal OEM and internal read data signal ZDD.
It includes a D circuit 4, a delay circuit 160a that delays the output permission signal OEM for a predetermined time Ta, and a delay circuit that delays the output of the AND circuit 4 for a predetermined time Tb. Delay circuit 160a
Has a delay time Ta shorter than the delay time Tb of the delay circuit 160b. Delay time Ta included in delay circuit 160a is set to a time width that prevents an invalid data signal from appearing at node N2 during "L" data reading. The delay time Ta of this delay circuit 160a
Is therefore set to, for example, the maximum value of the specification value of the time required from the change of the column address signal to the fall of column address strobe signal ZCAS to "L". This can prevent the invalid data signal from being transmitted to the node N2. Next, the operation of the circuit shown in FIG. 36 will be described.

First, referring to the operation waveform diagram of FIG. 37,
The operation when the "H" data signal Q is output will be described.

In this case, internal read data signal ZDD is at "L" (internal read data signal ZDD is once precharged to "L" during standby or before data read operation). In this state, the output permission signal OEM
Rises to "H", AND gate 3 outputs a signal of "H" on node N1. In response to the rise of the potential on node N1, drive transistor 1a is turned on. The current driving capability of the drive transistor 1a is relatively small. As a result, output node 6 is gently charged through drive transistor 1a.

Next, after the delay time Ta of the delay circuit 160a has elapsed, the output of the delay circuit 160a is "H".
And the output of the AND circuit 90a rises to "H". As a result, the drive transistor 1a is turned on. The drive transistor 1b has a sufficiently large current drivability. As a result, output node 6 is charged at high speed by drive transistor 1b, and its potential rises rapidly.

Next, with reference to FIG. 38, an operation when an invalid data signal is output at the time of outputting "L" data will be described. In this case, the output enable signal OEM first rises to "H". At this time, the internal read data signal ZDD
Is at "L" and the output of the inverter circuit 5 is at "H". Therefore, in response to the rise of output enable signal OEM, AND circuit 3 outputs a signal of "H" to node N1. In response to the rise of the signal potential on node N1, drive transistor 1a having a small current driving capability is turned on, and the potential of output node 6 is gradually raised.

When the valid data signal is transmitted and internal read data signal ZDD rises to "H", the output of AND circuit 3 attains "L" and drive transistor 1a is turned off. Further, in response to the internal read data signal ZDD of "H", AND circuit 4 outputs a signal of "H" to node N2, and drive transistor 2a having a small current driving capability is turned on. As a result, the increased potential of output node 6 is gently discharged to the ground potential level.

Then, when delay time Tb of delay circuit 160b elapses, the output of delay circuit 160b attains "H" (potential of node N30b), and AND circuit 90b outputs the signal of "H" to node N31b. This allows
Drive transistor 2b having a large current driving capability is turned on, and output node 6 is discharged at high speed to the ground potential level.

Even when an invalid data signal is output, first, the drive transistor 1a having a small current driving force is used.
Turns on to charge the output node 6. In this case, drive transistor 1a has a small current driving capability, and therefore the potential increase at output node 6 thereof is very small. Therefore, the potential amplitude of output node 6 can be sufficiently reduced, and ringing can be effectively prevented.

Drive transistor 1b having a large current drivability is kept off because the potential level of node N31a is fixed at "L". Delay circuit 160
This is because the potential of the node N1 has already become "L" when the output of "a" becomes "H".

Next, the operation when the invalid data signal is not output will be described with reference to FIG. In this case, first, internal read data signal ZDD rises to "H". As a result, the potential of the node N1 is fixed at "L".

Then, when the output enable signal OEM rises to "H", the potential of the node N2 rises to "H" via the AND circuit 4. When the predetermined time Ta elapses, the output of the delay circuit 160a rises to "H". However, since the potential of the node N1 is at "L", the AND circuit 90a
Output is "L", and the drive transistor 1b is
The off state is maintained together with the drive transistor 1a.

On the other hand, in response to the rise of the potential of node N2, drive transistor 2a is turned on, and output node 6 is gently discharged. Then, the delay circuit 16
When the output of 0b rises to "H", the potential of the node N31b rises to "H" via the AND circuit 90b, and the drive transistor 2b is turned on. This allows
Output node 6 is rapidly discharged to the ground potential level.
When the drive transistor 2b is turned on,
Already enough output node 6 due to drive transistor 2a
The potential of is low, and an output signal can be stably generated without causing ringing.

In the structure shown in FIG. 36, drive transistors 1a and 1b may be realized by appropriately setting the size or the gate width or the ratio of the gate width and the gate length for the difference in the current driving capability. . Further, a voltage of power supply voltage Vcc level may be applied to drive transistor 1a, and drive transistor 1b may be configured such that a voltage obtained by boosting power supply voltage Vcc is applied to the gate. This drive transistor 1a
The adjustment of the gate voltage of 1 and 1b may be used in combination with the adjustment of the size. The configuration in which the gate voltages are different may be applied to drive transistors 2a and 2b discharging output node 6 to the ground potential level.

In the structure of the output circuit shown in FIG. 36, as in the case of the modification 5 described above, a structure may be used in which the output permission signal OEM is passed through the delay circuit and then applied to the AND circuit 3. In this case, the rise time of the potential of node N1 can be delayed, the time of outputting the invalid data signal can be shortened, and the potential amplitude of output node 6 can be further reduced.

In the structure shown in FIG. 36, the invalid data signal is "L" by providing a circuit structure similar to that shown in the drawing to the drive transistor for raising the potential of output node 6. It is possible to prevent the potential amplitude of output node 6 from expanding when the valid data signal is "H", and to prevent ringing in this case.

[Modification 7] FIG. 40 shows a structure of an output circuit of a seventh modification of the fourth embodiment. Referring to FIG. 40, the output circuit includes an inverter circuit 5 for inverting internal read data signal ZDD, an AND circuit 3 for receiving output instruction signal DOT, an output permission signal OEM, and an output of inverter circuit 5, and an AND circuit 3. And an AND circuit 4 which conducts in response to the output of V.sub.1 and charges output node 6 to the level of power supply potential Vcc, an AND circuit 4 receiving output enable signal OEM and internal read data signal ZDD.
It includes a drive transistor 2a having a relatively small current driving capability that conducts in response to the output of circuit 4 and discharges output node 6 to the ground potential level.

The output circuit further delays the output of the AND circuit 4 (potential of the node N2) by a predetermined time.
60 and an AND circuit 90 receiving the output of delay circuit 160 and the signal of node N2. The output of the AND circuit 90 is given to the gate of the drive transistor 2b having a large current driving force. The operation of the output circuit shown in FIG. 40 will now be described with reference to the operation waveform diagram of FIG.

First, the operation when the invalid output data signal is "H" and the valid data signal is "L" will be described. In this case, before the output instruction signal DOT falls,
Output enable signal OEM rises to "H". Internal read data signal ZDD on internal data bus line 915b is at "L", and the output of inverter circuit 5 is at "H". Therefore, in response to the rise of the output enable signal OEM,
AND circuit 3 outputs a signal of "H" on node N1. Drive transistor 1 is turned on as the potential on node N1 rises. At this time, the output of the AND circuit 4 (potential of the node N2) is "L", and the drive transistors 2a and 2b are off. Therefore, output node 6 is charged through drive transistor 1 and its potential rises.

When output instruction signal DOT falls to "L", the potential of node N1 falls to "L" and drive transistor 1 is turned off. Then, in response to the fall of output instruction signal DOT, internal data bus line 91
The valid data signal ZDD of "H" is transmitted to 5b, and the signal of "L" is output from the inverter circuit 5 to the node N90. As a result, the output of the AND circuit 3, that is, the potential of the node N1 is fixed to "L" during the output of the data ZDD.

When internal read data signal ZDD attains "H", AND circuit 4 outputs a signal of "H" on node N2, and drive transistor 2a is turned on. As a result, output node 6 is gently discharged, and the potential of the output node gradually decreases.

Then, after a lapse of a predetermined time, the output of delay circuit 150 becomes "H", and AND circuit 90 outputs a signal of "H" on node N31. As a result, the drive transistor 2b is turned on and the output node 6
Rapidly discharges to ground potential level.

In the structure shown in FIG. 41, even when the invalid data signal is output, the period in which drive transistor 1 for charging the output node is on is extremely short, and the potential amplitude of output node 6 is reduced. It becomes possible. Further, in the case where the output permission signal OEM becomes “H” after the output instruction signal DOT becomes “L”,
It is possible to completely prevent invalid data from being output. When the valid output data signal is "H", the internal read data signal ZDD is fixed to "L" as shown by the broken line in FIG. In this case, the inverter circuit 5
Is at "H", and the potential of the node N1 rises to "H" when the output instruction signal DOT rises to "H". On the other hand, the output of the AND circuit 4 is "L", and the drive transistors 2a and 2b maintain the off state. Therefore, output node 6 is charged to the level of power supply potential Vcc through drive transistor 1. That is, when the valid output data signal is "H", the output permission signal OE
The drive transistor 1 is turned on in response to the rise of M, then turned off once in response to the transition of the output instruction signal DOT to "L", and then when the output instruction signal DOT becomes "H" again, the drive transistor 1 is turned on. 1 is turned on again.

Next, referring to FIG. 42, the operation in the case where the invalid data signal is not output at the time of reading the "L" output data will be described. In this case, first, the output instruction signal D
OT falls to "L". In this state, internal read data signal ZDD attains "L", and inverter circuit 5
Output (potential of the node N90) is at "H". Since the output enable signal OEM is at "L", the potential of the node N1 is at "L".

A valid data signal is transmitted to internal data bus line 915b a prescribed time after output instruction signal DOT falls to "L", and internal read data signal ZDD rises to "H". As a result, the potential of node N90 falls to "L" and the potential of node N1 is fixed at "L" during the reading of internal read data signal ZDD. At this time, the potential of the node N2 is still at "L" when the output enable signal OEM is "L". When the output enable signal OEM rises to "H", the potential of the node N2 changes to the AND circuit 4
Rise to "H" via. As a result, drive transistor 2a is turned on, and output node 6 is gently discharged to the ground potential level. Then, when a predetermined time elapses, the output of the delay circuit 160 becomes "H", and AN
The output of the D circuit 90 becomes "H". As a result, drive transistor 2b is turned on, and output node 6 is discharged at high speed to the ground potential level. When the drive transistor 2b is turned on, the potential of the output node 6 is sufficiently lowered, and an output signal can be stably output without causing ringing.

In the structure shown in FIG. 40, column address signal change detection signal φATD is used in place of output instruction signal DOT.
, A one-shot pulse signal which becomes "L" at a timing earlier than the output instruction signal DOT may be used. This can be created by using an appropriate delay circuit in the one-shot pulse generation circuit 50 shown in FIG. By using such a signal, the pulse width of the one-shot pulse signal generated in response to the rise of the output signal OEM can be further shortened in the operation waveform diagram shown in FIG.
The output time of the invalid output data signal of "H" can be further shortened, and the potential amplitude of output node 6 can be further reduced.

Further, in response to the column address change detection signal φATD, a signal changing from "H" to "L" is given to the AND circuit 3 at a timing faster than that of the output enable signal OEM changing from "L" to "H". By doing so, the appearance of the invalid data signal at the node N1 can be prevented.
As such a signal, in the configuration shown in FIG. 5, a circuit for generating a one-shot pulse signal which is "L" for a predetermined period in response to the fall of the potential of the output node N14 of the latch circuit is used. Good. The rising edge of the pulse signal may be determined by the falling edge of the output instruction signal DOT. As such a signal generation circuit, an AND circuit receiving the signal on node N14 and output instruction signal DOT shown in FIG. 5 can be used. By using such a configuration, it is possible to reliably prevent the invalid data signal from being output to the node N1.

In the structure shown in FIG. 40, output enable signal OEM may be applied to AND circuit 3 through a delay circuit. In this case, the time period during which the invalid data signal is output to node N1 can be shortened, and the potential amplitude of output node 6 can be reduced. Further, by setting the delay time of this delay circuit to an appropriate value, it is possible to prevent the generation of an invalid data signal at node N1.

[Modification 8] FIG. 43 shows an eighth modification of the output circuit. In the structure shown in FIG. 43, three drive transistors 2a, 2b and 2c for discharging output node 6 are provided. The drive transistors 2a, 2b and 2c have respective gate widths W
Are sequentially different from small, medium and large. That is, the current drivability of each drive transistor 2a, 2b and 2c is made different. The output of the AND circuit 90a is applied to the gate of the drive transistor 2b. AN
The D circuit 90a includes a potential on the node N2 and the delay circuit 160.
and the output of a. The delay circuit 160a delays the potential signal of the node N2 for a predetermined time. This delay circuit 160a
Is also further delayed by delay circuit 160b. The output of the AND circuit 90b is applied to the gate of the drive transistor 2c. AND circuit 90b receives the signal on node N2 and the output of delay circuit 160b.

In the structure of the output circuit shown in FIG. 43, when the potential of node N2 attains "H", drive transistor 2a is first turned on and output node 6 is gently discharged. Then, when a predetermined period elapses, the output of the AND circuit 90a becomes "H", and the drive transistor 2
b is turned on, and output node 6 is further discharged to the ground potential level.

When the predetermined time further elapses, the delay circuit 1
The output of 60b becomes "H", and the output of the AND circuit 90b turns on the drive transistor 2c,
The output node 6 is rapidly discharged to the ground potential level. In this way, three drive transistors for discharging the output node are provided, and by making the timing of turning on each different, it is possible to stably generate the output signal without causing ringing. The structure of the output circuit shown in FIG. 43 can be used in combination with the first to third embodiments.

[Modification 9] FIG. 44 shows a ninth modification of the fourth embodiment. In FIG. 44, a gate circuit 90 for directly driving drive transistor 2b for discharging output node 6 to the ground potential level.
The configuration of is shown. This gate circuit 90 can be used in each embodiment and modification. In FIG. 44, a basic circuit configuration is shown as the configuration of the output circuit.

In FIG. 44, drive transistor 2
a is driven by the NAND circuit 4a and the inverter circuit 4b. The NAND circuit 4a outputs the output enable signal OEM
And internal read data signal ZDD. Inverter circuit 4b receives the output of NAND circuit 4a and transmits a signal of logic corresponding to the internal read data signal onto node N2.

The output circuit further includes a delay circuit 171a for delaying the output of the NAND circuit 4a for a predetermined time and a delay circuit 171b for further delaying the output of the delay circuit 171a.
And a gate circuit 90 for driving drive transistor 2b in accordance with the output of NAND circuit 4a and the outputs of delay circuits 171a and 171b. This gate circuit 90 is
It corresponds to AND circuits 90a and 90b shown in FIG.

Gate circuit 90 includes p channel MOS transistors 172, 173 and 174 provided in parallel between the power supply potential node and internal node 177. The output of the NAND circuit 4a and the delay circuit 1 are connected to the respective gates of the transistors 172, 173 and 174.
The output of 71a and the output of delay circuit 171b are provided.

The gate circuit 90 further includes an internal node 17
7 and an inverter circuit provided between the ground potential and the ground potential. This inverter circuit is provided between output node N31 and internal node 177 and has its gate receiving p channel MOS transistor 17 which receives the output of NAND circuit 4a.
5, n provided between the output node N31 and the ground potential node and receiving the output of the NAND circuit 4a at its gate.
A channel MOS transistor 176 is included. Next, the operation of the gate circuit 90 will be briefly described.

When the potential of the node N2 is "L", NAN
The D circuit 4a outputs a signal of "H". In this state, transistors 172 through 175 are all off and transistor 176 is on.
Therefore, the output node N31 is at "L".

When the output of NAND circuit 4a attains "L", the potential of node N2 attains "H", drive transistor 2a is turned on, and output node 6 is gently discharged by drive transistor 2a. In this state, when the output of the NAND circuit 4a becomes "H",
Transistors 172 and 175 are turned on, and transistor 176b is turned off. Therefore, output node N31 is gently charged through transistors 172 and 175, and the potential thereof gradually rises.
As a result, the driving force of the drive transistor 2b is slightly increased.

Then, when the output of the delay circuit 171a becomes "L", the transistor 173 is turned on, and the node N31 is connected to the transistors 172 and 173 as well as 1
It is charged through 75, its potential rises a little faster, and the driving force of the drive transistor 2b is also increased a little.

When the predetermined time further passes, the output of the delay circuit 171b becomes "L", and the transistor 174 is turned on. As a result, the transistors 172 to 17
A current flows into transistor 175 via transistor 4, the potential of node N31 rises at high speed, and the driving force of drive transistor 2b is rapidly increased.

As described above, by making the rising speed of the output potential of the gate circuit 90 different over time without using the delay circuit, the driving force of the drive transistor 2b also changes over time, and each of the above It is possible to obtain the same effect as that of the embodiment and the modification. As shown in FIG. 44, even if the current drivability of drive transistor 2b is increased with time, the time change rate of the current that causes ringing at output node 6, that is, di / dt
Can be reduced, and ringing can be reliably prevented from occurring.

[Embodiment 5] In the semiconductor device, in order to ensure stable operation, the power supply voltage Vcc has an upper limit value V.
cmx and the lower limit value Vcmn are set. For example, when the operating power supply voltage Vcc is 5V, the upper limit Vcmx is set to 5.5V and the lower limit Vcmn is set to 4.5V in the specifications. Generally, ± 1 of the rated value of the power supply voltage Vcc
The fluctuation of the power supply voltage Vcc within the range of 0% is allowed.

Similarly, an upper limit value Tamx and a lower limit value Tamn are set for the operating temperature Ta. As a range of such operating temperature Ta, 0 to 70 ° C. is specified in the specifications.

On the other hand, in the circuit having the MOS transistor as a constituent element, the operating speed thereof increases as the power supply voltage Vcc increases. This is because the current drivability of the MOS transistor is determined by its gate voltage (gate-source potential difference), and this potential difference is determined by the power supply voltage Vcc.

In the circuit having MOS transistors as its constituent elements, the operating speed becomes higher as the operating temperature Ta becomes lower. This is because the higher the operating temperature, the higher the resistance of the diffusion region, and the higher the threshold voltage due to the influence of thermoelectrons and the like, and the lower the current driving force.

A remarkable example of such circuit characteristics appears in a semiconductor memory device in which the access time ta becomes shorter as the power supply voltage Vcc becomes higher, and the access time becomes longer as the operating temperature becomes higher. ing.

Below, the power supply voltage Vcc and the operating temperature T
A configuration for surely preventing the occurrence of ringing regardless of the variation of a will be described.

FIG. 45 is a diagram showing the characteristics of the first control voltage used in the fifth embodiment. Figure 45
As shown in (a), the first control voltage VN rises as the ambient temperature T rises. That is, the first control voltage VN has a positive temperature coefficient. Further, as shown in FIG. 45 (b), the first control voltage VN decreases as the power supply voltage Vcc increases. That is, the first control voltage VN has a negative dependence on the power supply voltage Vcc.

FIG. 46 shows the temperature and power supply voltage dependence of the second control voltage used in the fifth embodiment. As shown in FIG. 46 (a), the second control voltage VP decreases as the ambient temperature T increases. That is, the second control voltage VP has a negative temperature coefficient. Also, as shown in FIG. 46 (b), the second control voltage VP rises as the power supply voltage Vcc rises. That is, the second control voltage VP has a positive dependence on the power supply voltage Vcc. The delay time of the delay stage is adjusted by using the first and second control voltages VN and VP having mutually opposite voltage and power supply voltage dependence characteristics.

FIG. 47 shows a first structure of an inverter circuit forming a delay stage used in the fifth embodiment. In FIG. 47A, the inverter circuit forming the delay stage is a p-channel MO connected in series between the power supply voltage Vcc supply node and the output node 205.
S transistors 201 and 202 and output node 20
N channel MO provided between the node 5 and the ground potential node
The S transistor 203 is included. A second control voltage VP is applied to the gate of p channel MOS transistor 201. The gates of MOS transistors 202 and 203 are both connected to input node 204. Next, the operating characteristics of the inverter circuit shown in FIG. 47A will be described with reference to FIG.

If the power supply voltage Vcc is at the lower limit value Vcmn or the operating temperature T is at the upper limit temperature Tamx, the second
The control voltage VP of is smaller. Therefore, p
The current drivability of channel MOS transistor 201 is made larger than that under the condition of upper limit value Vcmx of power supply voltage Vcc or lower limit value Tamn of operating temperature T.

When the input signal IN applied to the input node 204 is at a low level, the MOS transistor 202 is on and the MOS transistor 203 is off. Output node 205 has transistors 201 and 2
It is charged through 02 to the power supply voltage Vcc level.
Here, the second control voltage VP is set to a value sufficiently lower than the power supply voltage Vcc, and the transistor 201 is
The power supply voltage Vcc is allowed to pass therethrough. The optimum value of the second control voltage VP is determined according to the actual operating characteristics of the device.

In this state, the power supply voltage Vcc is close to the lower limit value Vcmn or the operating temperature T is the upper limit value Tamx.
, The output node 205 is raised to the high level at high speed (indicated by the broken line in FIG. 47B).

When the input signal IN is at high level, M
OS transistor 203 is turned on, and output node 205 is discharged to the ground potential level. The discharge rate of the output node 205 in this case is determined by the current driving capability of the transistor 203. That is, when the delay stage is formed using the inverter circuit shown in FIG. 47A, the time for transmitting a low-level signal is longer when the upper limit value of power supply voltage Vcc and the ambient temperature are low.

FIG. 48 is a diagram showing another structure and operation characteristics of the inverter circuit forming the delay stage. FIG. 48
In (A), the inverter circuit 210 includes a p-channel MOS transistor 211 provided between a power supply potential node and an output node 215, and an n-channel MOS transistor provided in series between the output node 215 and a ground potential node.
Includes transistors 212 and 213. The input signal IN is applied to the gates of the MOS transistors 211 and 212.
Are provided via input node 214. The first control voltage VN is applied to the gate of the MOS transistor 213. Next, operating characteristics of the inverter circuit illustrated in FIG. 48A will be described with reference to FIG.

First control voltage VN has a negative dependency on power supply potential Vcc and a positive temperature coefficient.
When the input signal IN is at high level, the MOS transistor 212 is turned on. The power supply potential Vcc is the upper limit value Vc
When it is close to mx and when the ambient temperature T is close to the lower limit value Tamn, the first control voltage VN becomes low. Therefore, in this state, the current drivability of MOS transistor 213 is reduced. Here, the first control voltage VN is
It is set to a voltage value sufficiently higher than the threshold voltage of MOS transistor 213. Therefore, when power supply voltage Vcc is high or ambient temperature T is low, output node 215 is discharged relatively slowly as compared to the case where it is not. That is, when a high level signal is transmitted through the delay stage formed by the inverter circuit shown in FIG. 48A, when it is close to the upper limit value Vcmx of the power supply potential Vcc, or when the ambient temperature T is close to the lower limit value Tamn. Has a longer propagation time than otherwise.

FIG. 49 is a diagram showing still another structure and operating characteristics of the inverter circuit forming the delay stage used in the fifth embodiment. In FIG. 49A, an inverter circuit 220 is a p-channel MOS transistor connected in series between an output node 226 and a power supply potential node.
Transistors 221 and 222 and output node 226
And n-channel MOS transistors 223 and 224 connected in series between the node and the ground potential node. MOS
The gates of transistors 222 and 223 are both connected to input node 225 to receive input signal IN. MO
The second control voltage V is applied to the gate of the S transistor 221.
P is applied, and the first control voltage VN is applied to the gate of the MOS transistor 224. Next, in FIG.
The operation of the inverter circuit illustrated in FIG. 49A will be described with reference to FIG.

Inverter circuit 220 shown in FIG. 49A.
Has a configuration in which the inverter circuits 200 and 210 shown in FIG. 47 (A) and FIG. 48 (A) are combined. Therefore, when a high level signal is applied to input node 225, output node 226 is discharged at a higher speed than when power supply potential Vcc is low or ambient temperature T is high. Similarly, when a low level signal is applied to input node 225, output node 226 is charged more quickly when power supply potential Vcc is low or ambient temperature T is higher than when it is not. Therefore, when the delay stage is formed using the inverter circuit shown in FIG. 49A, the propagation delay time is close to the upper limit value of power supply voltage Vcc or the ambient temperature T for both high level and low level signals. Is longer when is close to the lower limit.

By constructing the delay stage using the inverter circuit as described above, the access time does not fluctuate even when the power supply voltage Vcc and the ambient temperature T fluctuate, and ringing does not occur stably. The output signal Q can be generated.

FIG. 50 is a diagram showing an example of application of the delay stage of the fifth embodiment. In FIG. 50A, a delay stage is provided in the circuit for generating output enable signal OEM shown in FIG. The delay stage 230 includes a delay stage 230 that delays and inverts the delay signal ZCASE of the internal column address strobe signal. Delay stage 230
Is output to the flip-flop 56. Delay stage 2
When the output of 30 goes high, the inverter circuit 58
The output permission signal OEM output from is at high level. The delay stage 230 is the inverter circuit 54 shown in FIG.
Equivalent to. Delay stage 230 includes three cascaded inverter circuits 231, 232, and 233. Inverter circuits 231 to 23 included in the delay stage 230
3 or the inverter circuit 220 shown in FIG.
7 and the inverter circuits 200 and 21 shown in FIG.
0s are alternately connected. Generation of output enable signal OEM is triggered by the fall of signal ZCASE, and therefore inverter circuits 231 and 23 included in delay stage 230 are included.
2 and 233 are inverter circuits 200, 2
It is provided in the order 10 and 200. When the inverter circuit 220 shown in FIG. 49 is used, the inverter circuits 231 to 233 are all composed of the inverter circuit 220.

Next, the operation of the circuit shown in FIG. 50A will be described with reference to the operation waveform diagram of FIG. 50B.

When output instruction signal DOT attains a low level, valid data ZDD is output in response to this. The output enable signal O is output before the fall of the output instruction signal DOT.
Consider a situation where EM rises to a high level. This state corresponds to the state in which invalid data is output. At this time, in delay stage 230, when power supply voltage Vcc is close to lower limit value Vcmn or ambient temperature T is high, the delay time is shortened. Therefore, the output permission signal OE
M rises to a high level because the power supply voltage Vcc is close to the upper limit value Vcmx or the ambient temperature T is the lower limit value Tamn.
Will be faster than if close to. Therefore, the power supply voltage Vc
When c is high or the ambient temperature T is low, the time when the invalid data signal is output from the output node becomes “short”. When the power supply voltage Vcc is close to the upper limit value Vcmx or the ambient temperature T is close to the lower limit value Tamn, the driving force of the MOS transistor is large. Therefore, when this invalid data signal is output, by delaying the time at which it is turned on when the driving force of the MOS transistor, that is, the driving force of the MOS transistor driving the output node is large, The swing width can be made sufficiently small, and the occurrence of ringing can be reliably prevented.

Also, when the output enable signal OEN becomes "H" after the output instructing signal DOT becomes "L" and thereafter the valid data ZDD changes, similarly, ringing is prevented from occurring and stable output is performed. A data signal can be output.

When power supply voltage Vcc is close to lower limit value Vcmn or ambient temperature T is high, the on-timing of the MOS transistor driving the output node becomes "fast". However, in this case, since the driving power of the MOS transistor driving the output node is small, the swing width of the voltage of the output node is not so large, and the ringing can be surely prevented. When the invalid data signal is not output but the valid data signal is output (when the signal OEM rises to the high level after the signal DOT rises to the high level), the MOS for driving the output node
When the driving force of the transistor is small, the timing of turning on the transistor is "advanced", so that the increase in access time is reliably prevented. Since the delay time is adjusted according to the operating condition, the charging / discharging speed of the output node can be made substantially constant regardless of the operating condition.

FIG. 51 is a diagram showing another application example of the delay stage according to the fifth embodiment of the present invention. As shown in FIG. 51A, delay circuit 161 in the output drive circuit shown in FIG. 34 is provided with inverter circuits 241 and 242 according to the fourth embodiment of the present invention. Other configurations are similar to those shown in FIG. The inverter circuits 241 and 242 are the inverter circuits 220 shown in FIG.
Alternatively, the inverter circuit 200 shown in FIGS. 47 and 48.
And 210 are used. In this case, the output permission signal OE
In order to delay the rise of M to the high level, the inverter circuit 210 shown in FIG. 48 is used for the first-stage inverter circuit 241, and the inverter circuit 242 for the next-stage inverter circuit 242 is shown in FIG.
The inverter circuit 200 shown in is used. Next in FIG.
The operation of the output circuit illustrated in FIG. 1A will be described with reference to FIG.

Consider an operation mode in which valid data signal ZDD rises to high level after output permission signal OEM rises to high level. This state is a mode in which an invalid data signal is output. In response to the rise of output enable signal OEM to the high level, the output of delay circuit 161 rises, and accordingly the potential of node 243 rises. At this time, the delay time of the delay circuit 161 is equal to the power supply voltage Vc.
When c is close to the lower limit value Vcmn or the ambient temperature T is close to the upper limit value Tamx, it is shortened. Therefore, the potential of node 243 rises quickly when the driving force of MOS transistor 2 is small. At this time MOS
Since the driving force of transistor 1 is small, the potential of output node 6 gradually rises according to the invalid data signal. Thereafter, the valid data signal is transmitted, internal read data signal ZDD rises to the high level, and MOS transistor 1 is turned off. Although the time TB during which this invalid data signal is output is long, the MOS transistor 1
Since the current driving force of the output voltage is small, the increase in the potential amplitude of the output node 6 is relatively small, and the output data signal can be stably generated without causing ringing even when the drive transistor 2 is turned on. You can

On the other hand, under operating conditions in which the driving power of MOS transistors 1 and 2 is high, the delay time of delay circuit 161 is lengthened. That is, the power supply voltage Vcc is close to the upper limit value Vcmx, or the ambient temperature T is the lower limit value Tam.
When it is close to x, the delay time of the delay circuit 161 becomes long, and the MOS transistor 1 is turned on at a late timing. Therefore, even when the current driving capability of MOS transistor 1 is large, the time for which it is in the ON state is short and the potential rise of output node 6 is small. Therefore, even if MOS transistor 2 is subsequently turned on in accordance with the transmission of the valid data signal, the potential amplitude of output node 6 is sufficiently small, and ringing can be reliably prevented.

When a valid data signal is output, the potential of node 243 is always at the low level, and MOS transistor 1 maintains the off state.

As described above, the potential amplitude of output node 6 can be reduced regardless of the operating conditions, the access time can be prevented from being deteriorated regardless of the operating conditions, and the occurrence of ringing can be surely suppressed. can do.

FIG. 52 is a diagram showing still another application example of the delay circuit according to the fifth embodiment of the present invention. Figure 52
The output control circuit shown in (A) has the same configuration as the output control circuit shown in FIG. In FIG. 52A, inverter circuits 251 to 254 included in the delay circuit 160a.
In contrast, the inverter circuit shown in FIGS. 47 to 49 is applied. That is, also in this delay circuit 160a, the delay time is lengthened under operating conditions in which the driving power of the MOS transistor is large. Other configurations are shown in FIG.
It is similar to the output control circuit shown in FIG. Next in FIG.
The operation of the output control circuit shown in FIG. 52A will be described with reference to FIG.

First, output enable signal OEM rises to a high level. At this time, the internal read data signal ZDD is still at the low level. This state is an operation mode in which an invalid data signal is output. In response to the rise of the output enable signal OEM, the potential of the node N1 rises to the high level, and the drive transistor 1 having a small current driving capability.
a is turned on, and the output node 6 is gently charged. Then, the output of the delay circuit 160a rises to the high level. In response to this, the output of the AND circuit 90a rises to the high level, and the drive transistor 1b is turned on via the node N31a. Delay circuit 160a
Power supply voltage rises to a high level, the power supply voltage Vcc is close to the upper limit value Vcmx, or the ambient temperature T is the lower limit value Ta.
If it is close to mn, it will be slowed down than otherwise. Therefore, the timing at which drive transistor 1b having a large current driving capability is turned on is delayed in an operating environment in which the current driving capability of a MOS transistor is large. Therefore, the potential rise of output node 6 can be reliably suppressed, the potential amplitude of output node 6 can be reduced, and the occurrence of ringing can be suppressed. At this time,
If the delay time of the delay circuit 160a is set to an appropriate value, the time when the drive transistor 1b is turned on can be set to almost zero in an operating environment in which the current driving capability of the MOS transistor is increased.

When only the valid data signal is output, the potential of node N1 is at low level and drive transistors 1a and 1b are not turned on. Therefore, the occurrence of ringing can be reliably prevented regardless of the operating environment.

FIG. 53 is a diagram showing an example of application of the inverter circuit according to the fifth embodiment of the present invention to still another configuration. In FIG. 53A, inverter circuits 261 to 264 of the fourth embodiment are used for delay circuit 12 for driving drive transistor 2b for driving output node 6 to the ground potential level. Regarding the delay time of the delay circuit 12, the power supply voltage Vcc has a lower limit value Vc.
When it is close to mn or the ambient temperature T is close to the upper limit value Tamx, it is shortened. Other configurations are similar to those of the output control circuit shown in FIGS. Next, FIG.
The operation of the output control circuit illustrated in FIG. 53A will be described with reference to FIG.

First, output enable signal OEM rises to a high level. Then, internal read data signal ZDD rises to a high level. As a result, the potential of the node N2 rises to the high level, and then the output of the delay circuit 12 rises to the high level. In response to the rise of the output of the delay circuit 12, the drive transistor 2b having a large current driving force is turned on via the AND circuit 8. At this time, the delay circuit 12 has a long delay time under an operating environment in which the current driving capability of the MOS transistor is large. Therefore, in an operating environment in which the current driving capability of drive transistor 2b is large, the time during which it is in the ON state is delayed, and the potential of output node 6 is turned on after the potential of drive transistor 2a has been made sufficiently low. Therefore, at this time, ringing does not occur even if output node 6 is discharged to the ground potential level with a large current driving force, and stable output data signal Q is obtained.

On the other hand, in the operating environment in which the current driving capability of the MOS transistor is reduced, the timing at which drive transistor 2b is turned on is accelerated. In this case, since the current drivability of drive transistor 2b is relatively small, even if the drive transistor 2b is turned on at a relatively fast timing, the potential of output node 6 is not discharged so rapidly and ringing occurs. A stable output data signal Q is obtained.

At this time, in an operating environment in which the current drivability of MOS transistors 2a and 2b is reduced, the timing at which drive transistor 2b is turned on is set earlier, so the low level output from output node 6 is set. The potential of the data signal Q is determined relatively quickly.
Therefore, even if the operating environment (operating condition) deteriorates, the access time does not become long, and a stable output data signal can be output at high speed.

If no invalid data signal is output,
Internal read data signal ZDD rises to a high level before output enable signal OEM. Also in this case, the potential of node N2 only rises to the high level in response to the rise of output enable signal OEM to the high level, and the change of the delay time of delay circuit 12 is the same as that described above. Is. Therefore, even when only this valid data signal is output, the output data signal can be output stably and at high speed.

Next, the structure for generating the first and second control voltages will be described. FIG. 54 is a diagram showing the configuration of the control voltage generation unit. Referring to FIG. 54, the control voltage generator generates a VREF1 generating circuit 25 that generates a constant reference voltage VREF1 independent of the operating temperature and the power supply voltage.
0, and a VREF2 generation circuit 25 for generating a reference voltage VREF2 that depends on the power supply voltage and the ambient temperature (operating temperature).
1 and the reference voltage VRE from the VREF1 generating circuit 251.
It includes differential amplifier circuits 252 and 253 that differentially amplify the second reference voltage VREF2 from F1 and VREF2 generation circuit 251. The differential amplifier circuit 252 generates the second control voltage VP, and the differential amplifier circuit 253 generates the first control voltage VN. The differential amplifier circuit 252 receives the first reference voltage VREF1 at its positive input and the second reference voltage VREF2 at its negative input. Differential amplifier circuit 25
3 receives the second reference voltage VREF2 at its positive input,
The negative input receives the first reference voltage VREF1. The differential amplifier circuits 252 and 253 can generate the first and second control voltages VP and VN having mutually opposite voltage and temperature dependent characteristics. Next, a specific configuration of each part will be described.

FIG. 55 is a diagram showing characteristics of the first reference voltage VREF1 and a specific structure of the VREF1 generating circuit. As shown in FIG. 55A, the first reference voltage VRE
F1 is a constant voltage that does not depend on the power supply voltage and the operating temperature. Referring to FIG. 55B, VREF1 generation circuit 250 includes constant current source 260 provided between a power supply potential node and output node 264, and temperature compensation provided between output node 264 and a ground potential node. It includes a fixed voltage diode 261. Constant voltage diode with temperature compensation 26
1 includes a PN diode 262 connected in the forward direction from the output node 264, and a Zener diode 263 provided in the reverse direction between the PN diode and the ground potential node. Zener diode 263 has a positive temperature coefficient,
The PN diode 262 has a negative temperature coefficient. The temperature coefficients of the diodes 262 and 263 which are opposite to each other compensate for the temperature dependence of the Zener voltage generated by the Zener diode 263, and a constant voltage is generated regardless of the operating temperature.

When a voltage equal to or higher than the Zener voltage is applied in the opposite direction, Zener diode 263 causes Zener breakdown and generates a constant Zener voltage. In this case, at the output node 264, the Zener voltage due to the Zener diode and P
A voltage that is the sum of the forward voltage drop due to the N diode 262 is generated. The forward drop voltage of the PN diode 262 and the zener diode of the zener diode 263 have negative and positive temperature coefficients, so that a constant voltage can be generated at the output node 264 regardless of the ambient temperature.

In the structure shown in FIG. 55B, as constant current source 260, various circuit structures for generating a constant current regardless of the power supply voltage and the operating temperature are known in the analog integrated circuit technical field. , Such a circuit can be used. Further, instead of the constant current source 260, a resistor having a sufficiently large resistance value (a resistance value large enough to ignore the temperature dependence characteristic) is connected between the output node 264 and the power supply potential node. It is possible to generate the constant reference voltage VREF1 provided by the temperature-compensated Zener diode 260.

FIG. 56 shows an example of the power supply voltage and ambient temperature dependence characteristics of second reference voltage VREF2 and the configuration of the second reference voltage generating circuit. As shown in FIGS. 56A and 56B, the second reference voltage VREF2 is
It has a negative dependence on the power supply voltage and a positive dependence on the operating temperature (ambient temperature).

In FIG. 56C, VREF2 generating circuit 251 includes a constant current source 271 provided between a power supply potential node and an output node 275, an output node and a node 2.
It includes an n-channel MOS transistor 272 provided between node 276 and a resistor 273 provided between node 276 and the ground potential node. The temperature dependence of the resistance value R of the resistor 273 depends on the temperature dependence characteristics of the constant current source 271 and the MOS.
It is made sufficiently larger than the temperature dependence characteristic of the on-resistance of the transistor 272. The resistance value R of the resistor 273 is set to be slightly larger than the ON resistance of the MOS transistor 272. The resistor 273 is formed by using, for example, polysilicon or a diffusion resistor ion-implanted with a relatively high concentration, and has a positive temperature coefficient. Next, the operation will be described.

A constant power supply voltage Vc is supplied from the constant current source 271.
A current is supplied which is independent of c and the ambient temperature. By the constant current from the constant current source 271, the output node 275
Is an on-resistance R provided by the MOS transistor 272.
A reference voltage VREF2 determined by the sum of (272) and the resistance R (273) of the resistance 273 is generated. When the power supply voltage Vcc rises to the upper limit value Vcmx, the MOS
The conductance of the transistor 272 is increased, that is, the resistance value R (272) is decreased, and the output node 2
The reference voltage VREF2 appearing at 75 goes low. That is, the second reference voltage VREF2 has a negative power supply voltage dependence characteristic.

When the ambient temperature T rises, the resistance 27
The resistance value R (273) of 3 increases and the output node 27
The second reference voltage VREF2 from 5 rises. At this time, the on-resistance R (273) of the MOS transistor 272
Although it also changes depending on the ambient temperature T, the change is negligible compared with the temperature-dependent characteristic of the resistor 273. Therefore, the second reference voltage VREF2 is
It has a positive dependence on the ambient temperature T.

For constant current source 271 shown in FIG. 56 (C), a constant current source circuit known in the analog integrated circuit field or the like that does not depend on the power supply voltage and the ambient temperature can be used.

In place of constant current source 271, a structure having a resistance having a positive temperature coefficient and a resistance having a negative temperature coefficient in parallel between power supply potential node and output node 275 may be used. Good. A resistor called a thermistor can be used as the resistor having such positive and negative temperature characteristics.

FIG. 57 shows the first control voltage VN and the second control voltage VN.
FIG. 6 is a diagram showing a generation mode of a control voltage VP of FIG. As shown in FIG. 54, the differential amplifier circuit 252 has the first reference voltage VR.
It receives EF1 at its positive input and receives a second reference voltage VREF2
Is received by its negative input. First reference voltage VREF1
Is constant. If the difference between the first reference voltage VREF1 and the second reference voltage VREF2 becomes large, the second reference voltage VREF
P is amplified by the differential amplifier circuit 252 and its potential rises (see FIG. 57A). That is, when the power supply voltage Vcc increases, the second reference voltage VREF2 decreases. Therefore, the difference (VREF1-VREF2) becomes large and the second control voltage VP rises. On the other hand, when the operating temperature T becomes high, the second reference voltage VREF2
Rises. In this case, the difference (VREF
1-VREF2) becomes small. Therefore, in this case, the second control voltage VP decreases. Therefore, FIG.
A second having the power supply voltage and ambient temperature dependent characteristics shown in FIG.
Control voltage VP can be generated.

On the other hand, the differential amplifier circuit 253 shown in FIG.
Receives a second reference voltage VREF2 at its positive input and a first reference voltage VREF1 at its negative input. Therefore, it is possible to generate the first control voltage VN having a characteristic opposite to that of the second control voltage VP.

The differential amplifier circuits 252 and 253 are known in the analog integrated circuit field to have a constant amplification characteristic regardless of the power supply voltage and the ambient temperature, and such a configuration should be used. You can Therefore, since the operating characteristics of the differential amplifier circuits 252 and 253 do not depend on the power supply voltage and the ambient temperature, the first and second control voltages VN and NP are set to the power supply voltage and the ambient temperature as shown above. It can be adjusted accordingly.

The voltage levels of the first control voltage VN and the second control voltage VP are not particularly described, but
As shown in FIGS. 47 and 48, the MOS transistor is set to an appropriate value within the voltage region for operating in the region between the three poles.

Further, in the structure shown in FIG. 55 (b),
It is possible that the Zener voltage of the Zener diode 263 is higher than the normal operating power supply voltage (for example, 5 volts). In such a case, if the device using this circuit is a semiconductor memory device, a booster circuit is provided for boosting the word line, for example, and the booster circuit boosts the operating power supply voltage Vcc. Allows a sufficient reference voltage VREF from the Zener diode with temperature compensation.
1 can be generated.

When the Zener voltage of the Zener diode 263 is low and has negative temperature characteristics, the PN diode 2
Instead of 62, a resistor having a positive temperature coefficient (for example, a diffusion resistor having a sufficient impurity concentration) may be used.

FIG. 58 shows operating power supply voltage and ambient temperature dependence characteristics of the inverter circuit in the modification of the fifth embodiment. As shown in FIG. 58, in this modified example, the operating power supply voltage Vcc (DEL
AY) is generated from the external power supply voltage and decreases as the external power supply voltage increases, and its value increases as the ambient temperature increases. The voltage and temperature dependence characteristics shown in FIG. 58 are the same as the voltage and temperature dependence characteristics of first control voltage VN shown in FIG. The difference is that the operating power supply voltage Vc
c (DELAY) is a point generated from the external power supply voltage. FIG. 59 shows a structure for generating power supply voltage Vcc (DELAY) shown in FIG.

As shown in FIG. 59, the power supply voltage Vcc (D
The circuit for generating ELAY) has a first reference voltage V
The differential amplifier circuit 290 receives REF1 as a negative input and receives the third reference voltage VREF3 as a positive input.
Power supply voltage Vcc generated from this differential amplifier circuit 290
(DELAY) is applied to the power supply voltage node of inverter circuit 291.

The third reference voltage VREF3 is shown in FIG.
It is created by a circuit configuration similar to that shown in FIG. The difference is that the power supply voltage Vcc is equal to the external power supply voltage ex.
t. It is to be replaced with Vcc. In this case, power supply voltage Vcc (DELAY) has the same voltage and ambient temperature dependence as first control voltage VN shown in FIG. The operating power supply voltage Vcc (DELAY) is the external power supply voltage e.
xt. As Vcc approaches the upper limit, it is lowered, and as ambient temperature rises, it also rises. Therefore, in the inverter circuit 291, when the upper limit value of the external power supply voltage or the ambient temperature is close to the lower limit value, the operating speed becomes slow (the operating power supply voltage is lowered, so that the driving power of the MOS transistor becomes small; the inverter It should be noted that the circuit 291 is not cascaded but used in cascade.

Therefore, as shown in FIG. 59 (B), even if such a structure is used, the delay time is lengthened when external power supply voltage Vcc is high or ambient temperature T is low, and the above-described implementation is performed. The same effect as the example can be obtained.

In the fifth embodiment, the configuration of the output control circuit when the output signal Q is output as a low level has been described. However, the same can be applied to the output control circuit when the output data signal Q is pulled up to the high level, and is also applied to the delay circuits of various modifications of the first to fourth embodiments. It is possible.

Furthermore, in the fifth embodiment, the delay time of the delay circuit may be appropriately changed depending on which of the low level output data signal and the high level output data signal determines the access time.

[Embodiment 6] FIG. 60 schematically shows a structure of an output circuit according to a sixth embodiment of the present invention.
In FIG. 60, an output circuit 926 generating an output signal Q in accordance with output permission signal OEM and internal data signal ZDD.
In contrast, dedicated power supply circuits 304a, 304b, 306
A voltage regulator 301 including a and 306b is provided. The power supply voltage application circuit 304a charges the power supply node 300 at a first speed in response to the output permission signal, and the power supply voltage application circuit 304b responds to the output permission signal OEM and is faster than the first speed. The power supply node 300 is charged at the second rate. The ground voltage applying circuit 306a outputs the output enable signal O
Ground node 302 is discharged at a third rate (which may be equal to the first rate) in response to EM, and ground voltage applying circuit 3
06b discharges power supply node 302 to the ground voltage level at a fourth speed higher than the third speed in response to output enable signal OEM. Although the configuration will be described in detail later, the power supply voltage application circuit 304b is activated at a timing later than the power supply voltage application circuit 304a, and the ground voltage application circuit 306b is activated at a timing later than the ground voltage application circuit 306a. To be in a state. The power supply node 300
And the ground node 302 constitutes a reference power node,
Power supply voltage application circuit 304a, power supply voltage application circuit 304
b, the ground voltage applying circuit 306a, and the ground voltage applying circuit 306b form a reference voltage source.

Output circuit 926 operates upon activation (output activation signal OEM is activated) with the voltage on power supply node 300 and ground node 302 as both operating power supply voltages, and outputs output signal Q.

FIG. 61 shows a structure of the output circuit shown in FIG. 61, output circuit 926 includes an inverter 5 for inverting internal data signal ZDD, a 2-input AND circuit 3 for receiving output enable signal OEM and an output signal of inverter circuit 5, an internal data signal ZDD and output enable signal OEM. N-channel M which receives the voltage VccQ on the power supply node 300 and transmits to the output node 6 in response to the output signal of the AND circuit 3 and the 2-input AND circuit 4 which receives the voltage.
It includes an OS transistor 1 and an n channel MOS transistor 2 which conducts in response to the output signal of AND circuit 4 and transmits voltage VssQ on ground node 302 to output node 6. These n-channel MOS transistors 1 and 2
Respectively form a drive transistor. The structure of the output circuit shown in FIG. 61 is the same as the conventional structure except that the voltages applied to power supply node 300 and ground node 302 are adjusted.

FIG. 62 shows a voltage regulator 301 shown in FIG.
This voltage regulator 301 is composed of inverters 310 and 311 that invert the output permission signal OEM, and an even number of stages (four stages in FIG. 62) that delay the output permission signal OEM by a predetermined time T5. Delay circuit 312
A two-input NAND circuit 313 that receives the output signal of the delay circuit 312 and the output enable signal OEM, and the NAND circuit 31.
3 inverts the output signal of the inverter circuit 3, an n-channel MOS transistor 315 that short-circuits the power supply node 300 and the ground node 302 in response to the output signal of the inverter circuit 310, and a reference voltage in response to the output signal of the inverter circuit 310. It includes an n channel MOS transistor 316 transmitting VREF to power supply node 300, and an n channel MOS transistor 317 transmitting reference voltage VREF to ground node 302 in response to an output signal of inverter circuit 310. The reference voltage VREF is the power supply voltage Vcc.
And an intermediate voltage level between the ground voltage GND and the ground voltage GND. When output node 6 (see FIG. 60) is precharged to the intermediate voltage level, reference voltage VREF may be the intermediate voltage level at which output node 6 is precharged.

Voltage regulator 301 further includes an n-channel MOS transistor 318 for supplying a current from power supply voltage Vcc supply node to power supply node 300 with a first current driving force in response to an output signal of inverter 311 and an inverter. In response to the output signal of the circuit 314, an n-channel MOS transistor 320 for supplying a current from the power supply voltage Vcc supply node to the power supply node 300 with a current driving power larger than the first current driving power, and the output of the inverter circuit 311. In response to the signal, the ground node 3 is driven by the third current driving force.
N channel MOS transistor 319 for discharging current from 02 to the ground voltage supply node, and inverter circuit 314.
From the ground node 302 to the ground voltage GND supply node in response to the output signal of
It includes an n-channel MOS transistor 321 that discharges current with the current driving force of. The first current driving force and the third current driving force may be equal, and the second current driving force and the fourth current driving force may be equal. MOS transistor 318
The magnitude of the current driving power of ~ 321 is W of the transistor.
It is realized by appropriately adjusting the ratio of / L (channel width / channel length). The larger the coefficient β (a constant proportional to W / L), the greater the current driving force.

In the structure of FIG. 62, power supply voltage applying circuit 304a includes a MOS transistor 318, power supply voltage applying circuit 304b includes a MOS transistor 320, and ground voltage applying circuit 306a includes a MOS transistor 319. The circuit 306b includes a MOS transistor 321. Delay circuit 312, NAND circuit 313, and inverter 314 form a rising delay circuit.

The operation of the circuits shown in FIGS. 61 and 62 will now be described with reference to the operation waveform diagram of FIG.

When output enable signal OEM falls from "H" to "L" level, output circuit 926 is inactivated, and the cycle for reading output data Q thereof is completed. FIG. 63 shows, as an example, a configuration in which output signal Q is precharged to an intermediate voltage level when output circuit 926 is inactivated. When the output circuit 926 is inactive, the output circuit 926 may be configured to be maintained in the output high impedance state.

When the output enable signal OEM becomes "L", the output signal of the inverter circuit 310 becomes "H", and the MOS
Transistors 315 to 317 are turned on, and power supply node 300 and ground node 302 are precharged to the reference voltage VREF level of the intermediate voltage level. Also,
The output signal of the inverter circuit 311 falls to "L",
MOS transistors 318 and 319 are turned off. Similarly, the output signal of the NAND circuit 313 also becomes "H", the output signal of the inverter circuit 314 accordingly becomes "L", and the MOS transistors 320 and 321 are turned off. Through this series of operations, nodes 300 and 302 are precharged to the level of reference voltage VREF.

When the next data reading is performed, output enable signal OEM first rises to the "H" level. The output signal of the inverter circuit 310 falls to "L", and the MOS transistors 315 to 317 are turned off. Then
The output signal of the inverter circuit 311 becomes "H", and the MOS transistors 318 and 319 having a small current driving capability.
Is turned on. As a result, the power supply node 300
Is gradually raised in voltage level from the reference voltage VREF level by the MOS transistor 318 having a small current driving capability. Similarly, ground node 302 is gently discharged to the ground voltage level by MOS transistor 319 having a small current driving capability, and the voltage level thereof gradually drops from reference voltage VREF at the intermediate level. According to the logic level of internal data signal ZDD, one of MOS transistors 1 and 2 shown in FIG. 61 is turned on. MOS transistor 1 or 2 which is turned on transmits the voltage on the corresponding reference power supply node (power supply node or ground node) to output node 6 (current between the corresponding reference power supply node and output node 6 Causes the flow of). Therefore, the MOS transistor 31 having a small current driving capability
8 and 319 are first turned on to slowly change the currents at nodes 300 and 302, whereby the voltage on node 300 or 302 is transmitted to output node 6, and the voltage at output node 6 is changed from this intermediate voltage level. It changes slowly. When the voltage level of output node 6 reaches a voltage level at which ringing does not occur, the voltage levels of nodes 300 and 302 are drastically changed at that time, and even if the voltage level of output signal Q is drastically changed accordingly, ringing is generated. Will never occur. That is, output enable signal OEM rises to "H", and after the voltage levels of nodes 300 and 302 change sufficiently, delay circuit 31
The output signal of 2 rises to "H", and accordingly the NAND circuit 3
When the output signal of 13 becomes "L", the inverter circuit 31
The output signal of 4 becomes "H", and the MOS transistors 320 and 321 having a large current driving capability are turned on. As a result, nodes 300 and 302 change in voltage level at high speed to reach power supply Vcc level and ground voltage GND level, respectively. As a result, the voltage level of output node 6 changes to power supply voltage Vcc or ground voltage GND level via drive transistor 1 or 2, and a high-speed and stable output signal can be generated without causing ringing.

[Modification 1] FIG. 64 shows a structure of a main portion of a first modification of the sixth embodiment of the present invention. In the structure shown in FIG. 64, the boosted voltage from boosting circuit 325 is applied to MOS transistors 318 and 320 shown in FIG. The booster circuit 325 boosts the power supply voltage Vcc or the external power supply voltage extVcc to generate a high voltage Vp equal to or higher than the external power supply voltage. In the structure shown in FIG. 64, power supply voltage VccQ applied to power supply node 302 can be set to a voltage level sufficiently higher than internal power supply voltage Vcc. In this case, even if the internal power supply voltage Vcc is lowered due to the reduction of current consumption, etc., "H" having a sufficient voltage level with a margin.
The signal of can be output. Even when the difference between VOH (high-level voltage of output signal) and VOL (low-level voltage of output signal) becomes small in such a low power supply voltage, the booster circuit 325 as shown in FIG. 64 is used. This makes it possible to compensate for the loss in the output drive transistor 1 and generate a high level output signal having a sufficiently high voltage level. Even in this case,
Since power supply node 302 is charged in two stages, no ringing occurs and an output signal having a sufficient voltage level can be stably output at high speed.

FIG. 65 shows a structure of an output circuit when the boosting circuit shown in FIG. 64 is used. In FIG. 65,
The output circuit 926 is provided between the AND circuit 3 and the output drive transistor 1, and operates using the high voltage Vp from the booster circuit 325 as one operating power supply voltage, and sets the “H” level of the output signal of the AND circuit 3 to the high voltage Vp. A level conversion circuit 327 for converting a boosted level to a level is included. AND circuits 3 and 4 operate using internal power supply voltage Vcc as one operating power supply voltage. The structure of level conversion circuit 327 can utilize a structure in which p-channel MOS transistors are configured to receive high voltage Vp at their sources and are cross-coupled. An n-channel MOS transistor is connected between the drain of the p-channel MOS transistor and the ground voltage node. By using level conversion circuit 327, power supply voltage VccQ of high voltage Vp level applied to power supply node 302 can be transmitted to output node 6.

Voltage regulator 301 also receives high voltage Vp. This is because, in the structure shown in FIG. 62, the output signals of inverters 311 and 314 need to be boosted to high voltage Vp level, and high voltage Vp is applied to inverters 311 and 314. These inverters 311 and 314 output a high voltage Vp level signal. In this case, a level conversion circuit may be provided at the output parts of the inverters 311 and 314, or the inverters 311 and 314 themselves may be configured to have a level conversion function.

In this case, the voltage applied to power supply node 300 and the voltage level applied to level converting circuit 327 may be different from each other. That is, the booster circuit 3
Two types of high voltage Vp output from 25 are prepared, and the level conversion circuit 327 level-converts the high level of the output signal of the NAND circuit 3 to the higher one of the two types of high voltage. Inverters 311 and 31
The high level voltage of 4 (see FIG. 52) is also level-converted to this higher high voltage level. In this case, the lower high voltage level can be transmitted to power supply node 300 without the loss of the threshold voltage of the MOS transistor.

In the structure shown in FIG. 65, the output portion of AND circuit 4 is not provided with a level conversion circuit. When output node 6 is discharged, even if the gate potential of drive transistor 2 is at the internal power supply voltage Vcc level, the drive transistor is turned on and the voltage to output node 6 is discharged to the voltage level on ground node 302.
At this time, if the gate potential of drive transistor 2 is at the level of internal power supply voltage Vcc, its conductance is reduced and the discharge rate of output node 6 is made slower than when high voltage Vp is applied. Therefore,
It is possible to suppress a sudden change in current at the start of discharge of the output node 6, which is more effective in suppressing ringing. The gate voltage level of drive transistor 2 is sufficiently higher than the voltage level of its ground node 302, and voltage VssQ on ground node 302 is at high speed to ground voltage GND.
Even if discharged to the level, the voltage level of output node 6 can be discharged at high speed to the level of ground voltage GND according to the high speed discharge.

Also in this case, by providing a level conversion circuit between the gate of drive transistor 2 and AND circuit 4, the gate potential of drive transistor 2 is made sufficiently high, and the discharge speed of output node 6 is adjusted by voltage adjustment. The configuration performed only by the device 301 may be used.
In the above structure, the voltages on power supply node 300 and ground node 302 (collectively referred to as reference power supply node) are changed in two steps. However, a configuration in which the voltage on the reference power supply node is changed over three or more stages may be used.

Further, in the output circuit, a structure using a plurality of drive transistors connected in parallel whose delay time is variable depending on whether or not an invalid signal is output may be used together. The output circuit 926 can be applied to all the first to fifth embodiments.

As described above, according to the sixth embodiment of the present invention, the change speed of the voltage on the reference power supply node of the output stage transistor for driving the output node according to the internal signal is changed over a plurality of steps. Because I configured
The voltage change on the output node 6 can be made gentle at first and gradually made fast, and a fast and stable output signal can be output without causing ringing.

[Embodiment 7] FIG. 66 shows a structure of a main portion of an output circuit according to a seventh embodiment of the present invention. FIG. 66
Shows the configuration of a voltage adjusting unit that supplies both operating power supply voltages of the output circuit. The structure of the output circuit is similar to that shown in FIG.

In FIG. 66, the voltage adjuster differs from the structure of voltage adjuster 301 shown in FIG. 60 in the following points. That is, in the configuration shown in FIG. 66, an n-channel MO responsive to the output signal of inverter circuit 311.
S transistor 328 transmits to power supply node 300 voltage Vccp between reference voltage VREF and power supply voltage Vcc. N channel MOS transistor 330 provided in parallel with MOS transistor 328 transmits power supply voltage Vcc to power supply node 300 in response to the output signal of inverter circuit 314. Further, n channel MOS transistor 329 coupled to ground node 302 transmits voltage Vbsg closer to the voltage level of intermediate voltage VREF than ground voltage GND to ground node 302 in response to the output signal of inverter circuit 311. The n-channel MOS transistor 331 responds to the output signal of the inverter circuit 314 with the ground voltage GND.
To ground node 302. The other configuration is the same as that shown in FIG.

The channel width and channel length ratio W / L of MOS transistors 328 and 330 may be the same, and as shown in FIG. 62, the ratio of channel width and channel length of MOS transistor 328 (or coefficient β). )
May be smaller than that of the MOS transistor 330. The W / L of the MOS transistor 329 is M
It may be equal to or smaller than the OS transistor 331. Next, the operation will be briefly described.

The operation of the output circuit is the same as that shown in FIG. During standby, the inverter circuit 31
The output signal of 0 is "H", and the MOS transistor 31
5, 316 and 317 are in the ON state and node 30
0 and 302 are precharged to the voltage level of the reference voltage VREF. At this time, the output signals of the inverter circuits 311 and 314 are both "L" (the output enable signal OEM is at "L" level), and the MOS transistor 3
28, 330, 321 and 331 are all off.

When the data signal is read, output enable signal OEM rises from "L" to "H". As a result, first, all the MOS transistors 315 to 317 are turned off. First, the output signal of the inverter circuit 311 rises to the "H" level, and the MOS transistor 328
And 329 are turned on. The power node 300 is
By this MOS transistor 328, the voltage is relatively gently charged to the Vccp level which is a voltage level where ringing does not occur. On the other hand, the MOS transistor 329 connects the ground node 302 to the voltage Vbsg at which ringing does not occur.
Discharge slowly to the level. Thereafter, MOS transistors 330 and 331 are turned on by the output signal of inverter circuit 314, power supply node 300 is rapidly charged to power supply voltage Vcc level, and ground node 302 is quickly discharged to ground voltage GND level. It When a high level output signal is output from the output circuit, the voltage on power supply node 300 is transmitted to output node 6 via drive transistor 1 (see FIG. 61). On the other hand, when the output circuit outputs a low level signal, the voltage on ground node 302 is transmitted to output node 6 via drive transistor 2. Therefore, the voltage change at output node 6 is substantially the same as the voltage change at power supply node 300 or ground node 302.
As a result, output signal Q on output node 6 gently changes to a voltage level at which ringing does not occur, and then driven at high speed to the power supply voltage or ground voltage level.
With this configuration, it is possible to output a stable output signal at high speed without causing ringing.

The MOS transistor 329 has the same ratio W / channel width W / channel length as the MOS transistor 331.
It may have L (or coefficient β). Since the source voltage Vbsg of the MOS transistor 329 is higher than the source voltage GND of the MOS transistor 331, the gate voltage of the MOS transistor 329 is effectively lower than the gate voltage of the MOS transistor 331, and accordingly the conductance of the MOS transistor 329 is reduced. It becomes smaller than the conductance of the MOS transistor 331,
As a result, the current driving capability of the MOS transistor 329 is M
This is because the current drivability of the OS transistor 331 is made smaller.

MOS transistor 318 for charging power supply node 300 shown in FIGS. 62 and 66,
P-channel MOS transistors may be used for 320, 328 and 330. Power supply voltage Vcc can be transmitted to power supply node 300 without the loss of the threshold voltage. In the structure shown in FIG. 66, n
When p-channel MOS transistors are used instead of the channel MOS transistors 328 and 330,
The ratio (or coefficient β) of the channel width and the channel length of these p-channel MOS transistors may be the same.
The current drivability of the p-channel MOS transistor receiving the voltage Vccp at its source is p
This is because it is made smaller than that of the channel MOS transistor.

FIG. 67 shows an example of a structure for generating voltages Vccp and Vbsg shown in FIG. 67A shows a structure for generating voltage Vccp, and FIG. 67B shows a structure for generating voltage Vbsg.

In FIG. 67A, the voltage generating circuit is
It includes diode-connected p-channel MOS transistors PM1 to PMn connected in series between a power supply voltage Vcc supply node and a node 332, and a resistor Rp connected between node 332 and a ground voltage GND supply node.
The resistance Rp has a resistance value sufficiently larger than the channel resistance of the MOS transistors PM1 to PMn. Each of the MOS transistors PM1 to PMn operates in the diode mode and reduces the voltage by the absolute value Vthp of the threshold voltage. Therefore, in the structure shown in FIG. 67A, a voltage of Vcc-n.Vthp is output as voltage Vccp. MOS transistors PM1 to PM
The number of n is adjusted to an appropriate value according to the level of the voltage Vccp.

In FIG. 67B, the voltage generating portion is connected in series between resistor Rn connected between power supply voltage Vcc supply node and node 333 and between node 333 and ground voltage GND supply node. , Diode-connected n-channel MOS transistors NM1 to NMn
including. The resistor Rn is a MOS transistor NM1 to N.
It has a resistance value sufficiently larger than each channel resistance of Mn. In this case, the MOS transistors NM1 to NM1
NMn operates in the diode mode and lowers the voltage by the threshold voltage Vthn. Therefore, in the case of the structure shown in FIG. 67 (B), voltage Vbsg appearing at node 33 is n · Vthn (ground voltage GN).
D to 0V).

Voltage Vccp has a value larger than reference voltage VREF, and voltage Vbsg has a value smaller than reference voltage VREF.

Various reference voltage generating circuits can be used instead of the structure of the voltage generating circuit shown in FIGS. 67A and 67B.

As described above, according to the structure of the seventh embodiment of the present invention, the power supply node for supplying the voltage for determining the voltage level of the output signal of the output circuit and the ground voltage are driven in two stages, and In the initial stage, the power supply voltage Vc
Since voltage Vccp lower than c and voltage Vbsg higher than ground voltage GND are configured to supply currents to the power supply node and the ground node, respectively.
By stably generating these voltage levels, it is possible to reliably drive the output node of the output circuit to a voltage level at which ringing does not occur, and thereafter drive at high speed to the power supply voltage Vcc level or the ground voltage GND level. Therefore, a stable output signal without ringing can be output at high speed.

According to the structure of the seventh embodiment,
Since the voltage level at which ringing does not occur can be set by the voltages Vccp and Vbsg, the output node is prevented from being charged and discharged at high speed before the voltage level of the output node is sufficiently changed, and the ringing is surely performed. Occurrence can be suppressed.

[Embodiment 8] FIG. 68 shows a structure of a main portion of an output circuit according to an eighth embodiment of the present invention. In FIG. 68, the output circuit 926 is similar to that of the previous embodiment.
An inverter circuit 5 for inverting the internal data signal ZDD,
An AND circuit 3 receiving the output permission signal OEM and the output signal of the inverter circuit 5, an AND circuit 4 receiving the output permission signal OEM and the internal data signal ZDD, and an output node 6 in response to the output signal of the AND circuit 3, Power node 300
Drive transistor 1 driving to the upper voltage VccQ level and an output drive transistor discharging output node 6 to the voltage VssQ level on ground node 302 in response to the output signal of AND circuit 4.

This output circuit further responds to the signal applied from AND circuit 4 to node N2 to adjust the voltage level on ground node 302 thereof.
including. 68, only the voltage regulator 340 that adjusts the voltage VssQ on the ground node 302 is shown in order to simplify the drawing, but the voltage Vcc on the power supply node 300 is shown.
A voltage regulator is also provided which regulates Q in response to the voltage level on this node N1. The circuit for adjusting voltage VccQ on power supply node 300 according to the signal on node N1 has the same configuration as voltage adjuster 340.

The voltage regulator 340 outputs the output instruction signal DOT.
And a drive circuit 350 that determines whether or not there is an invalid output in response to an external signal on the node N2, adjusts the delay time according to the determination result, and outputs an activation signal after a lapse of a predetermined delay time, Output signal of drive circuit 350 and node N2
A 2-input NAND circuit 351 for receiving the above internal signal, and N
In response to the inverter circuit 352 that inverts the output signal of the AND circuit 351, the inverter circuit 353 that inverts the signal on the node N2, the inverter circuit 354 that inverts the output signal of the inverter circuit 353, and the output signal of the inverter circuit 354. N-channel MOS transistor 360 having a relatively small current driving capability for discharging the ground node 302 to the level of the ground voltage GND, and conducting in response to the output signal of the inverter circuit 352, thereby grounding the ground node 302 to the ground voltage. An n-channel MOS transistor 365 having a relatively large current driving capability of discharging to the GND level is included. Inverter circuits 353 and 354
Form a buffer circuit.

Voltage adjuster 340 further includes an inverter circuit 370 inverting output enable signal OEM, and an n-channel MOS transistor 375 transmitting reference voltage VREF to ground node 302 in response to the output signal of inverter circuit 370. . The MOS transistor 375 becomes conductive when the output enable signal OEM is at “L” and the output circuit 926 is inactive, and the ground node 302 is connected to the reference voltage VREF.
Precharge to.

Drive circuit 350 includes an inverter circuit 381 for inverting output instruction signal DOT, a 2-input NAND circuit 382 for receiving the internal signal on node N2 and the output signal of inverter circuit 381, and an internal signal on node N2 for output. A 2-input AND circuit 383 for receiving the instruction signal DOT, and N
Cross-coupled NAND circuits NA13 and NA1 set in response to the output signal of AND circuit 382 and reset in response to the internal signal on internal node N2.
4 and a flip-flop 384 including the inverter circuit 385, an inverter circuit 385 that receives the output signal of the NAND circuit NA13 included in the flip-flop 384, a delay circuit 387 that delays the output signal of the inverter circuit 385 for a predetermined time T1, and an output signal of the inverter circuit 385. A 2-input NAND circuit 386 for receiving the output signal of the AND circuit 383, and a NAN
It includes a delay circuit 388 delaying the output signal of D circuit 386 for a predetermined time T2, and a 2-input NAND circuit 389 receiving output signals of delay circuits 387 and 388.

Flip-flop 384 determines whether a valid signal ("H" signal) is output on internal node N2 when output instructing signal DOT attains an active "H" level. It has a function. The delay time T1 of the delay circuit 387 is set longer than the delay time T2 of the delay circuit 388.

The structure of drive circuit 350 is substantially the same as that of the control circuit for adjusting the conduction timing of the drive transistor shown in FIG. Next, the operation will be briefly described.

First, with reference to the operation waveform diagram shown in FIG. 69, the operation when there is no invalid output will be described. The internal signal on this internal node N2 is "L" or "H".
Rises to, the output signals of the inverter circuits 353 and 354 become "H" accordingly, and the MOS transistor 360
Is turned on, and the small current driving force causes the voltage VssQ on the ground node 302 to change to the intermediate voltage VRE.
Discharge from F to the ground voltage GND. At this time, output enable signal OEM has risen to "H", and accordingly MOS transistor 345 is in the off state, and ground node 302
Is separated from the intermediate voltage VREF source. On the other hand, the output discharge drive transistor 2 is connected to the internal node N
It is turned on in response to the internal signal on 2 to discharge output node 6 to the voltage VssQ level on its ground node 302. At this time, since the output instruction signal DOT has not risen to "H", this signal is an invalid signal. Therefore, the output signal until the node N2 becomes "H" is an invalid signal, and the output node 6 is charged from the power supply node 300 via the drive transistor 1. The flip-flop 384 is reset and its output signal is "L".
Is. When the output instruction signal DOT rises from "L" to "H", the output signal of the NAND circuit 382 becomes "L",
Flip-flop 384 is set, and accordingly, the output signal of inverter circuit 385 falls to "L". On the other hand, AN
The output signal of the D circuit 383 also rises to "H" at the same time, but at this time, the output signal of the inverter circuit 385 is at "L" and the output signal of the NAND circuit 386 maintains "H". Therefore, the output signal of the delay circuit 388 maintains "H".

The output signal of the inverter circuit 385 is "L".
When a predetermined time T1 elapses after falling to the delay circuit 3, the delay circuit 3
The output signal of 87 falls to "L", and the NAND circuit 389
Output signal rises to "H". At this time, already the node N
The internal signal on 2 rises to "H", the input signals of the NAND circuit 351 both become "H", the output signal of this NAND circuit 351 falls from "H" to "L", and accordingly, The output signal of the inverter circuit 352 changes from "L" to "H".
Rise to. As a result, MOS transistor 365 having a large current drivability, which has been in the off state until then, is turned on, and ground node 302 is rapidly lowered to the level of ground voltage GND. As a result, the drive transistor 2
Output signal Q on output node 6 also rapidly drops to ground voltage GND level via. MOS transistor 35
5 is turned on when the output instruction signal DOT is "H".
This is after the elapse of the delay time T1 from the rise to By increasing the delay time T1, the output signal Q raised by the invalid output can be gently lowered to a voltage level at which ringing does not occur, and then can be rapidly lowered to the ground voltage GND level to cause ringing. Not stable output signal can be output.

Next, the operation in the case where the invalid output signal is not output will be described with reference to the operation waveform diagram of FIG. In this state, the internal signal on the internal node N2 rises to "H" after the output instruction signal DOT becomes "H". When both the internal signal on node N2 and the output instruction signal DOT become "H", the NAND circuit 38
The output signal of 3 becomes "H". On the other hand, while the internal signal on internal node N2 is "L", the output signal of NAND circuit 382 is irrespective of the state of output instruction signal DOT.
The flip-flop 384, which is "H", maintains the reset state, and its output signal maintains "L". Accordingly, the output signal of inverter circuit 385 maintains the "H" state. Therefore, when the output signal of the NAND circuit 383 rises to "H", the output signal of the NAND circuit 386 falls to "L", and after the elapse of the predetermined time T2, the delay circuit 3
The output signal of 88 falls to "L". This allows NAN
The output signal of the D circuit 389 rises from "L" to "H".

When the internal signal on internal node N2 rises to "H", inverter circuits 353 and 354 drive MO.
The S transistor 360 is turned on. On the other hand, at this time, MOS transistor 375 is in the off state, and voltage VssQ on ground node 302 is discharged at the level of ground voltage GND via MOS transistor 360, and the potential thereof gently drops. As a result, drive transistor 2 receives voltage VssQ on ground node 302.
According to the above, the output signal Q on the output node 6 is discharged. Therefore, the potential change of output signal Q on output node 6 is gradual, and ringing does not occur on output node 6. After the delay time T2 elapses after the internal signal on the internal node N2 rises to "H", the output signal of the NAND circuit 351 becomes "L" and the output signal of the inverter circuit 352 becomes "H", The MOS transistor 365 having a large current driving force is turned on. As a result, the ground node 3 is lowered to a voltage level where ringing does not occur.
The voltage VssQ on 02 is high speed M with a large current driving force.
The OS transistor 365 discharges the voltage to the ground voltage GND level. Drive transistor 2 discharges the voltage on output node 6 to the voltage level on ground node 302. Therefore, in this case, although output signal Q on output node 6 rapidly drops, it has already dropped to a voltage level at which ringing does not occur, so a stable output signal without ringing is output to output node 6. ..

As described above, by adjusting the on-timing of transistor 365 driving ground node 302 according to the presence / absence of an invalid signal output, the voltage level on output node 6 is surely set to a voltage level at which ringing does not occur. After that, the voltage on output node 6 can be discharged to the ground voltage level at a high speed, and a stable output signal with no ringing can be generated regardless of the presence or absence of an invalid signal.

Note that in the structure shown in FIG. 68, the MOS
Transistor 360 may be connected to receive voltage Vbsg higher than the level of ground voltage GND, as shown in FIG. Further, for the output circuit 926, as shown in FIGS. 23, 25, 27, 29, and 31 and the like, the timing of turning on the transistor having a large current driving force is changed depending on the presence or absence of the invalid output. A configuration may be provided.

The structure of drive circuit 350 included in the voltage regulator shown in FIG. 68 may be any structure as long as the timing at which MOS transistor 365 is turned on differs depending on the presence or absence of an invalid signal output. 25,
The configurations shown in FIGS. 27, 29 and 31 can be applied to this control circuit.

As described above, according to the structure of the eighth embodiment of the present invention, a plurality of transistors having different current driving capability are provided for the reference power supply node of the output circuit, and the current driving capability is determined according to the presence / absence of invalid output. Since it is configured such that the timing of turning on a large transistor is different, an output signal without ringing can be output at high speed regardless of the presence or absence of invalid output.

[Embodiment 9] FIG. 71 shows a structure of an output circuit according to a ninth embodiment of the present invention. In FIG. 71, output circuit 926 includes delay circuit 401 that delays the signal on internal node N2 for a predetermined time, and delay circuit 402 that further delays the output signal of delay circuit 401 for a predetermined time.
A NAND circuit 404 which receives the signal on the internal node N2 and the output signal of the delay circuit 401, and a 2-input AND which receives the internal signal on the internal node N2 and the output signal of the delay circuit 402
Responsive to the output signal of the circuit 706, the drive transistor 2e formed of an n-channel MOS transistor which conducts in response to the internal signal on the internal node N2 and discharges the output node 6 to the level of the ground voltage GND, and the output signal of the AND circuit 404. Drive transistor 2f formed of an n-channel MOS transistor discharging the output node 6 to the ground voltage GND level and the output signal of the AND circuit 406, and turning on the output node 6 to the ground voltage GND level. It includes a drive transistor 2g formed of an n-channel MOS transistor that discharges to.

The output circuit 926 is also an inverter circuit 5 for inverting the internal data signal ZDD as in the previous embodiment.
And an AND circuit 3 receiving the output enable signal OEM and the output signal of the inverter circuit 5, and an n-channel MOS transistor which conducts in response to the output signal of the AND circuit 3 and charges the output node 6 to the power supply voltage Vcc level. Drive transistor 1 to be turned on, and an AND circuit 4 for turning on drive transistor 2e in response to output enable signal OEM and internal data signal ZDD. The drive transistors 2e, 2f and 2g have other threshold voltages Vth.
1, Vth2 and Vth3, and a bias voltage VBB is applied to each well region (or substrate region).
1, VBB2, and VBB3 are provided.

Threshold voltages Vth1, Vth2 and V
th3 satisfies the relationship of Vth1>Vth2>Vth3> 0, and the substrate bias voltages VBB1 and VB are satisfied.
B2 and VBB3 satisfy the relationship of VBB1 <VBB2 <VBB3 <0. The n-channel MOS transistor is
When the threshold voltage becomes high, when the same gate voltage is applied, the gate potential is effectively lowered and the conductance is reduced. Therefore, when the "H" level voltage of the same voltage level is applied to drive transistors 2e, 2f and 2g, the conductance increases in the order of drive transistors 2e, 2f and 2g. Similarly, the substrate bias voltage generally increases the threshold voltage of the MOS transistor as its absolute value increases. Therefore, similarly, due to the influence of the substrate bias voltage, the substrate bias effect is reduced and the conductance is increased in the order of drive transistors 2e, 2f, and 2g. However, here, it is assumed that the drive transistors 2e, 2f, and 2g have the same size.

In operation, when the internal signal on internal node N2 rises to "H", drive transistor 2e is turned on and output node 6 is set to ground voltage GND.
Discharged to level. The threshold voltage Vth1 of the drive transistor 2e is the highest, the substrate bias voltage thereof is also the lowest, and the substrate bias effect is high. Therefore, output node 6 is discharged to the level of ground voltage GND with a relatively small current drivability. Next, when the output signal of the delay circuit 401 rises to "H", the drive transistor 2f is turned on.
Drive transistor 2f has threshold voltage Vth2 and substrate bias voltage VBB2 of intermediate magnitudes, and discharges output node 6 to the level of ground voltage GND with a relatively large current driving force. Then, the output signal of the delay circuit 402 rises to "H", the output signal of the AND circuit 406 accordingly becomes "H", and the drive transistor 2g is turned on. Drive transistor 2
g has the smallest substrate bias and the smallest threshold voltage Vth3. Therefore, output node 6 is discharged to the level of ground voltage GND with a large current drivability. As a result, the drive transistor 2
The voltage on output node 6 lowered to a voltage level where ringing does not occur by e and 2f is discharged at high speed to ground voltage GND level through drive transistor 2g. In this way, the substrate bias voltage VBB (VB
B1 to VBB3) and the threshold voltage Vth (Vth1
~ Vth3) is made different, and the current driving capability of the drive transistor is made to differ according to which the output node 6 is discharged relatively gently in the initial stage, and the voltage level drops to a level at which ringing does not occur. In addition, the output transistor 6 can be discharged to the ground voltage GND level at high speed by using the drive transistor having a large current driving capability, and a stable output signal without ringing can be output at high speed.

[Modification 1] FIG. 71 shows a modification of the output circuit of the ninth embodiment of the present invention. In FIG. 71, the voltage Vss from voltage regulator 301b is applied to ground node 302 forming the sources of drive transistors 2e, 2f and 2g for discharging output node 6.
Q is given. The drive transistors 2e, 2f and 2g and the delay circuits 401 and 402 are similar to those shown in FIG.
The same reference numerals are given to corresponding parts. This voltage regulator 301b responds to the output enable signal OEM by changing its output voltage VssQ to the reference voltage VR.
Change from EF to the ground voltage GND level. The structure of this voltage regulator is similar to that shown in FIGS. 62 and 66.

In FIG. 72, the output circuit further includes drive transistors 1e, 1f and 1g formed of n channel MOS transistors in parallel with each other between power supply node 300 and output node 6. Drive transistor 1e becomes conductive in response to the signal on internal node N1. The drive transistor 1f has an internal node N
The signal on 1 is rendered conductive in response to the output signal of the delay circuit 403 which delays for a predetermined time. The drive transistor 1g is
Delay circuit 4 for further delaying the output signal of delay circuit 403
It conducts in response to the output signal of 04. These drive transistors 1e, 1f and 1g have different threshold voltages and different substrate bias voltages. In FIG. 72, as an example, drive transistors 1e, 1f and 1g have the same magnitudes as the threshold voltage and bias voltage of drive transistors 2e, 2f and 2g for discharging output node 6, respectively. It is shown to have a threshold voltage and a bias voltage. These may be set to different values. In the output charging drive transistors 1e to 1g, the drive transistor that is turned on first may have a large threshold voltage and a deep substrate bias. Delay circuits 403 and 404 have the same delay times as delay circuits 401 and 402, respectively.

To the power supply node 300, the voltage regulator 301
The voltage VccQ from a is applied. This voltage regulator 3
01a is activated in response to the output enable signal OEM,
The output voltage VccQ is adjusted from the level of the reference voltage VRF. This voltage regulator 301a is a voltage regulator 301a.
Similar to b, the structure shown in FIG. 62 or 66 may be provided.

Generally, the current (drain current) Ids flowing from the drain to the source of a MOS transistor is given by the following equation.

Saturation region: | Vds | ≧ | Vgs-Vth |; Ids = (Vgs-Vth) ² Unsaturation region: | Vds | <| Vgs-Vth |: Ids = A {(Vgs-Vth) Vds- ( Vgs /
2)} where Vds is the drain-source voltage, and Vg
s indicates the gate-source voltage. Vth represents a threshold voltage. In both the saturated region and the unsaturated region, when the gate-source voltage Vgs becomes small,
The drain current Ids is greatly affected by the threshold voltage Vth. That is, in other words, the power supply voltage Vcc
Is lowered and the amplitude of the output signal of the output node 6 is reduced, the rate of change of the signal on the output node 6 can be sufficiently adjusted by this threshold voltage by the threshold voltage Vth. is there. Similarly, the threshold voltage Vth has a relationship of Vth = A + B (C + | VBB |) ^1/2 . That is, the threshold voltage Vth increases in absolute value according to the absolute value of the substrate bias voltage VBB. Therefore, similarly, even when the power supply voltage is lowered, the influence of substrate voltage bias VBB is superimposed on the threshold voltage, and the change in the voltage level of output node 6 can be adjusted. In particular, as shown in FIG.
The following advantages are obtained when adjusting the voltages of 00 and ground node 302.

More specifically, in the initial stage when output enable signal OEM is activated, voltage VssQ applied to ground node 302 is at a voltage level higher than ground voltage GND. In this case, drive transistor 2 for discharging
The source potentials of e, 2f and 2g rise and the gate voltage is effectively lowered accordingly. That is, the gate voltage V
gs is reduced. In this case, as is clear from the above formula, the influence of the threshold voltage Vth becomes large,
Accordingly, the influence of the substrate bias voltage also becomes large. On the other hand, when the voltage level of output node 6 decreases to a voltage level at which ringing does not occur, the voltage level on ground node 302 is also set to the ground voltage GND level, and the gate-source voltage Vgs of drive transistors 2e to 2g is also a sufficiently large value. Becomes In this case, the influence of threshold voltage Vth is made relatively small, and output node 6 is grounded at ground voltage GN at high speed.
It can be discharged to the D level. Therefore, by gradually changing the voltage on ground node 302, the current driving capability of the drive transistor can be effectively adjusted by utilizing the influence of the substrate bias voltage and the ground threshold voltage.

The same applies to drive transistors 1e, 1f, 1g for charging output node 6. In this case, when the voltage on power supply node 300 is relatively low, only drive transistor 1e is turned on. At this time, in drive transistor 1e, in the drain (conducting region connected to power supply node 300), the impurity region and the substrate region are in a relatively weak reverse bias state, and the depletion layer spreads relatively. It Therefore, in this case, the drain electric field is small, the flow of the drain current is suppressed, and the drain current depends on the substrate bias. Therefore, the drain current can be effectively suppressed, and the current is gradually supplied from power supply node 300 to output node 6. When the voltage VccQ on the power supply node 300 becomes a sufficiently large value,
In drive transistors 1e to 1g, the drain region and the substrate region are sufficiently reverse-biased, the depletion layer is sufficiently narrowed, and the drain current easily flows. Therefore, in this case, the bias voltage dependency is not impaired and a relatively large drain current can be supplied. In this state, drive transistor 1e is turned on. Therefore, also in drive transistors 1e to 1g for charging the output node, the current driving capability thereof can be adjusted by adjusting the threshold voltage and the bias voltage to appropriate values. In this way, the ground node 302 and the power supply node 3
By using a plurality of drive transistors that differ in substrate bias voltage and threshold voltage in combination with a circuit that adjusts the voltages VssQ and VccQ on 00,
An output circuit that effectively suppresses the occurrence of ringing can be obtained.

Also in the configurations shown in FIGS. 71 and 72, the ringing of the output signal can be more effectively performed by combining the timing of turning on drive transistors 1e and 2e with the presence or absence of the invalid output. Can be suppressed.

As described above, according to the structure of the ninth embodiment of the present invention, a plurality of transistors having different substrate bias voltages and threshold voltages are provided in parallel between the output node and the reference power supply node. Since these drive transistors are configured to be turned on at different timings, the current drive capability of these drive transistors is different, so an output that outputs a stable output signal at high speed while effectively suppressing ringing. The circuit can be obtained.

[Embodiment 10] FIG. 73 shows the first embodiment of the present invention.
It is a figure which shows the structure and operation | movement of the output circuit which is an Example of 0. In FIG. 73A, a rising delay circuit 4 delays the signal on internal node N2 for a predetermined time between output node 6 and drive transistor 2 for discharging the output node.
N-channel MOS which conducts in response to the output signal A of 10
Transistor 412 and this MOS transistor 412
A resistance element 414 is provided in parallel therewith. Resistance 414
Has a current limiting function. Other configurations are similar to those of the previous embodiment, the inverter circuit 5 for inverting the internal data signal ZDD, the AND circuit 3 for receiving the output enable signal OEM and the output signal of the inverter circuit 5, and the output signal of the AND circuit 3. In response to drive transistor 1 which conducts in response to NOH and transmits power supply voltage Vcc to output node 6, AND circuit 4 which receives output enable signal OEM and internal data signal ZDD, and in response to output signal NOL of AND circuit 4. A drive transistor 2 that is conductive is provided. Next, the operation of the output circuit shown in FIG. 73A will be described with reference to the operation waveform diagram of FIG. 73B.

When output enable signal OEM is "L", AN
The output signal NOL of the D circuit 4 is "L", and the drive transistor 2 is off. In this state,
The output signal A of the rising delay circuit 410 is "L", and M
The OS transistor 412 is off.

When output enable signal OEM and internal data signal ZDD both attain "H", output signal NOL from AND circuit 4 rises to "H", and drive transistor 2 is turned on. At this time, the rise delay circuit 410
Output signal A is still at "L" level, and MOS transistor 412 is in the off state. Therefore, in this state, output node 6 is discharged to ground voltage GND level through resistance element 414 and drive transistor 2. In this case, output node 6 is discharged relatively slowly due to the current limiting function of resistance element 414.

After a predetermined time T6 has elapsed after the output signal NOL of the AND circuit 4 rises to "H", the rising delay circuit 41
The output signal A of 0 rises to "H". This allows the MOS
The transistor 412 is turned on, and the resistance element 414
Are short-circuited. The on resistance (channel resistance) of the MOS transistor 412 is set to a value sufficiently smaller than the resistance value of the resistance element 414. Therefore, output node 6 is rapidly discharged to the level of ground voltage GND through MOS transistor 412 and drive transistor 2. When MOS transistor 412 is turned on, the voltage level of output node 6 has dropped to a voltage level at which ringing does not occur, and even if the voltage level of output node 6 is discharged to the ground voltage GND level at high speed. , No ringing occurs at its output node.

Delay circuit 410 shown in FIG.
MOS transistor 412 and resistance element 414 may also be provided for drive transistor 1 for charging the output node.

[Modification 1] FIG. 74 shows a tenth embodiment of the present invention.
FIG. 9 is a diagram showing a configuration and an operation of a first modification of the output circuit of the embodiment of FIG. In FIG. 74A, the output circuit 926
In the same manner as in the conventional case, the inverter circuit 5 that inverts the internal data signal ZDD, the AND circuit 3 that receives the output signal of the inverter circuit 5 and the output permission signal OEM, and the output signal NOH of the AND circuit 3 become conductive, Drive transistor 1 for charging output node 6 to the level of power supply voltage Vcc
And AND circuit 4 receiving output enable signal OEM and internal data signal ZDD, and drive transistor 2h which conducts in response to output signal NOL1 of AND circuit 4 and discharges output node 6 to the level of ground voltage GND.

Output circuit 926 further includes a rising delay circuit 420 delaying the rising of output signal NOL1 of AND circuit 4 for a predetermined time, and a rising delay circuit delaying rising of output signal NOL2 of rising delay circuit 420 for a further predetermined time. 422, a MOS transistor 424 whose one end is connected to the output node 6 and which is rendered conductive in response to the output signal A of the rise delay circuit 422, a resistance element 426 connected in parallel with the MOS transistor 424, and a rise delay circuit. Included is a drive transistor 2i which is rendered conductive in response to output signal NOL2 of 420 and couples resistance element 426 to ground voltage GND. The channel width of drive transistor 2h is smaller than that of drive transistor 2i, and the current driving capability of drive transistor 2h is smaller than that of drive transistor 2i. Further, the channel resistance (ON resistance) of the MOS transistor 424 is made sufficiently smaller than the ON resistance value of the resistance element 426. Next, the operation of the output circuit shown in FIG. 74 (A) will be described with reference to the operation waveform diagram of FIG. 74 (B).
Will be described with reference to.

When at least one of output enable signal OEM and internal data signal ZDD is "L", AND circuit 4
The output signal NOL1 of 1 maintains the state of "L". In this state, drive transistors 2h and 2i are both off, and output node 6 is not discharged.

When output enable signal OEM and internal data signal ZDD both attain "H", output signal NOL1 of AND circuit 4 rises to "H". As a result, first, the drive transistor 2h is turned on, and the output node 6
Is relatively slowly discharged to the ground voltage GND level by drive transistor 2h having a small current driving capability. After the delay time T7 of the rising delay circuit 420 elapses after the signal NOL1 rises to "H", the output signal NOL2 of the rising delay circuit 420 becomes "H",
The drive transistor 2i is turned on. Thus, output node 6 is discharged to ground voltage GND level through resistance element 426 and drive transistor 2i. Due to the current limiting function of resistance element 426, output node 6 is discharged to the ground voltage level somewhat gently.

Further, after the delay time T8 of the rising delay circuit 422 elapses after the signal NOL2 rises to "H", the output signal A of the rising delay circuit 422 rises to "H", and the MOS transistor is turned on. 424 is turned on. The channel resistance (ON resistance) of MOS transistor 424 is made sufficiently smaller than the resistance value of resistance element 426. Therefore, output node 6 is rapidly discharged to ground voltage GND level by drive transistor 2i due to its large current driving capability. It This allows
Since the voltage level of output node 6 is discharged to the ground voltage level at a high speed when the voltage level drops to a level at which ringing does not occur, an output signal can be generated at a high speed without causing ringing. Further, at this time, since the rate of decrease of the voltage level of the output node 6 is sequentially increased over three steps, the discharge rate of the output node 6 is increased at the time when the possibility of occurrence of ringing is reduced, resulting in higher speed. And an output signal can be generated without causing ringing.

The structure shown in FIG. 74A can also be applied to the structure in which output node 6 is charged to the level of power supply voltage Vcc.

In addition, FIG. 73 (A) and FIG.
With respect to the configuration of the output circuit shown in (A), a voltage regulator is used instead of the voltage power supply Vcc and the ground voltage GND.
ccQ and VssQ may be provided. Further, for the drive transistors 1 and 2h, a configuration may be used in which the timing of turning on the drive transistors 1 and 2h is different depending on the presence or absence of the invalid output.

As described above, according to the tenth embodiment of the present invention, the output node is first driven to the voltage level of the reference power supply node by using the resistance element, and then the resistance element is short-circuited to change the output node. Since it is driven to the voltage level of the reference power supply node at high speed, the output node is driven gently by the current limiting function of the resistance element when there is a possibility of ringing, and then output at high speed when no ringing occurs. Since the node is driven, it is possible to obtain an output circuit that outputs an output signal stably and at high speed without causing ringing.

[Embodiment 11] FIG. 75 shows the first embodiment of the present invention.
FIG. 3 is a diagram showing the configuration and operation of the output circuit according to the first embodiment. In FIG. 75A, an output circuit 926 is an inverter circuit 5 that inverts the internal data signal ZDD, an output signal of the inverter circuit 5 and an output permission signal OE, as in the conventional case.
AND circuit 3 receiving M and output signal N of AND circuit 3
Conducting in response to OH, the output node 6 is supplied with the power supply voltage Vcc.
It includes a drive transistor 1 charged to a level, an AND circuit 4 receiving an output enable signal OEM and an internal data signal ZDD.

The output circuit 926 further includes an output node 6
Of the resistance elements 43 having different resistance values that are coupled in parallel with each other
0, 432, and 434, and a drive transistor 2j that connects the other end of the resistance element 430 to the ground voltage GND level in response to the output signal NOL1 of the AND circuit 4.
The rising edge of the output signal NOL1 of the AND circuit 4 is set to the predetermined time T
9. A rising delay circuit 440 that delays by nine, a drive transistor 2k that conducts in response to the output signal NOL2 of the rising delay circuit 440, and couples the other end of the resistance element 432 to the ground voltage GND level, and an output signal of the rising delay circuit 440. A rising delay circuit 442 that further delays the rising of NOL2 by a predetermined time T10, and a drive transistor 21 that couples the other end of the resistance element 434 to the ground voltage GND level in response to the output signal NOL3 of the rising delay circuit 442.
including. Resistance elements 430, 432 and 434 have a large resistance value in this order. Next, the operation of the circuit shown in FIG. 75 (A) will be described with reference to the signal waveform diagram of FIG. 75 (B).

When output enable signal OEM and internal data signal ZDD both attain "H", output signal NOL1 of AND circuit 4 attains "H". As a result, the drive transistor 2j is turned on. In this state,
The output node 6 has a resistance element 430 having a large resistance value.
Is discharged to the ground voltage GND level via. The resistance element 430 has the largest current limiting function (has the largest resistance value), and the voltage drop of the output node 6 is relatively gradual. Next, when the predetermined time T9 elapses, the signal NOL2 from the rising delay circuit 440 becomes "H".
And the drive transistor 2k is turned on,
Output node 6 is discharged to the ground voltage level through resistance element 432. The resistance element 432 has a resistance value smaller than that of the resistance element 430, and therefore, the potential of the output node 6 is discharged somewhat gently.

Then, after a lapse of time T10 from the rise of signal NOL2, output signal NOL3 of rise delay circuit 442 becomes "H", and drive transistor 21 is turned on. Resistance element 434 has the smallest resistance value, and therefore output node 6 is rapidly discharged to the level of ground voltage GND. When the drive transistor 2l is turned on, the voltage level of the output node 6 has already dropped to a voltage level at which ringing does not occur. Even if the output node 6 is discharged at high speed through the drive transistor 2l, ringing occurs. Is generated at the output node and a stable output signal can be generated.

In the structure shown in FIG. 75A, resistance elements 430, 432 and 434 have resistance values different from each other, and the resistance elements are arranged to discharge the output node in order from the largest resistance element. . This configuration provides the following advantages over the configuration in which the resistance elements having the same resistance value are provided in parallel at the output node 6. When resistance elements having the same resistance value are provided in parallel, the combined resistance connected to this output node 6 is successively reduced.
Therefore, even in this case, output node 6 can be sequentially discharged at high speed. However, even when the voltage level at which ringing does not occur is reached, the discharge speed is determined by the combined resistance value determined by the number of resistance elements, and the output node 6 may not be discharged at high speed. Therefore, by utilizing the configuration having different resistance values, the voltage of output node 6 can be discharged at a high speed when the voltage of output node 6 is reduced to a voltage level where ringing is not reliably generated, and thus the higher speed. An output signal can be generated.

The structure shown in FIG. 75A can also be applied to the structure for charging output node 6.

Furthermore, in the structure shown in FIG. 75A, a structure in which the timing at which the drive transistor is turned on may be changed depending on the presence / absence of an invalid output signal may also be used. Further, a voltage regulator that applies voltages VccQ and VssQ to the power supply node and the ground node may be used.

As described above, according to the tenth embodiment of the present invention, a plurality of resistance elements having different resistance values are connected in parallel to the output node, and the output nodes are charged and discharged in order from the resistance element having the largest resistance value. When the output node has ringing, it charges and discharges relatively slowly, and when the output node changes to a voltage level where ringing does not occur, the output node reaches the minimum voltage level at high speed. It is possible to obtain an output circuit that can be driven and can generate an output signal at high speed without causing ringing.

[Embodiment 12] FIG. 76 shows the first embodiment of the present invention.
2 is a diagram schematically showing a configuration of an output circuit that is an embodiment of FIG. In FIG. 76, the output circuit 926 has an internal data signal, an output permission signal and an output instruction signal DO if necessary.
Drive circuit 450 generating a data signal output according to T, and drive transistors 1 and 2 outputting output signal Q to output node 6 according to the output signal of drive circuit 450 are included. The structure of the output circuit 926 is similar to that of the previous embodiment or the conventional structure.

Referring to FIG. 76, the output circuit further includes a reference voltage generating circuit 47 which is supplied with a current from external power supply voltage extVcc supply node 455 and generates a reference voltage VREF3 dependent on temperature and external power supply voltage extVcc.
0, a constant reference voltage VREF1 that does not depend on the temperature T and the external power supply voltage extVcc, and this reference voltage VREF
3 and a differential amplifier 460 that differentially amplifies. Differential operating amplifier 460 supplies one-side operating power supply voltage VccQ to output circuit 926 to power supply node 300. Differential amplifier 460 operates with external power supply voltage extVcc applied to external power supply voltage extVcc supply node 455 as one operating power supply voltage. The reference voltage VREF1 is
It is generated using the circuit configuration shown in FIG. 55B (however, reference voltage VREF1 is generated from external power supply voltage extVcc).

Reference voltage generating circuit 470 includes constant current source 471 for supplying a constant current from external power supply voltage extVcc supply node 455 to node 475, and MOS connected in series between node 475 and the ground voltage GND supply node.
It includes a transistor 472 and a resistance element 473. MO
The external power supply voltage ex is applied to the gate of the S transistor 472.
tVcc is given. The configuration of reference voltage generating circuit 470 is substantially the same as that shown in FIG. Simply change the external power supply voltage extVcc to the reference voltage VRE.
Only F3 has been generated. That is, resistance element 473 is formed using, for example, polysilicon or a diffusion resistance ion-implanted with a relatively high concentration, and has a positive temperature coefficient. The resistance value R of this resistance element 473
Is made slightly larger than the on-resistance of the MOS transistor 472. The temperature dependence of the resistance value R of the resistor 473 is made sufficiently larger than the temperature dependence characteristics of the constant current source 271 and the ON resistance of the MOS transistor 472. MOS transistor 472 functions as a variable resistance element that provides a conductance that changes according to external power supply voltage extVcc. The operation of reference voltage generating circuit 470 is the same as that of the reference voltage generating circuit shown in FIG. 56 (C), and detailed description thereof will be omitted. The reference voltage generating circuit 470 has a negative dependence characteristic on the external power supply voltage extVcc as shown in FIG. 77 (A), and has a negative dependency on the ambient temperature (operating temperature) as shown in FIG. 77 (B). As a result, the reference voltage VREF3 having a positive dependence characteristic is generated.

The differential amplifier 460 uses the reference voltage VREF3.
And the reference voltage VREF1 is amplified. When the operating temperature (ambient temperature) T rises, the reference voltage VREF3 rises, and the voltage V output from the differential amplifier 460 accordingly.
ccQ increases. On the other hand, when the ambient temperature (operating temperature) T is constant and the external power supply voltage extVcc rises,
The reference voltage VREF3 decreases, and accordingly the differential amplifier 460
The voltage VccQ output from the device decreases. That is, differential amplifier 460 has a positive dependence characteristic on operating temperature (ambient temperature) T as shown in FIG. 70 (A), and FIG. 78 (B) with respect to external power supply voltage extVcc. Voltage VccQ having a negative dependency characteristic is applied onto power supply node 300 as shown in FIG. Next, the voltage V having such characteristics
The effect of ccQ will be described.

As described with reference to FIGS. 56 to 59, generally, when the operating temperature rises, the operating speed of the MOS transistor decreases due to the generation of thermoelectrons in the channel region, while the gate potential or As the drain potential increases, the drain current increases and the operating speed increases (in the case of n-channel MOS transistor). When external power supply voltage extVcc rises, a voltage that changes in proportion to this external power supply voltage extVcc is supplied to power supply node 3
When it is applied to 00, the operating speed of the drive transistor 1 is increased. In this case, in the case where the potential of the output node 6 is precharged to the intermediate potential, the operating speeds of the drive transistor 2 and the drive transistor 1 are different, and the time required for outputting the "H" level signal is increased. And the time required for outputting the "L" level signal is different, and the operating characteristics of the output circuit deteriorate. In this case, the differential amplifier 460 is used to reduce the voltage VccQ applied to the power supply node 300, thereby suppressing an increase in the operating speed of the drive transistor 1 and increasing the access time when the "H" level signal is output. Can be suppressed, and the operating characteristics can be maintained constant. Similarly, when the ambient temperature (operating temperature) T rises,
Although the operating speeds of drive transistors 1 and 2 decrease, in this case, power supply voltage VccQ on power supply node 300 is reduced.
Drive transistor 1 by increasing
It is possible to compensate for the decrease in the operating speed of, and it is possible to hold the output signal determination timing constant.

In the structure shown in FIG. 76, a level conversion circuit is used to apply a voltage at the level of voltage VccQ, which changes similarly to voltage VccQ, to the gates of drive transistors 1 and 2. It is possible to obtain a stable output circuit that can make the output signal determination timing constant regardless of the voltage extVcc and the ambient temperature (operating temperature) T.

FIG. 79 is a diagram schematically showing an overall structure of a semiconductor device to which the present invention is applied. Referring to FIG. 79, the semiconductor device includes a step-down circuit 480 that generates a constant internal voltage Vcc that does not depend on external power supply voltage extVcc within a predetermined range of external power supply voltage extVcc.
An internal power supply use circuit 482 which operates using internal power supply voltage Vcc applied on internal power supply line 303 and ground voltage GND applied on ground line 302 as both operating power supply voltages, and applied to power supply node 300 from step-down circuit 480. An external power supply voltage extVcc and a ground voltage GND applied to ground node 302 are used as both operating power supply voltages, and an input / output circuit 484 is provided for providing an interface with the outside of the device. In the case of the configuration shown in FIG. 79, the components included in the system outside the apparatus operate with external power supply voltage extVcc as the operating power supply voltage. Therefore, in this case, in order to interface with an external device, input / output circuit 484 uses external power supply voltage extVcc as its operating power supply voltage. By applying the configuration shown in FIG. 76 to the output circuit included in this input / output circuit 484, a stable output signal independent of the external power supply voltage extVcc and the ambient temperature (operating temperature) can be generated. The signal output timing can also be constant.

In the structure shown in FIG. 76, power supply voltage VccQ applied to power supply node 300 may be applied not only to drive transistor 1 but also to drive circuit 450. In this output circuit 926, drive circuit 450 may be provided with a circuit for converting the level of internal power supply voltage Vcc to the level of external power supply voltage extVcc and applying it to the gates of drive transistors 1 and 2.

As described above, according to the eleventh embodiment of the present invention, the power supply node of the output circuit maintains a positive dependence on the ambient temperature and has a negative dependence on the external power supply voltage. Since it is configured to transmit voltage, it is necessary to generate an output circuit that compensates for changes in the operating characteristics of the drive transistor due to fluctuations in ambient temperature and external power supply voltage, and that stably generates an output signal with no ringing at a fixed timing. You can

Needless to say, this 11th
In the output circuit of this embodiment, the configurations of different output node drive timings in the first to sixth embodiments may be used in combination.

[Embodiment 13] FIG. 80 shows the first embodiment of the present invention.
It is a figure which shows the structure of the principal part of the output circuit which is a 2nd Example. In the structure shown in FIG. 80, power supply node 300 of output circuit 926 is activated in response to clock signal φCK in order to apply voltage VccQ to power supply node 300.
Differential amplifier 490 that differentially amplifies upper voltage VccQ and reference voltage VREFa is coupled between power supply node (internal power supply voltage supply node or external power supply voltage supply node) and power supply node 300, and differential amplifier 490 is connected. Output signal C
P channel MOS transistor 492 supplying current from power supply voltage supply node 491 to power supply node 300 in response to 1 and n channel MOS transistor discharging power supply node 300 to the level of ground voltage GND in response to clock signal / φCK. A switching transistor 494 including a transistor is provided.

Clock signal φCK is activated, for example, when output permission signal OEM is activated. This clock signal φCK may be activated in response to a signal giving the operation timing of output circuit 926. The operation of the circuit shown in FIG. 80A will now be described with reference to the operation waveform diagram of FIG. 80B.

Clock signal φCK is inactive and is at "L"
At this time, differential amplifier 490 is inactive, its output signal C1 is at the level of voltage Vcc applied to power supply voltage supply node 491, and drive transistor 492 is off. On the other hand, the clock signal / φCK is “H”
, The switching transistor 494 is in the ON state, and the voltage VccQ on the power supply node 300 is the ground voltage G.
It is at the ND level. In this state, drive transistors 1 and 2 included in output circuit 926 are both off, and output node 6 is precharged to the intermediate voltage level or maintained in the state of the output signal read in the previous cycle. Output (set to output high impedance state).

When a new data signal is read, clock signal φCK attains an active "H" level at the same time as or earlier than output enable signal OEM, and differential amplifier 490 is activated. on the other hand,
The clock signal / φCK becomes "L", and the switching transistor 494 is turned off. Power node 30
When the voltage VccQ on 0 is lower than the reference voltage VREFa, the output signal C1 from the differential amplifier 490 drops from the “H” level (voltage Vcc level), and the drive transistor 492 is turned on. A current is supplied from the power supply voltage supply node 491 to the power supply node 300,
The voltage VccQ is increased. At this time, if the current driving capability of drive transistor 492 is adjusted to an appropriate value, voltage VccQ on power supply node 300 gradually rises. The voltage VccQ on the power supply node 300 is the reference voltage V
When it becomes higher than REFa, the output signal of the differential amplifier 490 becomes the “H” level and the drive transistor 492.
Is turned off. As a result, voltage VccQ on power supply node 300 is maintained at the voltage level of reference voltage VREFa.

In output circuit 926, drive transistor 1 is turned on when a signal of "H" is output, and current is supplied from power supply node 300 to output node 6. At this time, the change in the voltage level on output node 6 is substantially the same as the change in voltage VccQ at power supply node 300. The rate of change of voltage VccQ on power supply node 300 is determined by the current drivability of drive transistor 492 and the parasitic capacitance associated with power supply node 300. The parasitic capacitance in the power supply node 300 is a value specific to the circuit and is substantially constant. Therefore, by adjusting the current drivability of drive transistor 492 to an appropriate value, the changing speed of voltage VccQ can be adjusted to an appropriate value, and accordingly, the ringing of output signal Q at output node 6 can be prevented. Can be suppressed.

At this time, if the changing speed of the output signal C1 of the differential amplifier 490 is adjusted, the current driving force of the drive transistor 492 can be changed at an appropriate speed, and the output signal Q of the output node 6 is accordingly changed. The rate of change of can be made gentle so that ringing does not occur.

Further, the reference voltage VREFa is applied to the output node 6
Is set to a voltage level that does not cause ringing when driven at a high speed, output node 6 can reach the voltage level of reference voltage VREFa at a relatively high speed. At this time, if another circuit is used to increase the voltage on power supply node 300 to the level of power supply voltage Vcc, output signal Q can be output at high speed and stably without causing ringing.

The reference voltage VREFa may have a voltage level higher than the high level voltage VOH of the output signal defined by the specifications.

As described above, according to the twelfth embodiment of the present invention, voltage VccQ applied to the power supply node of output circuit 926 is activated in response to a signal giving the operation timing of this output circuit. Since the differential amplifier and the drive transistor that supplies a current from the power supply voltage supply node to the power supply node in response to the output signal of the differential amplifier are provided, the output signal appearing at the output node on this power supply node 300 is provided. The voltage VccQ can be changed according to the changing speed, and an output signal can be stably generated at high speed without causing ringing.

[Embodiment 14] FIG. 81 shows the first embodiment of the present invention.
It is a figure which shows roughly the structure of the part relevant to the data signal output of the semiconductor device which is an Example of 3. FIG. 81, a semiconductor device 500 includes a memory cell array 501 and 502 each including a plurality of memory cells arranged in rows and columns, and an internal data bus for amplifying data in the memory cell selected in the memory cell arrays 501 and 502. Includes a data bus amplifier 504 that communicates over 506. A configuration may be used in which memory cell arrays 501 and 502 are simultaneously activated, a memory cell is selected from each of them, and data of the selected memory cell is read. Even if only one of the memory cell arrays 501 and 502 is activated, a memory cell is selected in the activated memory cell array and the selected memory cell data is read. Good.

In this semiconductor memory device 500, a plurality of bits of data signals are output, and therefore a plurality of pads 510a to 510c and 510d to 510f are arranged. Internal data bus 506 and pads 510a-501
output circuits 926a to 926c and 926d to 926 corresponding to pads 510a to 510f, respectively.
f is arranged. As shown in FIG. 81, the length of internal data bus 506 from data bus amplifier 504 to output circuits 926a to 926f is different. 81, in the semiconductor device 500, the output circuits 926a to 926c.
And output circuits 926d-926f are shown as being symmetrically arranged. In that case, the internal data bus 5 between the data bus amplifier 504 and the output circuits 926a and 926d.
06 is the shortest, and output circuits 926c and 926
internal data bus 50 between f and the data bus amplifier 504
The length of 6 is the longest.

Output circuits 926a to 926c have their time constants for generating output signal Q reduced as the distance from data bus amplifier 504 increases (as the length of internal data bus 506 increases), and output signals Q The rate of change is increased. Similarly, output circuits 926d to 926
Also in f, as the distance from the data bus amplifier 504 becomes longer, the time constant of the output signal Q becomes smaller.

When drive transistors for driving a plurality of output nodes are provided in parallel, and when the on timings of the plurality of drive transistors are made different, the time difference of the on timings of the drive transistors in the output circuit 926a is It is made larger than that in the output circuit 926c. Similarly, the output circuit 926
The time difference between the ON timings of the plurality of drive transistors in d is made larger than that of the output circuit 926f. Next, the operation will be described.

First, the operation in the case where the time constant of the output signal is made smaller as the distance from data bus amplifier 504 becomes longer will be described with reference to FIG. 82 (A). In FIG. 82A, in the case where output signals Qa and Qc change from "L" to "H" in accordance with internal data signal IQa applied to output circuit 926a and internal data signal IQc applied to output circuit 926c, respectively. The operation is shown. Data bus amplifier 504 is activated in response to a preamplifier enable signal (not shown), and memory cell array 501 and / or 50 is activated.
The data of the plurality of memory cells selected in 2 is amplified, and the amplified plurality of bits of memory cell data are transmitted to the internal data bus 506. As a result, the internal signals IQa and IQc on the internal data bus 506 are transmitted at the time ta.
Varies according to this amplified signal. The longer the length of internal data bus 506, the greater its parasitic capacitance and wiring resistance, and therefore internal data signal IQa changes relatively faster than internal data signal IQc. Fig. 82
In (A), internal data signal IQ is obtained at time tb.
The state where a reaches the predetermined voltage level "H" level is shown. Output circuits 926a-926c and 926d
.About.926f are activated at the same timing according to output enable signal OEM (not shown). Output circuit 926
The current driving force of a is small, and the output signal Qa
Of the output signal Qa is relatively slow. On the other hand, the output circuit 926c
Has a smaller time constant of its output signal Qc, that is, the current driving capability of the output circuit 926c is made relatively larger, and the output signal Qc according to the internal data signal IQc.
Changes relatively fast. Internal data signal IQa changes at a high speed, and the current driving capability of output circuit 926a is reduced. Therefore, output signal Qa from output circuit 926a changes relatively gently. On the other hand, in output circuit 926c, internal data signal IQc changes relatively gently, but the current driving capability of this output circuit 926c is increased. The signal Qc changes relatively quickly. Accordingly, the changing speeds of the output signals Qc and Qa of the output circuits 926c and 926a can be the same, and the definite state can be set at almost the same timing.

In FIG. 82A, a state in which data output signals Qa and Qc are set to the definite state at time tc is shown as an example. At this time, the output circuit 926 receives the internal data signal IQa that changes at high speed.
The current driving power of a is small, and the internal data signal I
Even if Qa changes at high speed, the occurrence of ringing is suppressed in this output signal Qa. On the other hand, output circuit 926 receiving internal data signal IQc that changes relatively slowly.
In c, although the current driving force is increased,
The rate of change of the internal data signal IQc is slow,
By generating the signal Qc with a large current driving force, it is possible to compensate for the gradual change of the internal data signal IQc and generate the output signal Qc at high speed. At this time, even if the current driving capability of output circuit 926c is increased, if the change in the output signal level of the AND circuit included in the output circuit 926c follows the change speed of internal data signal IQc, the output signal Qc can generate the output signal Qc at high speed without causing ringing. This is a series of operations, and the pads 510a ...
Output signals that are in a stable definite state are generated at 510c and 510d to 510f at substantially the same timing.

Now, with reference to FIG. 82B, the operation will be described in the case where the output circuit includes two drive transistors and these two drive transistors are turned on at different timings. This FIG. 82 (B)
Also shows the data input / output relationship of output circuits 926a and 926c. Also in FIG. 82B, internal data signals IQa and IQc are both "H".
An example is shown in which the output signals Qa and Qc from output circuits 926a and 926c both change to "H" level.

Data bus amplifier 504 is activated and internal data signals IQa and IQa on internal data bus 506 are activated.
When Qc changes, the output circuit 926a ...
926c and 926d to 926f are activated. Internal data signal IQa to output circuit 926a is brought to a stable state at time tb. At this time, the output circuit 926a outputs the output signal Qa with a relatively small driving force. Therefore, the data signal Qa changes relatively gently (the transistor having a small driving force is charged). Next, at time te, the output circuit 926
The drive transistor having a large driving force included in a is turned on, and output signal Qa is charged at a high speed to a predetermined voltage level. At this time, the output signal Qa has its voltage level sufficiently changed to a voltage level at which ringing does not occur. Therefore, even if the internal signal Qa is driven to a predetermined voltage level at high speed, ringing does not occur,
It is possible to obtain a stable output signal. On the other hand, internal data signal IQc changes relatively gently. In this case, the output circuit 926c first turns on the drive transistor having a small driving force to charge the output signal Qc. At time td, a drive transistor having a large current driving capability is turned on in output circuit 926c, and its output signal Qc is charged at high speed. At this time,
The internal data signal IQc changes relatively slowly,
Therefore, even if the output circuit 926c changes the output signal Qc with a large driving force, the drive transistor 1
The signal voltage level applied to the internal data signal I
Due to the gradual change of Qc, the voltage level has not yet reached a sufficiently high voltage level (predetermined final voltage level), so that the output node is driven relatively gently and the output signal Qc is output at high speed without causing ringing. Drive to a predetermined voltage level. When internal data signal IQc reaches the predetermined voltage level, finally output signal Qc reaches the predetermined voltage level in accordance with this internal data signal IQc.

As shown in FIGS. 82 (A) and 82 (B), the magnitude of the current driving capability of the output circuit and the time difference between the on timings of the plurality of drive transistors are adjusted according to the distance from data bus amplifier 504. By doing so, the timings at which the output signals from all the output circuits are in the definite state can be made substantially the same without causing ringing, and a semiconductor memory device with a short access time can be realized.

In the signal waveform diagrams shown in FIGS. 82A and 82B, when the data bus amplifier 504 is activated, the output circuit is also activated at the same time. However, after the data bus amplifier 504 is activated and the internal data of the data bus 506 is almost determined, the output circuits 926a to 926f are activated (the output enable signal OEM is activated).
Also in the configuration, the time difference between the activation timing of data bus amplifier 504 and the activation timing of output circuits 926a to 926f can be shortened, and accordingly, a semiconductor memory device having a short access time can be realized.

[Modification 1] FIG. 83 shows a thirteenth embodiment of the present invention.
It is a figure which shows the structure of the modification of the Example of this. In FIG. 83, the semiconductor device 500 is housed in the package 550. This package 550 has an external lead terminal 515a.
~ 515c and 515d-515f are arranged. These external lead terminals 515a to 515f are pads 510a to 510c and 510d to 5 of the semiconductor device 500.
10f is connected via a lead frame and a bonding wire. In FIG. 83, pads 510a-5
10f and the external lead terminals 515a to 515f are a combination of these bonding wires and lead frames.
Shown by two straight lines. In the semiconductor device, the length of the lead frame differs depending on the shape of this package. Figure 83
, The distance lf between the pad 510 (510a to 510f) and the external lead terminal 515 (515a to 515f) and the distance ld between the data bus amplifier 504 and the pad 510 (the output circuit is shown in FIG. 83). The current drivability of the drive transistor in the output circuit and the time difference between the on timings of the plurality of drive transistors are adjusted in accordance with the distance of (1). That is, for example, the smaller the sum of the distance ld of the internal data bus 506 and the total distance lf of the bonding wire and the lead frame, the larger the time constant of the output signal Q output from the output circuit, and the slower the changing speed thereof (drive transistor). To reduce the current driving force). Alternatively, the smaller the sum of the distances ld and lf, the larger the time difference between the on timings of the plurality of drive transistors. If the length lf of the lead frame and the bonding wire is long, the load to be driven by the output circuit becomes large and the change speed of the output signal becomes small. Therefore, the driving force of the output circuit is increased as the distance lf is increased to compensate for this large load and change the output signal at high speed. This configuration allows all output signals from all output circuits to reach a stable state at the same timing without causing ringing, regardless of the length of the sum of the distance of the internal data bus and the distance of the wire bonding and the lead frame. It is possible to obtain a semiconductor memory device that can do this.

When the signal delay in the internal data bus is not so large as to the input / output characteristics of the output circuit by the length of the bonding wire and the lead frame, the driving force of the output circuit is The time constant of the output signal Q may be determined according to the length of the frame length lf.

As described above, according to the thirteenth embodiment of the present invention, the current drivability of the drive transistor according to the input and output loads (length of internal data bus and output signal line) of each output circuit. By adjusting the time difference between the timings of turning on or off a plurality of the drive transistors, or a plurality of the drive transistors, it is possible to obtain a semiconductor device operating at high speed in which all output circuits are brought into a definite state at substantially the same timing without causing ringing.

[Embodiment 15] FIG. 84 shows the first embodiment of the present invention.
It is a figure which shows the structure of the principal part of the output circuit which is a 4th Example. FIG. 84 shows a structure of a portion for discharging the output node to the ground voltage level. A similar structure may be provided for the portion charging output node 6 to the voltage level on power supply node 561. In FIG. 84, the output circuit includes a drive element 562 having a small current driving force for discharging output node 6 to the level of ground voltage GND in response to internal signal NOL1, and a drive element which is activated at a timing later than internal signal NOL1. It includes a drive element 564 having a large current driving capability for discharging output node 6 to the ground voltage level in response to signal NOL2. Output node 6 is connected to pad 560. Drive element 564 having a large current driving force is arranged at a position close to pad 560. In FIG. 84, this drive element 562
Drive transistors 2a and 2b are shown representatively, since and 564 may include a resistance element inside and various configurations described in the previous embodiments can be applied.

The drive transistor 2b having a large current driving capability is the drive transistor 2a having a small current driving capability.
Its channel width is made larger than that of. That is, the junction area between the impurity region connected to output node 6 and the substrate region is larger in drive transistor 2b than in drive transistor 2a. Similarly, the area of the gate insulating film of the drive transistor 2b is larger than that of the drive transistor 2a. Therefore, even when the same voltage is applied between the drain gates and drain sources of drive transistors 2a and 2b, drive transistor 2b has a smaller drain electric field and accordingly a higher junction breakdown voltage. Similarly, in the drive transistor 2b having a wider gate insulating film, the inter-electrode electric field of the capacitor, which becomes larger than the withstand voltage of the drive transistor 2a, is inversely proportional to the capacitor area). When the resistance element is used, the voltage drop of the resistance element having a large resistance value becomes large.

Therefore, when the structure shown in FIG. 84 is used, when a large noise such as a surge voltage occurs in output pad 560, the excessive noise is absorbed by drive transistor 2b having a large junction breakdown voltage or insulation breakdown voltage, and the junction breakdown voltage is absorbed. Is prevented and excessive noise is prevented from being applied to the drive transistor 2a having a small gate voltage and / or a small withstand voltage. This makes it possible to obtain an output circuit with excellent resistance to excessive noise without providing any special protection device.

In the structure shown in FIG. 84, power supply node 561 may be supplied with power supply voltage Vcc, and voltage VccQ output from another power supply circuit as described in the previous embodiment. May be given.

The number of drive elements connected in parallel to this output node may be larger than two, in which case the drive element having the largest electrode driving force is arranged at the position closest to output pad 560. Good.

As described above, according to the fourteenth embodiment of the present invention, when a plurality of drive elements are provided and the current drive strengths of the plurality of drive elements are different, the largest current drive capacity is obtained. By arranging the drive element with the drive element closest to the output pad, excessive noise such as surge voltage generated on the output pad is absorbed by the drive element with a large current driving force. It is possible to obtain a highly reliable output circuit excellent in noise resistance without providing.

[Embodiment 16] FIG. 85 shows the first embodiment of the present invention.
It is a figure which shows the structure of the principal part of the output circuit which is a 5th Example. FIG. 85 shows a structure of a portion for discharging output node 6 to the ground voltage level. A similar configuration can be provided for a portion (transistor 1 is representatively shown) for charging output node 6 to the voltage level on power supply node 561. Transistor 1 is shown as protected by protection circuit 570.

In FIG. 85, the output circuit includes a plurality of drive elements connected in parallel to output node 6 and having different current driving capabilities. In FIG. 85, only drive element 562 having the smallest current driving force is shown. The drive element 562 is applicable in various configurations as in the previous embodiment, and only the drive transistor 2a is shown as a representative. Output node 6 is connected to output pad 560. The drive element 562 and the power supply pad 560 having a small current driving force
A protection circuit 570 is provided at the position of the output node between. The protection circuit 570 is, for example, a power supply node 561.
And diode 571 having a cathode connected to output node 6 and an anode connected to output node 6, and a cathode connected to output node 6 and an anode connected to receive ground voltage GND. The drive element having a large current driving force may be provided at any of positions F and G shown by arrows in FIG. Drive element and output pad 560 that may be destroyed by excessive noise such as surge voltage with small current driving force
The protection circuit 570 may be provided between the two. This Figure 85
In the case of the configuration shown in (1), when the positive excessive noise is generated in the output pad 560, the diode 572 conducts, the positive excessive noise is discharged to the power supply node 561, and the excessive noise is absorbed. On the other hand, when the negative excessive noise is generated, the diode 574 becomes conductive and charges the negative excessive voltage to the ground voltage level. As a result, it is possible to prevent excessive noise such as positive and negative surge voltages from being absorbed by the protection circuit 570 and destroy the drive transistor 2a having a small junction breakdown voltage and dielectric breakdown voltage due to excessive noise. The same applies when a resistance element is used.

The structure shown in FIG. 85 may be combined with the structure in which power supply node 561 is supplied with voltage VccQ. Note that the protection circuit 570 is shown to be formed of a diode, but any structure can be used as long as it is a circuit having a protection function of absorbing excessive noise such as a surge voltage.

The output charging transistor 1 is provided in the subsequent stage of the protection circuit 570. However, when the transistor 1 has a relatively large current driving force, it is provided between the protection circuit 570 and the pad 560. It may be provided.

As described above, according to the fifteenth embodiment of the present invention, since the protection circuit for absorbing excessive noise is arranged between the drive element having a small current driving force and the output pad, the output pad is interposed. Even if excessive noise is generated at the output node, such excessive noise is absorbed by the protection circuit, and it is prevented that excessive noise is transmitted to the drive element with a small current driving force. Can be prevented from being destroyed by excessive noise, and an output circuit having excellent resistance to excessive noise can be obtained.

Although the first to fifteenth embodiments of the present invention have been described in detail above, these embodiments may be appropriately combined and used in the application.

Further, in the above-described embodiments, as the data output configuration, as an example, the case where the inverted data of the data in the memory cell is transmitted to the data output system is shown.
However, the present invention is not limited to this, and the configuration of the present invention can be applied to the case where non-inverted data is transmitted or the case where both complementary data pairs of inverted data and non-inverted data are transmitted to the data output system through a pair of data lines. Can be applied.

Furthermore, in the above-described embodiment, the configuration in which the output data of "L" level is output is mainly described, but the present invention is also applied to the route of outputting the data of "H". be able to.

In the above embodiment, one output circuit is mainly described. However, even in the multi-bit parallel output structure, the structure of the present invention can be applied to the output system of each bit. The data output node and the data input node may be shared or may be separately provided.

Further, in the above-mentioned embodiments, the output circuit is shown to be composed of only n-channel MOS transistors, but a CMO using both n-channel MOS transistors and p-channel MOS transistors.
The same can be applied to the output circuit including the S circuit.

[0492]

According to the first aspect of the present invention, since the output node is set to the intermediate potential level when the output enable signal is inactivated, the amplitude of the output signal becomes small and ringing is effectively generated. Can be prevented.

According to the second aspect of the invention, the logic of the output signal is discriminated, and the potential of the output node is set to the potential level direction of the logic different from the logic of the output signal when the output signal is invalidated according to the discrimination result. It is changing. Therefore,
Even if the next output signal has the opposite logic to the logic of the previous output signal, the amplitude of the output signal can be reduced, and ringing can be effectively prevented.

According to the invention of claim 3, as the potential of the output node changes, the driving force of the drive element for driving the output node is increased according to the degree of the change. Therefore, the output node is not rapidly driven, and the output node is driven at a high speed at a potential level where ringing does not occur, so that the occurrence of ringing can be reliably prevented without increasing the access time. .

According to the invention of claim 4, the on-timing of the drive element for driving the output node at a relatively high speed is adjusted according to at least one of the operating voltage and the operating temperature. That is, when the driving force of the drive element increases in an operating environment such as when the power supply voltage becomes high or the operating temperature becomes low,
The on-timing is delayed. Therefore, the on-timing can be adjusted according to the current driving force of the drive element, and the occurrence of ringing can be reliably prevented without increasing the access time.

According to the invention of claim 5, the on-timing of the drive element for driving the output node at a relatively high speed is adjusted according to the output permission signal and the output instruction signal. Therefore, the time for which the invalid output signal is output can be shortened, and even when the invalid output signal is output, the potential amplitude of the output node can be reduced, and the access time can be reduced without increasing. It is possible to prevent ringing from occurring.

According to the sixth aspect of the present invention, the drive transistor responds to the internal signal by supplying the voltage to be transmitted to the output node to the reference power supply node at the first speed from the voltage supply source according to the output enable signal. Since the current is supplied to the reference power supply node and then the second current supply element supplies the current to the reference power supply node at the second speed higher than the first speed, the drive transistor Since the voltage on this reference power supply node is transmitted to the output node during the conduction of, the voltage on the output node changes gradually according to the voltage on this reference power supply node, and then when it reaches a voltage level where ringing does not occur. , The voltage of the output node changes at high speed,
A stable output signal can be obtained without ringing at the output node.

According to the seventh aspect of the invention, the gate means having different delay times according to the presence / absence of the invalid output and the delay of the gate means with respect to the reference power supply node for supplying the voltage to be transmitted to the output node by the drive transistor. Adjusting means for setting the time and changing the voltage of the reference power supply node at a first speed in response to the activation state of the output signal of the gate means, and then at a second speed faster than the first speed The voltage that appears at the output node is gradually changed when there is a possibility of ringing regardless of the presence or absence of an invalid output, and the possibility of ringing is reduced. It is possible to change the voltage of the output node at high speed and generate a stable output signal without ringing. That.

According to the eighth aspect of the present invention, in the output circuit according to the sixth or seventh aspect, the second current driving element supplies the voltage transmitted to the reference power supply node by the first current driving element to the reference power supply node. Since the voltage which is closer to the second logic than the voltage of the first logic to be transmitted is configured, overdrive in the first current driving element can be surely prevented, and the occurrence of ringing is stably suppressed. And second
It is possible to drive the output node at high speed by the current driving element, and it is possible to obtain an output circuit that operates at high speed and stably.

According to the ninth aspect of the present invention, a plurality of drive transistors arranged in parallel with each other are formed of insulated gate field effect transistors at the output node, and the threshold voltage of the plurality of insulated gate field effect transistors is increased. And the substrate bias potential are made different from each other, and the configuration is such that the insulated gate field effect transistor with a large absolute value of the threshold voltage or the absolute value of the substrate bias potential is turned on sequentially, so that the output node has a current driving force. Starting from a small insulated gate field effect transistor having a small size, the output signals can be generated at high speed without causing ringing.

According to the tenth aspect of the present invention, the resistance element and the switching element are connected in parallel to the output node, the switching element and the resistance element are both connected to the drive transistor, and the resistance element and the drive transistor are initially connected. Since the output node is driven via the switching element and the resistance element is short-circuited by the switching transistor, the output node is first driven gently by the current limiting function of the resistance element, and then the resistance element is short-circuited by the switching transistor. Since the output node is driven at a high speed, the output node is gently driven when there is a possibility of ringing, so that an output signal can be generated at a high speed while suppressing the occurrence of ringing.

According to the eleventh aspect of the present invention, a plurality of resistance elements having different resistance values are connected to the output node, and a drive transistor is connected to each of the plurality of resistance elements to form a resistance element having a large resistance value. Since the drive transistors are configured to be turned on sequentially from the connected drive transistors, the output node is driven slowly at first by the current limiting function of the resistance element, and then gradually at high speed. Since it is driven gently, it is possible to obtain an output circuit capable of generating an output signal at an output node at high speed while suppressing the occurrence of ringing.

According to the twelfth aspect of the invention, there is provided a second reference having a constant reference voltage having no dependency on the external power supply voltage and the temperature and a second reference having a negative dependency on the external power supply voltage and a positive temperature coefficient. A differential amplifier that differentially amplifies the reference voltage;
Since the current supply transistor that supplies the current from the external power supply node to the reference power supply node according to the output signal of the differential amplifier is provided, it is possible to compensate for the decrease in the operating speed of the output drive transistor when the ambient temperature (operating temperature) rises and The increase in the operating speed of the output drive transistor when the power supply voltage rises can be compensated to ensure that the output signal is always in a definite state at a fixed timing, and the current limiting function of this current supply transistor allows the voltage on the output node to increase rapidly. Therefore, it is possible to obtain an output circuit that can prevent the output signal from being changed to, and can reliably generate an output signal at high speed without causing stable ringing.

According to the thirteenth aspect of the invention, the drive element is activated in response to the clock signal which gives the output timing of the internal signal to the first power supply node which gives the voltage transmitted to the output node, Comparing means for comparing the voltage of the first power supply node with a reference voltage; and a transistor element for causing a current flow between the second power supply node and the first power supply node according to an output signal of the comparing means. Since the drive element is turned on, the voltage change speed of the first power supply node can be set to an appropriate value by the current limiting function of the transistor element and the time constant of the output signal of the comparison means, and ringing can be performed. It is possible to obtain an output circuit that can stably generate an output signal at high speed without causing a noise.

According to the fourteenth aspect of the present invention, a bus amplifier which amplifies a plurality of bits of memory cell data in parallel and outputs the amplified data to an internal data bus, and an output signal amplified by this bus amplifier are buffered and externally output. In a semiconductor device having a plurality of output circuits for outputting to a node, the time constant that determines the changing speed of the output signal of each of the plurality of output circuits is shortened as the distance between the output node and the bus amplifier increases. Therefore, the larger the input load and output load of the output circuit, the smaller the time constant of the output signal of the output circuit. Accordingly, compensate for the decrease in the changing speed of the input signal and the output signal and generate the output signal at high speed. In addition, each output circuit can generate an output signal that is in a definite state at almost the same timing, and a semiconductor device that operates stably and at high speed can be provided. Rukoto can.

According to the fifteenth aspect of the present invention, in an output circuit having a plurality of drive elements provided in parallel at the output node and having different driving forces, a drive having a larger current driving force than a drive element having a small current driving force Since the element is located near the output pad, excessive noise such as surge voltage generated on the output pad is absorbed by the drive element with large current driving force, and the drive element with small current driving force is destroyed by excessive noise. It is possible to obtain an output circuit that is prevented from being damaged and that operates stably and has excellent noise resistance.

According to the sixteenth aspect of the present invention, in the output circuit having a plurality of drive elements connected in parallel with each other to the output signal line between the output node and the output pad and having different current driving capabilities, Since a protection circuit for absorbing excessive noise voltage such as surge voltage is provided between the drive element with small force and the output pad, the drive element with small current driving force is destroyed by excessive noise such as surge voltage generated on the output pad. Can be prevented, and an output circuit with excellent resistance to excessive noise can be obtained.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an output control circuit according to a first embodiment of the present invention.

FIG. 2 is a signal waveform diagram showing an operation of the output control circuit shown in FIG.

FIG. 3 is a diagram showing a first modification of the first embodiment of the present invention.

FIG. 4 is a diagram for explaining the operation of the output control circuit shown in FIG.

5 is a diagram showing a configuration of an output permission signal generation circuit shown in FIG.

6 is a signal waveform diagram representing an operation of the output permission signal generating circuit shown in FIG.

FIG. 7 is a diagram showing a second modification of the first embodiment of the present invention.

FIG. 8 is a diagram showing a third modification of the first embodiment of the present invention.

FIG. 9 is a diagram showing a configuration of an output control circuit according to a second embodiment of the present invention.

10 is a signal waveform diagram representing an operation of the output control circuit shown in FIG.

11 is a signal waveform diagram representing an operation of the output control circuit shown in FIG.

FIG. 12 is a diagram showing a modification of the second embodiment of the present invention.

13 is a signal waveform diagram representing an operation of the output control circuit shown in FIG.

FIG. 14 is a diagram showing a timing relationship between an output instruction signal and an output permission signal and a relationship between output signals appearing at that time.

FIG. 15 is a diagram for explaining a timing relationship between an output instruction signal and an output permission signal and a relationship between output data signals.

FIG. 16 is a diagram showing a configuration of an output control circuit according to a third embodiment of the present invention.

17 is a signal waveform diagram representing an operation of the output control circuit shown in FIG.

FIG. 18 is a signal waveform diagram showing the structure and operation of the first modification of the third embodiment of the present invention.

FIG. 19 is a diagram showing a configuration of a second modification of the third exemplary embodiment of the present invention.

FIG. 20 is a diagram showing the configuration of a third modification of the third exemplary embodiment of the present invention.

FIG. 21 is a diagram showing a modified example of the NAND circuit shown in FIG. 20.

22 is a signal waveform diagram representing an operation of the circuit shown in FIG.

FIG. 23 is a diagram showing a configuration of an output control circuit according to a fourth embodiment of the present invention.

24 is a signal waveform diagram representing an operation of the output control circuit shown in FIG.

FIG. 25 is a diagram showing a first modification of the output control circuit according to the fourth embodiment of the present invention.

FIG. 26 is a signal waveform diagram representing an operation of the output control circuit shown in FIG.

FIG. 27 is a diagram showing a second modification of the output control circuit according to the fourth embodiment of the present invention.

28 is a signal waveform diagram representing an operation of the output control circuit shown in FIG.

FIG. 29 is a diagram showing a third modification of the output control circuit according to the fourth embodiment of the present invention.

30 is a signal waveform diagram representing an operation of the output control circuit shown in FIG.

FIG. 31 is a diagram showing a fourth modification of the output control circuit according to the fourth embodiment of the present invention.

32 is a signal waveform diagram representing an operation of the output control circuit shown in FIG.

FIG. 33 is a diagram showing a fifth modification of the output control circuit according to the fourth embodiment of the present invention.

FIG. 34 is a diagram showing a sixth modification of the output control circuit according to the fourth embodiment of the present invention.

35 is a signal waveform diagram representing an operation of the output control circuit shown in FIG.

FIG. 36 is a diagram showing a seventh modification of the output control circuit according to the fourth embodiment of the present invention.

37 is a signal waveform diagram representing an operation of the output control circuit shown in FIG.

38 is a signal waveform diagram representing an operation of the output control circuit shown in FIG.

39 is a signal waveform diagram representing an operation of the output control circuit shown in FIG.

FIG. 40 is a diagram showing an eighth modification of the output control circuit according to the fourth embodiment of the present invention.

41 is a signal waveform diagram representing an operation of the output control circuit shown in FIG.

42 is a signal waveform diagram representing an operation of the output control circuit shown in FIG.

FIG. 43 is a diagram showing a ninth modification of the output control circuit according to the fourth embodiment of the present invention.

FIG. 44 is a diagram showing a tenth modification of the output control circuit according to the fourth embodiment of the present invention.

FIG. 45 is a diagram showing temperature and voltage dependence characteristics of the first control voltage used in the fifth embodiment of the present invention.

FIG. 46 is a diagram showing temperature and voltage dependence characteristics of a second control voltage used in the fifth embodiment of the present invention.

FIG. 47 is a diagram showing the structure of the components of the delay circuit used in the fifth embodiment of the present invention and the operating characteristics thereof.

FIG. 48 is a diagram showing another configuration example of the components of the delay circuit used in the fifth embodiment of the present invention and its operating characteristics.

FIG. 49 is a diagram showing still another configuration of the components of the delay circuit used in the fifth embodiment of the present invention and its operating characteristics.

FIG. 50 is a diagram showing a first application example of the fifth embodiment of the present invention and its operation waveform.

FIG. 51 is a diagram showing a second application example of the fifth embodiment of the present invention and its operation waveform.

FIG. 52 is a diagram showing a third application example of the fifth embodiment of the present invention and its operation waveform.

FIG. 53 is a diagram showing a fourth application example of the fifth embodiment of the present invention and its operation waveform.

FIG. 54 is a diagram schematically showing a circuit configuration for generating first and second control voltages.

FIG. 55 is a diagram showing a specific configuration of the VREF1 generation circuit shown in FIG. 54 and a voltage / temperature dependence characteristic of the first reference voltage.

56 is a diagram showing a specific configuration of the VREF2 generating circuit shown in FIG. 54 and a voltage / temperature dependence characteristic of a second reference voltage.

57 is a diagram showing input / output voltages of the differential amplifier circuit shown in FIG. 54.

FIG. 58 is a diagram showing the voltage / temperature dependence characteristic of the operating power supply voltage used in the modification of the fifth embodiment of the present invention.

FIG. 59 is a diagram showing a modified example of the fifth embodiment of the present invention and its operating characteristics.

FIG. 60 is a diagram schematically showing a configuration of an output circuit according to a sixth embodiment of the present invention.

61 is a diagram schematically showing a configuration of the output circuit shown in FIG. 60. FIG.

62 is a diagram showing a configuration of the voltage regulator shown in FIG. 60. FIG.

63 is a signal waveform diagram representing an operation of the voltage regulator shown in FIG. 62.

FIG. 64 is a diagram showing a first modification of the sixth embodiment of the present invention.

FIG. 65 is a diagram schematically showing a configuration of an output circuit in a first modification of the sixth embodiment of the present invention.

FIG. 66 is a diagram showing the structure of a voltage regulator in the output circuit of the seventh embodiment of the present invention.

67 shows the adjustment voltages Vccp and Vb shown in FIG. 66.
It is a figure which shows the structure of an sg generation circuit.

FIG. 68 is a diagram showing the structure of the output circuit of the eighth embodiment of the present invention.

69 is a signal waveform diagram representing an operation of the output circuit shown in FIG. 68.

70 is a signal waveform diagram representing an operation of the output circuit shown in FIG. 68.

FIG. 71 is a diagram showing the structure of an output circuit according to a ninth embodiment of the present invention.

FIG. 72 is a diagram showing a modification of the ninth embodiment of the present invention.

FIG. 73 is a diagram showing the structure and operation of the output circuit of the tenth embodiment of the present invention.

FIG. 74 is a diagram showing the structure and operation of a modification of the tenth embodiment of the present invention.

FIG. 75 is a diagram showing the structure and operation of the output circuit of the eleventh embodiment of the present invention.

FIG. 76 is a diagram showing the structure of an output circuit according to a twelfth embodiment of the present invention.

77 is a diagram showing the external power supply voltage and temperature dependence characteristics of the reference voltage VRF3 output from the reference voltage generating circuit shown in FIG.

78 is a diagram showing temperature and external power supply voltage dependency characteristics of power supply voltage VccQ appearing on the reference power supply node shown in FIG. 76. FIG.

FIG. 79 is a diagram showing an application example of the twelfth embodiment of the present invention.

FIG. 80 is a diagram showing the structure and operation of the output circuit of the thirteenth embodiment of the present invention.

FIG. 81 is a diagram showing the structure of a semiconductor device according to a thirteenth embodiment of the present invention.

82 is a waveform chart showing a signal output operation in the semiconductor device shown in FIG. 81. FIG.

FIG. 83 is a diagram showing a modification of the thirteenth embodiment of the present invention.

FIG. 84 is a diagram showing the structure of an output circuit according to a fourteenth embodiment of the present invention.

FIG. 85 is a diagram showing the structure of the output circuit of the fifteenth embodiment of the present invention.

FIG. 86 is a diagram schematically showing an overall configuration of a conventional dynamic semiconductor memory device.

FIG. 87 is a diagram showing a configuration of a conventional output circuit.

88 is a signal waveform diagram representing an operation of the output circuit shown in FIG. 87.

FIG. 89 is a diagram showing parasitic capacitance and parasitic inductance associated with an output node.

90 is a diagram for explaining ringing caused by the parasitic inductance shown in FIG. 89. FIG.

FIG. 91 shows a possible modification of the output control circuit.

92 is a signal waveform diagram representing an operation of the output control circuit shown in FIG. 91.

93 is a diagram showing the relationship between the output enable signal and the column address strobe signal shown in FIG. 91. FIG.

[Explanation of symbols]

1,1a, 1b Output drive transistor, 2,2
a, 2b output drive transistor, 6 output node, 12 delay circuit, 13 NAND circuit, 14 NAN
D circuit, 15 delay circuit, 16 NOR circuit, 17 inverting delay circuit, 18 NOR circuit, 19 inverting delay circuit, 2
0 NOR circuit, 21 OR circuit, 22 NAND circuit,
40a, 40b control block, 50 one-shot pulse generation circuit, 51 delay circuit, 52 one-shot pulse generation circuit, 56 flip-flop, 60a, 60
b Internal data line precharge transistor, 67p
Channel MOS transistor, 84 flip-flop, 87 delay circuit, 87a delay circuit, 88 delay circuit, 89 NAND circuit, 90 AND circuit, 91 N
OR circuit, 92 gate circuit, 93 flip-flop, 94 flip-flop, 95 delay circuit, 100
Output control circuit, 105 latch circuit, 106 latch circuit, 107 delay circuit, 108 delay circuit, 111
AND circuit, 113 NAND circuit, 114 delay circuit, 115 delay circuit, 116 NAND circuit, 117
Latch circuit, 121 NAND circuit, 122 latch circuit, 123 delay circuit, 125 delay circuit, 126
NAND circuit, 130 NAND circuit, 131 delay circuit, 132 latch circuit, 134 NAND circuit, 13
5 NAND circuit, 136 delay circuit, 137 delay circuit, 142 latch circuit, 143 delay circuit, 144
AND circuit, 145 NOR circuit, 146 delay circuit,
160, 160a, 160b Delay circuit, 161, Delay circuit, 230 Delay circuit, 231, 232, 233 Inverter circuit, 241, 242 Inverter circuit, 25
1 to 254 inverter circuit, 261 to 264 inverter circuit, 250 VREF1 generation circuit, 251 VR
EF2 generation circuit, 252 differential amplification circuit, 253 differential amplification circuit, 261 temperature compensation Zener diode, 27
1 constant current source, 272 n-channel MOS transistor, 273 resistance element, 290 differential amplifier circuit, 291
Inverter circuit, 922 input / output control circuit, 926 output circuit, 300 power supply node, 301 voltage regulator, 3
02 ground node, 304a, 304b power supply voltage applying circuit, 306a, 306b ground voltage applying circuit, 31
8, 319, 320, 321 drive transistor,
325 booster circuit, 327 level conversion circuit, 328,
329 drive transistor, 330, 331 drive transistor, 340 voltage regulator, 350 drive circuit, 360, 365 drive transistor, 384
Flip-flop, 387, 388 delay circuit, 2e,
2f, 2g drive transistor, 401, 402
Delay circuit, 404, 406 AND circuit, 1e, 1f,
1g drive transistor, 403, 404 delay circuit, 301a, 301b voltage regulator, 410 rising delay circuit, 412 switching transistor, 414
Resistance element, 420, 422 Rise delay circuit, 2h,
2i drive transistor, 424 switching transistor, 426 resistance element, 2j, 2k, 2l drive transistor, 430, 432, 434 resistance element, 440, 442 rise delay circuit, 460 differential amplifier (comparison circuit), 470 reference voltage generation circuit, 490
Differential amplifier, 492 drive element, 494 switching transistor, 504 data bus amplifier, 50
6 Internal data bus, 510a to 510f output pad, 515a to 515f external lead terminal, 560 output pad, 562, 564 drive element, 570 protection circuit, 926a to 926f output circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location 8839-5J H03K 19/094 B

Claims (16)

[Claims] 1. An output circuit for outputting a signal of a logic corresponding to the logic of an input signal appearing at an input node to an output node, wherein the output circuit outputs the signal according to the signal appearing at the input node when an output enable signal is activated. A drive element for driving the node to one of the first and second potential levels corresponding to the logic of the input signal; and, in response to inactivating the output enable signal, setting the output node to the first potential level. An output circuit comprising: a control unit that drives to a potential level intermediate between the first and second potential levels. 2. An output circuit for outputting a signal having a logic corresponding to the logic of an input signal appearing at an input node to an output node, wherein the output node outputs the signal of the input signal to the output node in response to activation of an output enable signal. Drive element means for driving to a potential level corresponding to the logic; and a determining means for determining the logic of the signal appearing at the output node in response to the transition of the output enable signal to the inactive state; Control means for driving the output node to a potential level corresponding to a logic different from the logic discriminated by the discriminating means for a predetermined period in response to the discrimination result output and the signal for invalidating the signal at the output node. An output circuit provided. 3. An output circuit for outputting a signal of a logic corresponding to the logic of an input signal given to an input node to an output node, the potential of the output node corresponding to the logic of the input signal according to the input signal. An output circuit comprising: a drive element that drives to a level; and a control unit that increases the drive force of the drive element as the potential of the signal at the output node approaches a potential corresponding to the logic of the input signal. 4. An output circuit for outputting a signal having a logic corresponding to the logic of an input signal applied to an input node to an output node, wherein the output node outputs the input signal to the output node in response to the input signal. A first drive element that drives at a first speed to a potential level corresponding to the logic of 1., a delay unit that delays the input signal, and a delay circuit that outputs the output node to the first node in response to an output of the delay unit. A second drive element for driving to a potential level corresponding to the logic of the input signal at a second speed higher than the speed of, and a length of delay time given to the input signal by the delay means, Adjusting means for adjusting according to at least one of the operating temperatures. 5. Gate means for transmitting a signal having a logic corresponding to the logic of the input signal to a first node in response to an output enable signal and an input signal, and in response to an output of the gate means, A first drive element for driving the output node to a potential level corresponding to the logic of the input signal at a first speed; a delay means for delaying the output of the gate means; and a delay means for responding to the output of the delay means. A second driving element for driving the output node to a potential level corresponding to the logic of the input signal at a speed higher than the first speed, and the output enable signal and the input signal being output. An output circuit that adjusts the delay time of the delay unit according to the output instruction signal. 6. An output circuit for outputting a signal having a logic corresponding to an internal signal on an internal node to an output node, the output circuit comprising: a signal to be output to the output node in response to the internal signal. A drive transistor for transmitting a voltage on the reference power supply node from a reference power supply node supplying a logic voltage to the output node; and a signal output to the output node, which is coupled between the voltage supply source and the reference power supply node. A first current supply element having a first current driving force, which conducts in response to an output permission signal that gives a timing; and a first current supply element coupled between the voltage supply source and the reference power supply node. An output circuit comprising a second current supply element having a second current driving force larger than the first current driving force, which is responsive in response to conduction after the first current supplying element. 7. An output circuit for transmitting a voltage on a reference power supply node to an output node in response to an internal signal on an internal node, wherein the output circuit responds to the internal signal from the reference power supply node to the output node. A drive transistor for transmitting a voltage; a variable delay means; a gate means for outputting a signal which becomes active after a delay time set by the variable delay means in response to the internal signal; the internal signal; A delay time adjusting means for setting a delay time of the variable delay means of the gate means in response to an output instruction signal indicating that the signal is a signal to be output; and a reference voltage supply source and the reference power supply node. A first current supply element having a first current driving capability, which is connected between the first current supply element and the second current supply element and which is conductive in response to the internal signal, and is coupled between the reference voltage supply source and the reference power supply node. Is made conductive upon activation of the output signal of said gate means,
And a second current supply element having a second current driving force larger than the first current driving force. 8. The drive transistor transmits a voltage of one of binary logics to the output node, and the reference voltage supply source supplies a voltage of the one logic to the second current supply element. A first source for providing a voltage; and a second source for providing a voltage closer to the other logic of the binary logic than the voltage on the first voltage source to the first current supply element. Item 6. The output circuit according to Item 6 or 7. 9. An output circuit for transmitting a signal of a logic corresponding to the logic of the internal signal to an output node in response to an internal signal on the internal node, the threshold voltage being different from each other and the substrate regions being different from each other. A plurality of insulated gate field effect transistors that have at least one characteristic of a bias voltage and are provided in parallel with each other between the output node and the corresponding logic voltage supply node; and in response to the internal signal, An activation means is provided for sequentially turning on a plurality of insulated gate field effect transistors in the order of increasing absolute value of the threshold voltage or insulative gate type field effect transistors with increasing absolute value of the substrate region bias voltage. , Output circuit. 10. In response to an internal signal on the output node,
An output circuit for transmitting a signal of a logic corresponding to the logic of the internal signal onto an output node, a resistance element coupled to the output node, a voltage supply for supplying a voltage of the logic corresponding to the resistance element. A first drive transistor connected between the node and a node, the first drive transistor being conductive in response to the internal signal; and the resistor element being a predetermined time after the first drive transistor is conductive in response to the internal signal. An output circuit comprising a switching element that short-circuits. 11. A plurality of resistance elements having different resistance values connected in parallel between an output node and a voltage supply node of the first logic, each of the plurality of resistance elements and the voltage supply node. A plurality of drive transistors coupled to each other, and activation control means for sequentially turning on the drive transistors connected to the resistance element having a larger resistance value among the plurality of resistance elements in response to the internal signal. An output circuit provided. 12. An output circuit for transmitting a signal of a logic corresponding to the logic of an internal signal onto an output node, comprising: an external power supply voltage supply node; and an external power supply voltage and temperature applied to the external power supply voltage supply node. A reference voltage generating unit that generates a constant reference voltage that does not depend on the external voltage, and a reference voltage from the reference voltage generating unit and the external power supply voltage have a positive dependency on temperature and a negative voltage on the external power supply voltage. Internal power supply voltage generating means for generating a dependent internal power supply voltage, and a voltage supplied from the internal power supply voltage generating means and supplied by the internal power supply voltage generating means to the output node in response to the internal signal. And output means for transmitting the signal to the output node. 13. A drive transistor transmitting a voltage on a first power supply node to an output node in response to an internal signal on an internal node, and a drive transistor activated in response to a clock signal giving an output timing of the internal signal. , A comparator for comparing a voltage on the first power supply node with a reference voltage, and a second power supply node coupled to the first power supply node for responding to an output signal of the comparator. An output circuit comprising: a transistor element that causes a current flow between the second power supply node and the first power supply node. 14. A bus amplifier for amplifying each signal on an internal signal bus having a plurality of bit widths in a parallel manner, and a signal for outputting a logic signal corresponding to each of the plurality of signals amplified by the bus amplifier to the outside. A plurality of output nodes, each of which is provided corresponding to each of the plurality of output nodes, each of which has a negative dependence on a distance between the bus amplifier and the corresponding output node; And a plurality of output circuits each having a time constant for buffering a corresponding signal of the bus amplifier and transmitting the buffered signal to a corresponding output node. 15. An output circuit for transmitting a signal of a logic corresponding to the logic of a signal on an internal node to an output pad via an output node and an output signal line, wherein the output signal line and a reference voltage supply node are connected to each other. A first drive element coupled between and driving the output signal line to a voltage level on the reference voltage supply node with a first current driving force in response to the internal signal; the output signal line and the reference; It is connected to a voltage supply node and is arranged closer to the output pad than the first drive element, and is turned on in response to the internal signal at a timing later than that of the first drive element. A second drive element for driving the output node to a voltage level on the reference voltage node with a second current driving force larger than the first current driving force. 16. An output circuit for transmitting a signal having a logic corresponding to the logic of a signal on an internal node to an output pad via an output node and an output signal line, wherein the output signal line and a reference voltage supply node are connected to each other. A first drive element coupled between the first drive element and the first drive element for driving the output signal line to a voltage level on the reference voltage node in response to the internal signal; and the output signal line and the reference voltage. The output signal is coupled to a supply node, is turned on in response to the internal signal at a timing later than that of the first drive element, and has a second current driving force larger than the first current driving force. A second drive element for driving the line to a voltage level on the reference voltage node; and a second drive element provided between the first drive element and the output pad for absorbing a noise voltage appearing on the output pad. An output circuit having an input protection means.